Rev. 1.10
94
November 26, 2019
Rev. 1.10
95
November 26, 2019
HT68FB240
USB Low Speed Flash MCU
6+2 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However,
in the 6+2 PWM Mode, each PWM cycle is subdivided into four individual sub-cycles known as
modulation cycle 0
~
modulation cycle 3, denoted as "i" in the table. Each one of these four sub-
cycles contains 64 clock cycles. In this mode, a modulation frequency increase by a factor of four
is achieved. The 8-bit PWM, PWM0, PWM1 or PWM
2
register value, which represents the overall
duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit
2~bit
7 is denoted here as the DC value. The second group which consists of bit
0~bit
1 is known
as the AC value. In the 6+2 PWM mode, the duty cycle value of each of the four modulation sub-
cycles is shown in the following table.
The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation.
It is important to note how the single PWM cycle is subdivided into 4 individual modulation cycles,
numbered from 0~3 and how the AC value is related to the PWM value.
Parameter
AC (0~3)
DC (Duty Cycle)
Modulation cycle i
(i=0~3)
i < AC
(DC+1)/64
i ≥ AC
DC/64
6+2 PWM Mode
PWM Register for 6+2 Mode
