Holtek HT66F488, Manual, Page: 65 / 195

Rev. 1.21 64 �ove��e� ��� 2�1� Rev. 1.21 65 �ove��e� ��� 2�1�
HT66F488/HT66F489
A/D Flash MCU with EEPROM
HT66F488/HT66F489
A/D Flash MCU with EEPROM
Compact Type TM Register Description
Overall operation of each Compact TM is controlled using several registers. A read only register
pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store
the internal 10-bit CCRA value. The remaining two registers are control registers which setup the
different operating and control modes as well as the three CCRP bits.
Register
Name
Bit
7 6 5 4 3 2 1 0
CTMC� CTPAU CTCK2 CTCK1 CTCK� CTO� CTRP2 CTRP1 CTRP�
CTMC1 CTM1 CTM� CTIO1 CTIO� CTOC CTPOL CTDPX CTCCLR
CTMDL D� D6 D5 D4 D3 D2 D1 D�
CTMDH — — — — — — D� D8
CTMAL D� D6 D5 D4 D3 D2 D1 D�
CTMAH — — — — — — D� D8
Compact TM Register List
CTMC0 Register
Bit 7 6 5 4 3 2 1 0
�a�e CTPAU CTCK2 CTCK1 CTCK� CTO� CTRP2 CTRP1 CTRP�
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR � � � � � � � �
Bit 7
CTPAU
: CTM Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6 ~ 4
CTCK2 ~ CTCK0
: Select CTM Counter clock
000: f
SYS
/4
001: f
SYS
010: f
H
/16
011: f
H
/64
100: f
TBC
101: f
TBC
110: CTCK rising edge clock
111: CTCK falling edge clock
These three bits are used to select the clock source for the CTM. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
f
SYS
is the system clock, while f
H
and f
TBC
are other internal clocks, the details of which
can be found in the oscillator section.
Bit 3
CTON
: CTM Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset to
zero, however when the bit changes from high to low, the internal counter will retain
its residual value until the bit returns high again.