Rev. 1.40
66
March 29, 2019
Rev. 1.40
67
March 29, 2019
HT45F23A/HT45F24A
TinyPower
TM
Flash MCU with OPA & Comparators
HT45F23A/HT45F24A
TinyPower
TM
Flash MCU with OPA & Comparators
Timer Control Registers – TMR0C, TMR1C
The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in
four different modes, the options of which are determined by the contents of their respective control
register.
It is the Timer Control Register together with its corresponding timer registers that control the
full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the
appropriate Timer Control Register is fully programmed with the right data to ensure its correct
operation, a process that is normally carried out during program initialisation.
To choose which of the four modes the timer is to operate in, either in the timer mode, the external
event counting mode, the internal event counter mode, or the pulse width measurement mode, bits 7
and 6 of the Timer Control Register, which are known as the bit pair T0M1/T0M0 or T1M1/T1M0
respectively, depending upon which timer is used, must be set to the required logic levels. The timer-
on bit, which is bit 4 of the Timer Control Register and known as T0ON or T1ON, depending upon
which timer is used, provides the basic on/off control of the respective timer. Setting the bit high
allows the counter to run, clearing the bit stops the counter. For timers that have prescalers, bits 0~2
of the Timer Control Register determine the division ratio of the input clock prescaler. The prescaler
bit settings have no effect if an external clock source is used. If the timer is in the event count or
pulse width measurement mode, the active transition edge level type is selected by the logic level of
bit 3 of the Timer Control Register which is known as T0E or T1E depending upon which timer is
used. An additional T1S bit in the TMR1C register is used to determine the clock source for Timer/
Event Counter 1.
Configuring the Timer Mode
In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an
internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the
Operating Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer Control Register must be
set to the correct value as shown.Control Register Operating Mode Select Bits for the Timer Mode
Bit7
Bit6
1
0
In this mode the internal clock, f
SYS
, is used as the internal clock for 8-bit Timer/Event Counter 0
and f
SUB
or f
SYS
/4 is used as the internal clock for 16-bit Timer/Event Counter 1. However, the clock
source, f
SYS
, for 8-bit timer is further divided by a prescaler, the value of which is determined by the
Prescaler Rate Select bits T0PSC2~T0PSC0, which are bits 2~0 in the Timer Control Register. After
the other bits in the Timer Control Register have been setup, the enable bit T0ON or T1ON, which is
bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. Each
time an internal clock cycle occurs, the Timer/Event Counter increments by one. When it is full and
overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already
loaded into the preload register and continue counting. The interrupt can be disabled by ensuring
that the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC0, is reset
to zero.
Timer Mode Timing Chart