
Rev. 1.00
407 of 486
July 31, 2018
32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
19 Inter-Integrated Circuit (I2C)
Bits
Field
Descriptions
[2]
GCEN
General Call Enable
0: General call is disabled
1: General call is enabled
When the device receives the calling address with a value of 0x00 and if both
the GCEN and the AA bits are set to 1, then the I
2
C interface is addressed as a
slave and the GCS bit in the I2CSR register is set to 1. When the I2CEN bit is
cleared to 0, the GCEN bit is automatically cleared to 0 by hardware.
[1]
STOP
STOP Condition Control
0: No action
1: Send a STOP condition in master mode
This bit is set to 1 by software to generate a STOP condition and automatically
cleared to 0 by hardware. The STOP bit is only available for the master device.
[0]
AA
Acknowledge Bit
0: Send a Not Acknowledge (NACK) signal after a byte is received
1: Send an Acknowledge (ACK) signal after a byte is received
When the I2CEN bit is cleared to 0, the AA bit is automatically cleared to 0 by
hardware.
I
2
C Interrupt Enable Register – I2CIER
This register specifies the corresponding I
2
C interrupt enable bits.
Offset:
0x004
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
Reserved
Type/Reset
23
22
21
20
19
18
17
16
Reserved
RXBFIE
TXDEIE
RXDNEIE
Type/Reset
RW 0 RW 0 RW 0
15
14
13
12
11
10
9
8
Reserved
TOUTIE BUSERRIE RXNACKIE ARBLOSIE
Type/Reset
RW 0 RW 0 RW 0 RW 0
7
6
5
4
3
2
1
0
Reserved
GCSIE
ADRSIE
STOIE
STAIE
Type/Reset
RW 0 RW 0 RW 0 RW 0
Bits
Field
Descriptions
[18]
RXBFIE
RX Buffer Full Interrupt Enable Bit
0: Interrupt is disabled
1: Interrupt is enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
[17]
TXDEIE
Data Register Empty Interrupt Enable Bit in Transmitter Mode
0: Interrupt is disabled
1: Interrupt is enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.