Rev. 1.00
148
October 26, 2018
Rev. 1.00
149
October 26, 2018
BS86DH12C
High Voltage Touch A/D Flash MCU with HVIO
BS86DH12C
High Voltage Touch A/D Flash MCU with HVIO
last break character and subsequently send out one or two stop bits. The automatic logic highs at the
end of the last break character will ensure that the start bit of the next frame is recognized.
UART Receiver
The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word
length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the
receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which
is received on the RX external input pin is sent to the data recovery block. The data recovery block
operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the
baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the
receive data register, if the register is empty. The data which is received on the external RX input pin
is sampled three times by a majority detect circuit to determine the logic level that has been placed
onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly
mapped into the Data Memory area and as such is not available to the application program for direct
read/write operations.
Receiving Data
When the UART receiver is receiving data, the data is serially shifted in on the external RX input
pin, LSB first. In the read mode, the TXR_RXR register forms a buffer between the internal bus
and the receiver shift register. The TXR_RXR register is a two byte deep FIFO data buffer, where
two bytes can be held in the FIFO while a third byte can continue to be received. Note that the
application program must ensure that the data is read from TXR_RXR before the third byte has been
completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be
subsequently indicated. The steps to initiate a data transfer can be summarized as follows:
• Make the correct selection of BNO, PRT and PREN bits to define the word length, parity type.
• Configure the BRG register to select the desired baud rate.
• Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin.
At this point the receiver will be enabled which will begin to look for a start bit.
When a character is received the following sequence of events will occur:
• The RXIF bit in the USR register will be set when the TXR_RXR register has data available.
There will be at most one more character available before an overrun error occurs.
• When the contents of the shift register have been transferred to the TXR_RXR register, then if
the RIE bit is set, an interrupt will be generated.
• If during reception, a frame error, noise error, parity error, or an overrun error has been detected,
then the error flags can be set.
The RXIF bit can be cleared using the following software sequence:
1. A USR register access
2. A TXR_RXR register read execution
Receive Break
Any break character received by the UART will be managed as a framing error. The receiver will
count and expect a certain number of bit times as specified by the values programmed into the BNO
bit plus one stop bit. If the break is much longer than 13 bit times, the reception will be considered
as complete after the number of bit times specified by BNO plus one stop bit. The RXIF bit is set,
FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate
and the RIDLE bit is set. A break is regarded as a character that contains only zeros with the FERR
flag set. If a long break signal has been detected, the receiver will regard it as a data frame including