Control Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
SMOD Register
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
D4
LTO
HTO
IDLEN
HLCLK
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
POR
0
0
0
0
0
0
1
1
Bit 7~5
CKS2~CKS0
: The system clock selection when HLCLK is
²
0
²
000: f
L
(f
LIRC
)
001: f
L
(f
LIRC
)
010: f
H
/64
011: f
H
/32
100: f
H
/16
101: f
H
/8
110: f
H
/4
111: f
H
/2
These three bits are used to select which clock is used as the system clock source. In addition
to the system clock source, which is LIRC, a divided version of the high
speed system oscillator can also be chosen as the system clock source.
Bit 4
Undefined bit
This bit can be read or written by user software program.
Bit 3
LTO
: Low speed system oscillator ready flag
0: not ready
1: ready
This is the low speed system oscillator ready flag which indicates when the low speed system
oscillator is stable after power on reset.
Bit 2
HTO
: High speed system oscillator ready flag
0: not ready
1: ready
This is the high speed system oscillator ready flag which indicates when the high speed system
oscillator is stable. This flag is cleared to
²
0
²
by hardware when the device is powered on and
then changes to a high level after the high speed system oscillator is stable. Therefore this flag
will always be read as
²
1
²
by the application program after device power-on. The flag will be
low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to
a high level after 15~16 clock cycles.
Bit 1
IDLEN
: IDLE Mode control
0: disable
1: enable
This is the IDLE Mode Control bit and determines what happens when the HALT instruction is
executed. If this bit is high, when a HALT instruction is executed the device will enter the
IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to
keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU
and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the
SLEEP Mode when a HALT instruction is executed.
Bit 0
HLCLK
: system clock selection
0: f
H
/2 ~ f
H
/64 or f
L
1: f
H
This bit is used to select if the f
H
clock or the f
H
/2 ~ f
H
/64 or f
L
clock is used as the system
clock. When the bit is high the f
H
clock will be selected and if low the f
H
/2 ~ f
H
/64 or f
L
clock will
be selected. When system clock switches from the f
H
clock to the f
L
clock and the f
H
clock will
be automatically switched off to conserve power.
BS83B08-3/B12-3/B16-3/B16G-3/C24-3
8-Bit Touch Key Flash MCU
Rev. 1.50
39
April 28, 2020
