System Architecture
A key factor in the high-performance features of the Holtek range of microcontroller is attributed to
their internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontroller providing increased speed of operation and enhanced performance. The
pipelining scheme is implemented in such a way that instruction fetching and instruction execution are
overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or
call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries
out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The
internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal
registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple
addressing methods of these registers along with additional architectural features ensure that a
minimum of external components is required to provide a functional I/O control system with
maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume
production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a high or low speed oscillator is subdivided into four
internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the
beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one
instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the contents
of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction
will take one more instruction cycle to execute.
Rev. 1.50
18
April 28, 2020
BS83B08-3/B12-3/B16-3/B16G-3/C24-3
8-Bit Touch Key Flash MCU
F e t c h I n s t . ( P C )
E x e c u t e I n s t . ( P C - 1 )
F e t c h I n s t . ( P C + 1 )
E x e c u t e I n s t . ( P C )
F e t c h I n s t . ( P C + 2 )
E x e c u t e I n s t . ( P C + 1 )
P C
P C + 1
P C + 2
f
S Y S
( S y s t e m C l o c k )
P h a s e C l o c k T 1
P r o g r a m C o u n t e r
P h a s e C l o c k T 2
P h a s e C l o c k T 3
P h a s e C l o c k T 4
P i p e l i n i n g
System Clocking and Pipelining
F e t c h I n s t . 1
E x e c u t e I n s t . 1
F e t c h I n s t . 2
F l u s h P i p e l i n e
1
2
3
4
5
6
D E L A Y :
M O V A , [ 1 2 H ]
C A L L D E L A Y
C P L [ 1 2 H ]
:
:
N O P
E x e c u t e I n s t . 2
F e t c h I n s t . 3
F e t c h I n s t . 6
E x e c u t e I n s t . 6
F e t c h I n s t . 7
Instruction Fetching
