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Mnemonic

Description

Cycles

Flag Affected

Bit Operation

CLR [m].i
SET [m].i

Clear bit of Data Memory
Set bit of Data Memory

1

Note

1

Note

None
None

Branch

JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI

Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt

2

1

Note

1

note

1

Note

1

Note

1

Note

1

Note

1

Note

1

Note

2
2
2
2

None
None
None
None
None
None
None
None
None
None
None
None
None

Table Read

TABRDC [m]
TABRDL [m]

Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory

2

Note

2

Note

None
None

Miscellaneous

NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT

No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode

1

1

Note

1

Note

1
1
1

1

Note

1
1

None
None
None

TO, PDF
TO, PDF
TO, PDF

None
None

TO, PDF

Note:

1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,

if no skip takes place only one cycle is required.

2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.

3. For the

²

CLR WDT1

²

and

²

CLR WDT2

²

instructions the TO and PDF flags may be affected by the

execution status. The TO and PDF flags are cleared after both

²

CLR WDT1

²

and

²

CLR WDT2

²

instructions

are consecutively executed. Otherwise the TO and PDF flags remain unchanged.

BS83B08-3/B12-3/B16-3/B16G-3/C24-3
8-Bit Touch Key Flash MCU

Rev. 1.50

115

April 28, 2020

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Summary of Contents for BS83B08-3

Page 1: ...8 Bit Touch Key Flash MCU BS83B08 3 BS83B12 3 BS83B16 3 BS83B16G 3 BS83C24 3 Revision 1 50 Date April 28 2020 ...

Page 2: ... Reset Characteristics 14 Oscillator Temperature Frequency Characteristics 15 System Architecture 18 Clocking and Pipelining 18 Program Counter 19 Stack 19 Arithmetic and Logic Unit ALU 20 Flash Program Memory 20 Structure 20 Special Vectors 21 Look up Table 21 Table Program Example 22 In Circuit Programming 23 RAM Data Memory 24 Structure 24 Special Function Register Description 24 Indirect Addre...

Page 3: ...or LIRC 37 Operating Modes and System Clocks 38 System Clocks 38 Control Register 39 System Operation Modes 40 Operating Mode Switching 41 NORMAL Mode to SLOW Mode Switching 42 SLOW Mode to NORMAL Mode Switching 42 Entering the SLEEP Mode 42 Entering the IDLE0 Mode 43 Entering the IDLE1 Mode 43 Standby Current Considerations 43 Wake up 44 Programming Considerations 44 Watchdog Timer 45 Watchdog Ti...

Page 4: ...h Key Structure 75 Touch Key Register Definition 76 Touch Key Operation 79 Touch Key Interrupt 80 Programming Considerations 80 Serial Interface Module SIM 81 SPI Interface 81 I2 C Interface 87 Interrupts 96 Interrupt Registers 96 Interrupt Register Contents 97 Interrupt Operation 104 External Interrupt 107 Multi function Interrupt 107 Time Base Interrupts 108 Timer Event Counter Interrupt 109 EEP...

Page 5: ... pin NSOP 150mil Outline Dimensions 127 16 pin SSOP 150mil Outline Dimensions 128 20 pin SOP 300mil Outline Dimensions 129 20 pin SSOP 150mil Outline Dimensions 130 24 pin SOP 300mil Outline Dimensions 131 24 pin SSOP 150mil Outline Dimensions 132 28 pin SOP 300mil Outline Dimensions 133 28 pin SSOP 150mil Outline Dimensions 134 44 pin LQFP 10mm 10mm FP2 0mm Outline Dimensions 135 Contents Rev 1 5...

Page 6: ...LOW IDLE and SLEEP All instructions executed in one or two instruction cycles Table read instructions 63 powerful instructions Up to 8 subroutine nesting levels Bit manipulation instruction Peripheral Features Flash Program Memory up to 4K 16 RAM Data Memory 160 8 512 8 EEPROM Memory up to 128 8 Watchdog Timer function Up to 41 bidirectional I O lines External interrupt line shared with I O pin Si...

Page 7: ... different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption Easy communication with the outside world is provided using the internal I2 C and SPI interfaces while the inclusion of flexible I O programming features Timer Event Counters and many other features further enhance device functionality and flexibility These touch key devices will f...

Page 8: ...E Y 3 P B 3 K E Y 4 P B 4 K E Y 5 P B 5 K E Y 6 P B 6 K E Y 7 P B 7 K E Y 8 P C 0 K E Y 9 P C 1 K E Y 1 0 P C 2 K E Y 1 1 P C 3 K E Y 1 2 P A 1 S D O P A 4 I N T P A 3 S C S P A 0 S D I S D A P A 2 S C K S C L R E S V D D V S S P C 7 K E Y 1 6 P C 6 K E Y 1 5 P C 5 K E Y 1 4 P C 4 K E Y 1 3 B S 8 3 B 1 6 3 2 4 S O P A S S O P A 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 2 3 4 5 6 7 ...

Page 9: ... up SCS SIMC0 ST CMOS SPI slave select PA4 INT PA4 PAWU PAPU ST CMOS General purpose I O Register enabled pull up and wake up INT INTEG ST External interrupt PB0 KEY1 PB3 KEY4 PB0 PB3 PBPU ST CMOS General purpose I O Register enabled pull up KEY1 KEY4 TKM0C1 NSI Touch key inputs PB4 KEY5 PB7 KEY8 PB4 PB7 PBPU ST CMOS General purpose I O Register enabled pull up KEY5 KEY8 TKM1C1 NSI Touch key input...

Page 10: ... inputs PC0 KEY9 PC3 KEY12 PC0 PC3 PCPU ST CMOS General purpose I O Register enabled pull up KEY9 KEY12 TKM2C1 NSI Touch key inputs PC4 KEY13 PC7 KEY16 PC4 PC7 PCPU ST CMOS General purpose I O Register enabled pull up KEY13 KEY16 TKM3C1 NSI Touch key inputs PD0 KEY17 PD3 KEY20 PD0 PD3 PDPU ST CMOS General purpose I O Register enabled pull up KEY17 KEY20 TKM4C1 NSI Touch key inputs PD4 KEY21 PD7 KE...

Page 11: ...SDI SDA 961 020 658 000 29 PB6 KEY7 152 880 677 500 11 PA3 SCS 1056 020 658 000 30 PB7 KEY8 275 880 677 500 12 PA4 INT 1151 020 658 000 31 PC0 KEY9 398 880 677 500 13 PA1 SDO 1246 020 658 000 32 PC1 KEY10 521 880 677 500 14 Dummy 1341 020 658 000 33 PC2 KEY11 644 880 677 500 15 Align2 1361 400 559 990 34 PC3 KEY12 767 880 677 500 16 Dummy 1327 340 677 500 35 PC4 KEY13 890 880 677 500 17 Dummy 1247...

Page 12: ...H 3V No load fH 8MHz WDT enable 1 2 1 8 mA 5V 2 2 3 3 mA 3V No load fH 12MHz WDT enable 1 6 2 4 mA 5V 3 3 5 0 mA 5V No load fH 16MHz WDT enable 4 0 6 0 mA IDD2 Operating Current LIRC fSYS fL for BS83B08 3 B12 3 B16 3 3V No load fL 32kHz WDT enable 50 100 mA 5V 70 150 mA IDD3 Operating Current LIRC fSYS fL for BS83C24 3 3V No load fL 32kHz WDT enable 15 30 mA 5V 30 60 mA IIDLE0 IDLE0 Mode Standby C...

Page 13: ... DC 8 MHz 2 7V 5 5V DC 12 MHz 4 5V 5 5V DC 16 MHz fHIRC System Clock HIRC 3V 5V Ta 25 C 2 8 2 MHz 3V 5V Ta 25 C 2 12 2 MHz 5V Ta 25 C 2 16 2 MHz 3V 5V Ta 0 70 C 4 8 3 MHz 3V 5V Ta 0 70 C 4 12 3 MHz 5V Ta 0 70 C 4 16 3 MHz 2 5V 4 0V Ta 0 70 C 9 8 6 MHz 3 0V 5 5V Ta 0 70 C 5 8 12 MHz 2 7V 4 0V Ta 0 70 C 9 12 5 MHz 3 0V 5 5V Ta 0 70 C 5 12 11 MHz 4 5V 5 5V Ta 0 70 C 5 16 5 MHz 2 5V 4 0V Ta 40 C 85 C ...

Page 14: ...S fSYS LIRC 1 2 Note 1 tSYS 1 fSYS 2 To maintain the accuracy of the internal HIRC oscillator frequency a 0 1mF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible Power on Reset Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VPOR VDD Start Voltage to Ensure Power on Reset 100 mV RPOR AC VDD Raising R...

Page 15: ...exceeding the specified operating range are shown for information purposes only The device will operate properly only within the specified range BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU Rev 1 50 15 April 28 2020 Internal RC 8MHz 3V 7 300 7 400 7 500 7 600 7 700 7 800 7 900 8 000 8 100 8 200 8 300 60 40 20 0 20 40 60 80 100 120 140 Ta C f SYS MHz 2 5V 2 7V 3 0V 4 0V Internal RC ...

Page 16: ...10 800 11 000 11 200 11 400 11 600 11 800 12 000 12 200 12 400 60 40 20 0 20 40 60 80 100 120 140 Ta C f SYS MHz 2 7V 3 0V 4 0V Internal RC 12MHz 5V 11 400 11 600 11 800 12 000 12 200 12 400 12 600 12 800 13 000 60 40 20 0 20 40 60 80 100 120 140 Ta C f SYS MHz 3 0V 4 0V 4 5V 4 75V 5 0V 5 25V 5 5V T a C T a C ...

Page 17: ... Bit Touch Key Flash MCU Rev 1 50 17 April 28 2020 Internal RC 16MHz 5V 15 300 15 400 15 500 15 600 15 700 15 800 15 900 16 000 16 100 16 200 16 300 16 400 60 40 20 0 20 40 60 80 100 120 140 Ta C f SYS MHz 4 5V 4 75V 5 0V 5 25V 5 5V T a C ...

Page 18: ...w speed oscillator is subdivided into four internally generated non overlapping clocks T1 T4 The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched The remaining T2 T4 clocks carry out the decoding and execution functions In this way one T1 T4 clock cycle forms one instruction cycle Although the fetching and execution of instructions take...

Page 19: ...nd is a readable and writeable register By transferring data directly into this register a short program jump can be executed directly however as only this low byte is available for manipulation the jumps are limited to the present page of memory that is 256 locations When such program jumps are executed it should also be noted that a dummy cycle will be inserted Manipulating the PCL register may ...

Page 20: ...es the Program Memory is Flash type which means it can be programmed and re programmed a large number of times allowing the user the convenience of code modification on the same device By using the appropriate programming tools these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating Structure...

Page 21: ...ransferred to the user defined Data Memory register m as specified in the instruction The higher order table data byte from the Program Memory will be transferred to the TBLH special register Any unused bits in this transferred higher order byte will be read as 0 The accompanying diagram illustrates the addressing data flow of the look up table BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Fl...

Page 22: ...ing the table read instructions the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine As a rule it is recommended that simultaneous use of the table read instructions should be avoided However in situations where simultaneous use cannot be avoided the interrupts should be disabled prior to the execution of any main routine t...

Page 23: ...S VSS Ground The Program Memory and EEPROM data memory can both be programmed serially in circuit using this 5 wire interface Data is downloaded and uploaded serially on a single pin with an additional line for the clock Two additional lines are required for the power supply and one line for the reset The technical details regarding the in circuit programming of the devices are beyond the scope of...

Page 24: ...achieved by setting the Bank Pointer to the correct value The start address of the Data Memory for all devices is the address 00H Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section however several registers require a separate description in this section Indirect Addressing Registers IAR0 IAR1 The Indirect Address...

Page 25: ...I M C 1 S I M D S I M A S I M C 2 T K M 0 1 6 D H T K M 0 1 6 D L R e s e r v e d R e s e r v e d T K M 0 C 0 T K M 0 C 1 T K M 0 C 2 T K M 0 C 3 B S 8 3 B 0 8 3 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 ...

Page 26: ... 1 C 0 T K M 1 C 1 T K M 1 C 2 T K M 1 C 3 P C P C C P C P U U n u s e d U n u s e d C T R L U n u s e d U n u s e d U n u s e d E E C U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d T K M 2 1 6 D H T K M 2 1 6 D L R e s e r v e d R e s e r v e d T K M 2 C 0 T K M 2 C 1 T K M 2 C 2 T K M 2 C 3 T K M 3 1 6 D H T K M 3 1 6 D L R e s e r v e d R e s e r v e d T K M...

Page 27: ...T K M 3 C 3 T K M 4 1 6 D H T K M 4 1 6 D L R e s e r v e d R e s e r v e d T K M 4 C 0 T K M 4 C 1 T K M 4 C 2 T K M 4 C 3 I A R 0 M P 0 I A R 1 M P 1 B P A C C P C L T B L P T B L H T B H P S T A T U S S M O D I N T C 3 I N T E G I N T C 0 I N T C 1 I N T C 2 M F I 0 M F I 1 M F I 2 P A P A C P A P U P A W U U n u s e d U n u s e d W D T C T B C T M R 0 T M R 0 C E E A E E D P B P B C P B P U I ...

Page 28: ... a offset adres1 Accumulator loaded with first RAM address mov mp0 a setup memory pointer with first RAM address loop clr IAR0 clear the data at address defined by MP0 inc mp0 increment memory pointer sdz block check if last memory location has been cleared jmp loop continue The important point to note here is that in the example shown above no reference is made to specific RAM addresses Bank Poin...

Page 29: ...rogram Counter Low Register PCL To provide additional program control functions the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory By manipulating this register direct jumps to other program locations are easily implemented Loading a value directly into this PCL register will cause a jump to the specified Program ...

Page 30: ...t if the result of an arithmetic or logical operation is zero otherwise Z is cleared OV is set if an operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa otherwise OV is cleared PDF is cleared by a system power up or executing the CLR WDT instruction PDF is set by executing the HALT instruction TO is cleared by a system power up or exec...

Page 31: ...PROM Data Memory capacity is 64 8 or 128 8 bits for this series of devices Unlike the Program Memory and RAM Data Memory the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 a...

Page 32: ...0 Bit 5 0 Data EEPROM address Data EEPROM address bit 5 bit 0 BS83C24 3 EEPROM Register List Name Bit 7 6 5 4 3 2 1 0 EEA D6 D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC WREN WR RDEN RD EEA Register Bit 7 6 5 4 3 2 1 0 Name D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W POR x x x x x x x x unknown Bit 7 unimplemented read as 0 Bit 6 0 Data EEPROM address Data EEPROM address bit 6 bit 0 ...

Page 33: ...disable 1 enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out Clearing this bit to zero will inhibit Data EEPROM read operations Bit 0 RD EEPROM read control 0 read cycle has finished 1 activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle This bit w...

Page 34: ...r by polling the WR bit in the EEC register or by using the EEPROM interrupt When the write cycle terminates the WR bit will be automatically cleared to zero by the microcontroller informing the user that the data has been written to the EEPROM The application program can therefore poll the WR bit to determine when the write cycle has ended Write Protection Protection against inadvertent write ope...

Page 35: ...mples Reading Data from the EEPROM Polling Method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A 040H setup memory pointer MP1 MOV MP1 A MP1 points to EEC register MOV A 01H setup Bank Pointer MOV BP A SET IAR1 1 set RDEN bit enable read operations SET IAR1 0 start Read Cycle set RD bit BACK SZ IAR1 0 check for read cycle end JMP BACK CLR IAR1 disable EEPROM read write CLR BP MOV A EEDATA...

Page 36: ...t in power sensitive portable applications Type Name Freq Internal High Speed HIRC 8 12 or 16MHz Internal Low Speed LIRC 32kHz Oscillator Types System Clock Configurations There are two methods of generating the system clock a high speed internal clock source and low speed internal clock source The high speed oscillator is an internal 8MHz 12MHz or 16MHz RC oscillator while the low speed oscillato...

Page 37: ...requency oscillator It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V requiring no external components for its implementation Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage temperature and process variations on the oscillation frequency are ...

Page 38: ...uency fL source and is selected using the HLCLK bit and CKS2 CKS0 bits in the SMOD register Both the high and low speed system clocks are sourced from internal RC oscillators Rev 1 50 38 April 28 2020 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU S L E E P T i m e B a s e c l o c k s o u r c e d i s a b l e d i n S l E E P M o d e H I R C 8 M H z 1 2 M H z 1 6 M H z H i g h S p e e ...

Page 39: ...then changes to a high level after the high speed system oscillator is stable Therefore this flag will always be read as 1 by the application program after device power on The flag will be low when in the SLEEP or IDLE0 Mode but after a wake up has occurred the flag will change to a high level after 15 16 clock cycles Bit 1 IDLEN IDLE Mode control 0 disable 1 enable This is the IDLE Mode Control b...

Page 40: ...o a mode where the microcontroller operates normally although now with the slow speed clock source Running the microcontroller in this mode allows it to run with much lower operating currents In the SLOW Mode the high speed clock is off SLEEP Mode The SLEEP Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is low In the SLEEP mode the CPU will be stopp...

Page 41: ...that clock source is switched from the high speed clock source fHIRC to the clock source fHIRC 2 fHIRC 64 or fLIRC If the clock is from fHIRC the high speed clock source will stop running to conserve power When this happens it must be noted that the fHIRC 16 and fHIRC 64 internal clock sources will also stop running The accompanying flowchart shows what happens when the device moves between the va...

Page 42: ...execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 0 When this instruction is executed under the conditions described above the following will occur The system clock will be stopped and the application program will stop at the HALT instruction but the fLIRC clock will be on The Data Memory contents and registers will maintain their present conditio...

Page 43: ... counting The I O ports will maintain their present conditions In the status register the Power Down flag PDF will be set and the Watchdog time out flag TO will be cleared Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible perhaps only in the order of several micro amps except in the I...

Page 44: ...ons may occur The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full in which case the program will resume execution at the instruction following the HALT instruction In this situation the interrupt which woke up the device will not be immediately serviced but will rather be serviced later when the related interrupt is finally enabled or when a stack...

Page 45: ...e 1 enable Bit 6 4 WS2 WS1 WS0 WDT time out period selection 000 256 fLIRC 001 512 fLIRC 010 1024 fLIRC 011 2048 fLIRC 100 4096 fLIRC 101 8192 fLIRC 110 16384 fLIRC 111 32768 fLIRC These three bits determine the division ratio of the Watchdog Timer source clock which in turn determines the timeout period Bit 3 0 Undefined bit These bits can be read or written by user software program Watchdog Time...

Page 46: ...Timer successive executions of this instruction will have no effect only the execution of a CLR WDT2 instruction will clear the Watchdog Timer Similarly after the CLR WDT2 instruction has been executed only a successive CLR WDT1 instruction can clear the Watchdog Timer For these devices the single CLR WDT instruction will have no effect so care must be taken not to use this instruction The maximum...

Page 47: ...allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high Another type of reset is when the Watchdog Timer overflows and resets the microcontroller All types of reset operations result in different register conditions being setup Another reset exists in the form of a Low Voltage Reset LVR where a full reset similar to the RES reset is implemented ...

Page 48: ...e Enhanced Reset Circuit shown is recommended More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website Pulling the RES Pin low using external hardware will also execute a device reset In this case as in the case of other resets the Program Counter will reset to zero and program execution initiated from this point The RES bit in the CTRL regist...

Page 49: ...tage i e a voltage in the range between 0 9V VLVR must exist for greater than the value tLVR specified in the A C characteristics If the low voltage state does not exceed tLVR the LVR will ignore it and will not perform a reset function One of a range of specified voltage values for VLVR can be selected using configuration options Watchdog Time out Reset during Normal Operation The Watchdog time o...

Page 50: ...chdog Timer The reset flags are shown in the table TO PDF RESET Conditions 0 0 Power on reset u u RES or LVR reset during NORMAL or SLOW Mode operation 1 u WDT time out reset during NORMAL or SLOW Mode operation 1 1 WDT time out reset during IDLE or SLEEP Mode operation Note u stands for unchanged The following table indicates the way in which the various components of the microcontroller are af f...

Page 51: ... 0 u u INTC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u INTC2 0 0 0 0 0 0 0 0 u u MFI0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u PAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u PAPU 0 0 0 0 ...

Page 52: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM116DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM116DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 53: ...1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u WDTC 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 u u u u u u u u TBC 0 0 0 0 0 0 0 0 u u TMR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TMRC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u ...

Page 54: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM1C3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u PCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u PCPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u CTRL x 0 0 0 0 1 0 0 0 0 1 0 0 0 0 u 0 0 0 0 u u u u u EEC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u TKM216DH 0 0 0 0 0 0 0 0 0 0...

Page 55: ... 1 1 1 1 1 1 u u u u u PAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u WDTC 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 u u u u u u u u TBC 0 0 0 0 0 0 0 0 u u TMR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TMRC 0 0 0 0 0 0 0 0...

Page 56: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTRL x 0 0 0 0 1 0 0 0 0 1 0 0 0 0 u 0 0 0 0 u u u u u EEC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u TKM216DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM216DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM2C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 57: ... u u u u u INTC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u MFI0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u MFI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u MFI2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PA 1 1 1 1 1 1 1 1 1 1 u u u u u PAC 1 1 1 1 1 1 1 1 1 1 u u u u u PAPU 0 0 0 0 0 0 0 0 0 0 u u u u u PAWU 0 0 0 0 0 0 0 0 0 0 u u u u u WDTC 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 u ...

Page 58: ...L x 0 0 0 0 u 0 0 0 0 u u u u u PD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u PDC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u PDPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u PEC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u PEPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM216DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u...

Page 59: ... 0 0 0 0 0 u u u u u u u u TKM5C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM5C2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM5C3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PF 1 1 1 1 1 1 1 1 u u u u PFC 1 1 1 1 1 1 1 1 u u u u PFPU 0 0 0 0 0 0 0 0 u u u u TMR1H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TMR1L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TMR1C 0 0 0 0 1 ...

Page 60: ... For input operation these ports are non latching which means the inputs must be ready at the T2 rising edge of instruction MOV A m where m denotes the port address For output operation all the data is latched and remains unchanged until the output latch is rewritten I O Register List BS83B08 3 Register Name Bit 7 6 5 4 3 2 1 0 PAWU D4 D3 D2 D1 D0 PAPU D4 D3 D2 D1 D0 PA D4 D3 D2 D1 D0 PAC D4 D3 D2...

Page 61: ...AWU D4 D3 D2 D1 D0 PAPU D4 D3 D2 D1 D0 PA D4 D3 D2 D1 D0 PAC D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 PDPU D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PEPU D7 D6 D5 D4 D3 D2 D1 D0 PE D7 D6 D5 D4 D3 D2 D1 D0 PEC D7 D6 D5 D4 ...

Page 62: ... as 0 Bit 4 0 PAPU Port A bit 4 bit 0 pull high control 0 disable 1 enable PBPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 PBPU Port B bit 7 bit 0 pull high control 0 disable 1 enable PCPU Register BS83B12 3 Bit 7 6 5 4 3 2 1 0 Name D3 D2 D1 D0 R W R W R W R W R W POR 0 0 0 0 Bit 7 4 unimplemented read as 0 Bit 3 0 PCPU...

Page 63: ... preserves power a feature that is important for battery and other low power applications Various methods exist to wake up the microcontroller one of which is to change the logic condition on one of the Port Apins from high to low This function is especially suitable for applications that can be woken up via external switches Each pin on Port A can be selected individually to have this wake up fea...

Page 64: ... is written as a 0 the I O pin will be setup as a CMOS output If the pin is currently setup as an output instructions can still be used to read the output register However it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin PAC Register Bit 7 6 5 4 3 2 1 0 Name D4 D3 D2 D1 D0 R W R W R W R W R W R W POR 1 ...

Page 65: ...CC Port C bit 7 bit 0 input output control 0 output 1 input PDC Register BS83C24 3 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 1 1 1 1 1 1 1 1 Bit 7 0 PDC Port D bit 7 bit 0 input output control 0 output 1 input PEC Register BS83C24 3 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 1 1 1 1 1 1 1 1 Bit 7 0 PEC Por...

Page 66: ...grammed Selecting which pins are inputs and which are outputs can be achieved byte wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the SET m i and CLR m i instructions Note that when using these bit control instructions a read modify write operation takes place The microcontroller must first read in ...

Page 67: ...he timer clock source can also be configured to come from an external timer pin The accompanying table illustrates the Timer Type list for the devices Device Timer Type Timer Register Name Timer Control Register Name Time Operating Modes BS83B08 3 BS83B12 3 BS83B16 3 BS83B16G 3 8 bit TMR TMRC Timer Mode BS83C24 3 8 bit TMR0 TMRC0 Timer Mode 16 bit TMR1L TMR1H TMRC1 Timer Mode Event Counter Mode Pu...

Page 68: ...n Note that if the Timer Event Counter is in an OFF condition and data is written to its preload register this data will be immediately written into the actual counter However if the counter is enabled and counting any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occ...

Page 69: ...nimplemented read as 0 Bit 5 TS Timer Event Counter Clock Source 0 fSYS 1 fLIRC Bit 4 TON Timer Event Counter Counting Enable 0 disable 1 enable Bit 3 unimplemented read as 0 Bits 2 0 TPSC2 TPSC0 Timer prescaler rate selection Timer internal clock 000 fTP 001 fTP 2 010 fTP 4 011 fTP 8 100 fTP 16 101 fTP 32 110 fTP 64 111 fTP 128 BS83C24 3 Bit 7 6 5 4 3 2 1 0 Name T0S T0ON T0PSC2 T0PSC1 T0PSC0 R W ...

Page 70: ...ch is determined by the bits TPSC2 TPSC0 or T0PSC2 T0PSC0 in the Timer Control Register The timer on bit TON or T0ON must be set high to enable the timer to run Each time an internal clock high to low transition occurs the timer increments by one when the timer is full and overflows an interrupt signal is generated and the timer will reload the value already loaded into the preload register and co...

Page 71: ...mer Control Register is low the Timer Event Counter will increment each time the external timer pin receives a low to high transition If the T1EG is high the counter will increment each time the external timer pin receives a high to low transition When it is full and overflows an interrupt signal is generated and the Timer Event Counter will reload the value already loaded into the preload registe...

Page 72: ... signal on the external timer pin returns to its original level whereas in the other two modes the enable bit can only be reset to zero under program control The residual value in the Timer Event Counter which can now be read by the program therefore represents the length of the pulse received on the TC1 pin As the enable bit has now been reset any further transitions on the external timer pin wil...

Page 73: ... precise values of frequency can be generated I O Interfacing The Timer Event Counter when configured to run in the event counter or pulse width capture mode requires the use of an external timer pin for its operation As this pin is a shared pin it must be configured correctly to ensure that it is setup for use as a Timer Event Counter input pin This is achieved by ensuring that the mode select bi...

Page 74: ... an interrupt signal However irrespective of whether the interrupts are enabled or not a Timer Event Counter overflow will also generate a wake up signal if the device is in a Power down condition This situation may occur if the Timer Event Counter is in the Event Counting Mode and if the external signal continues to change state In such a case the Timer Event Counter will continue to count these ...

Page 75: ...dule number M0 to M5 Each module contains its own control logic circuits and register set Examination of the register names will reveal the module number it is referring to Device Keys n Touch Key Module Touch Key Shared I O Pin BS83B08 3 8 M0 K1 K4 PB0 PB3 M1 K5 K8 PB4 PB7 BS83B12 3 12 M0 K1 K4 PB0 PB3 M1 K5 K8 PB4 PB7 M2 K9 K12 PC0 PC3 BS83B16 3 BS83B16G 3 16 M0 K1 K4 PB0 PB3 M1 K5 K8 PB4 PB7 M2...

Page 76: ...ntrol Register 3 Counter overflow bits Reference Oscillator Overflow Time Select Register Listing Register Name Bit 7 6 5 4 3 2 1 0 TKMn16DH D7 D6 D5 D4 D3 D2 D1 D0 TKMn16DL D7 D6 D5 D4 D3 D2 D1 D0 TKMnC0 MnMXS1 MnMXS0 D5 D4 D3 D2 D1 D0 TKMnC1 MnK4OEN MnK3OEN MnK2OEN MnK1OEN MnK4IO MnK3IO MnK2IO MnK1IO TKMnC2 Mn16CTON D6 MnST MnROEN MnRCCLR Mn16CTCLR D1 MnROS TKMnC3 D9 D8 MnRCOV Mn16CTOV D3 MnROVS...

Page 77: ...inary value 011000 TKMnC1 Register Bit 7 6 5 4 3 2 1 0 Name MnK4OEN MnK3OEN MnK2OEN MnK1OEN MnK4IO MnK3IO MnK2IO MnK1IO R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bits 7 4 MnK4OEN MnK1OEN key selector control MnK4OEN M0 M1 M2 M3 M4 M5 Key 4 Key 8 Key 12 Key 16 Key 20 Key 24 0 Disable 1 Enable MnK3OEN M0 M1 M2 M3 M4 M5 Key 3 Key 7 Key 11 Key 15 Key 19 Key 23 0 Disable 1 Enable MnK2OEN ...

Page 78: ...ed bit must not be modified Bit 5 MnST Time slot counter start control 0 time slot counter stopped 0 1 enable time slot counter When this bit changes from low to high the time slot counter will be enabled and the touch sense procedure started When the time slot counter has completed its counting an interrupt will be generated Bit 4 MnROEN Reference clock control 0 disable 1 enable Bit 3 MnRCCLR Ti...

Page 79: ...rnal sense oscillator touch actions can be sensed by measuring these frequency changes Using an internal programmable divider the reference clock is used to generate a fixed time period By counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined The device contains four touch key inputs which are shared with logical I O...

Page 80: ...ime slot counter flag will go high and remain high until the counter overflows When this happens an interrupt signal will be generated When the external touch key size and layout are defined their related capacitances will then determine the sensor oscillator frequency Rev 1 50 80 April 28 2020 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU C F Mux Mux Reference Clock Touch Key 1 Set...

Page 81: ...ve devices from a single master the master can use I O pin to select the slave devices SPI Interface Operation The SPI interface is a full duplex synchronous serial data link It is a four line interface with pin names SDI SDO SCK and SCS Pins SDI and SDO are the Serial Data Input and Serial Data Output lines SCK is the Serial Clock line and SCS is the Slave Select line As the SPI interface pins ar...

Page 82: ...ual data to be transmitted must be placed in the SIMD register After the data is received from the SPI bus the de vice can read it from the SIMD register Any transmission or reception of data from the SPI bus must be made via the SIMD register SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x unknown Rev 1 50 82 April 28 2020 B...

Page 83: ...k frequency The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0 If the SPI Slave Mode is selected then the clock will be supplied by an external Master device Bit 4 2 unimplemented read as 0 Bit 1 SIMEN SIM Control 0 disable 1 enable The bit is the overall on off control for the SIM interface When the SIMEN bit is cleared the SDI SDO SCK and SCS or SDA...

Page 84: ... be low when the clock is inactive When the CKPOLB bit is low then the SCK line will be high when the clock is inactive The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit Bit 3 MLS SPI Data shift order 0 LSB 1 MSB This is the data shift select bit and is used to select how the data is transferred either MSB or LSB first Setting the bit high will select MS...

Page 85: ...it The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits The SPI will continue to function even in the IDLE Mode BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU Rev 1 50 85 April 28 2020 S C K C K P O L B 1 S C K C K P O L B 0 S D O S C S S D I D a t a C a p t u r e D 7 D 0 D 6 D 1 D 5 D 2 D ...

Page 86: ... f i g u r e C K P O L B C K E G C S E N a n d M L S S I M 2 0 0 0 0 0 0 1 0 1 0 0 1 1 o r 1 0 0 S I M 2 0 1 0 1 N SPI Transfer Control Flowchart S C K C K P O L B 1 S C K C K P O L B 0 S D O S C S S D I D a t a C a p t u r e D 7 D 0 D 6 D 1 D 5 D 2 D 4 D 3 D 3 D 4 D 2 D 5 D 1 D 6 D 0 D 7 W r i t e t o S I M D S D O c h a n g e s a s s o o n a s w r i t i n g o c c u r s S D O i s f l o a t i n g ...

Page 87: ...he bidirectional I 2 C bus one is known as the master device and one as the slave device Both master and slave can transmit and receive data however it is the master device that has overall control of the bus For these devices which only operates in slave mode there are two methods of transferring data on the I2 C bus the slave transmit mode and the slave receive mode BS83B08 3 B12 3 B16 3 B16G 3 ...

Page 88: ...controller writes data to the I 2 C bus the actual data to be transmitted must be placed in the SIMD register After the data is received from the I 2 C bus the microcontroller can read it from the SIMD register Any transmission or reception of data from the I 2 C bus must be made via the SIMD register The SIM pins are pin shared with other I O pins and must be selected using the SIMEN bit in the S...

Page 89: ...t is the overall on off control for the SIM interface When the SIMEN bit is cleared the SDI SDO SCK and SCS or SDA and SCL lines will be as I O function and the SIM operating current will be reduced to a minimum value When the bit is high the SIM interface is enabled If the SIM is configured to operate as an SPI interface via the SIM2 SIM0 bits the contents of the SPI control registers will remain...

Page 90: ...n receive mode 1 Slave device should be in transmit mode The SRW flag is the I 2 C Slave Read Write flag This flag determines whether the master device wishes to transmit or receive data from the I 2 C bus When the transmitted address and slave address is match that is when the HAAS flag is set high the slave device will check the SRW flag to determine whether it should be in transmit mode or rece...

Page 91: ...ister SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x unknown SIMA Register Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x unknown Bit 7 1 IICA6 IICA0 I 2 C slave address IICA6 IICA0 is the I 2 C slave address bit 6 bit 0 The SIMA register is als...

Page 92: ... any transfer of data to or from the I 2 C bus the microcontroller must initialise the bus the following are steps to achieve this Step 1 Set the SIM2 SIM0 and SIMEN bits in the SIMC0 register to 1 to enable the I2 C bus Step 2 Write the slave address of the device to the I2 C bus address register SIMA Step 3 Set the SIME and SIM Muti Function interrupt enable bit of the interrupt control register...

Page 93: ...ead from the SIMD register to release the SCL line I 2 C Bus Read Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I 2 C bus or write data to the I2 C bus The slave device should examine this bit to determine if it is to be a transmitter or a receiver If the SRW flag is 1 then this indicates that the master device wishes to read data from...

Page 94: ... byte If the slave transmitter does not receive an acknowledge bit signal from the master receiver then the slave transmitter will release the SDAline to allow the master to send a STOP signal to release the I 2 C Bus The corresponding data will be stored in the SIMD register If setup as a transmitter the slave device must first write the data to be transmitted into the SIMD register If setup as a...

Page 95: ...ition as occurred The time out condition will also generate an interrupt which uses the I2 C interrrupt vector When an I 2 C time out occurs the I 2 C internal circuitry will be reset and the registers will be reset into the following condition Register After I 2 C Time out SIMDR SIMAR SIMC0 No change SIMC1 Reset to POR condition I2 C Registers After Time out The I2CTOF flag can be cleared by the ...

Page 96: ...Memory as shown in the accompanying table The number of registers depends upon the device chosen but fall into three categories The first is the INTC0 INTC3 registers which setup the primary interrupts the second is the MFI0 MFI2 registers which setup the Multi function interrupts Finally there is an INTEG register to setup the external interrupt trigger edge type Each register contains a number o...

Page 97: ...1 0 INTEG INTS1 INTS0 INTC0 TKM1F TKM0F INTF TKM1E TKM0E INTE EMI INTC1 TF MF0F DEF SIMF TE MF0E DEE SIME INTC2 TKM3F TKM2F MF1F TBF TKM3E TKM2E MF1E TBE MFI0 M116CTF D6 M016CTF D4 M116CTE D2 M016CTE D0 MFI1 M316CTF D6 M216CTF D4 M316CTE D2 M216CTE D0 BS83C24 3 Name Bit 7 6 5 4 3 2 1 0 INTEG INTS1 INTS0 INTC0 TKM1F TKM0F INTF TKM1E TKM0E INTE EMI INTC1 T0F MF0F DEF SIMF T0E MF0E DEE SIME INTC2 TKM...

Page 98: ...ented read as 0 Bit 6 TKM1F Touch key module 1 interrupt request flag 0 No request 1 interrupt request Bit 5 TKM0F Touch Key module 0 interrupt request flag 0 No request 1 Interrupt request Bit 4 INTF INT pin interrupt request flag 0 No request 1 Interrupt request Bit 3 TKM1E Touch key module 1 interrupt control 0 disable 1 enable Bit 2 TKM0E Touch key module 0 interrupt control 0 disable 1 enable...

Page 99: ...1 interrupt request Bit 5 DEF Data EEPROM interrupt request flag 0 no request 1 interrupt request Bit 4 SIMF SIM interrupt reqeust flag 0 no request 1 interrupt request Bit 3 TE Timer Event Counter interrupt control 0 disable 1 enable Bit 2 MF0E Multi function interrupt 0 control 0 disable 1 enable Bit 1 DEE Data EEPROM interrupt control 0 disable 1 enable Bit 0 SIME SIM interrupt control 0 disabl...

Page 100: ...st 1 interrupt request Bit 3 T0E Timer Event Counter 0 interrupt control 0 disable 1 enable Bit 2 MF0E Multi function interrupt 0 control 0 disable 1 enable Bit 1 DEE Data EEPROM interrupt control 0 disable 1 enable Bit 0 SIME SIM interrupt control 0 disable 1 enable INTC2 Register BS83B08 3 Bit 7 6 5 4 3 2 1 0 Name TBF TBE R W R W R W POR 0 0 Bit 7 5 unimplemented read as 0 Bit 4 TBF Time Base in...

Page 101: ...r BS83B16 3 BS83B16G 3 BS83C24 3 Bit 7 6 5 4 3 2 1 0 Name TKM3F TKM2F MF1F TBF TKM3E TKM2E MF1E TBE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 TKM3F Touch key module 3 interrupt request flag 0 No request 1 Interrupt request Bit 6 TKM2F Touch key module 2 interrupt request flag 0 No request 1 Interrupt request Bit 5 MF1F Multi function interrupt 1 request flag 0 No request 1 Inte...

Page 102: ...ol 0 disable 1 enable Bit 0 T1E Timer Event Counter 1 Interrupt Control 0 disable 1 enable MFI0 Register All devices Bit 7 6 5 4 3 2 1 0 Name M116CTF D6 M016CTF D4 M116CTE D2 M016CTE D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 M116CTF Touch key module 1 16 bit counter interrupt request flag 0 no request 1 interrupt request Bit 6 D6 Reserved bit must not be modified Bit 5 M016C...

Page 103: ...4 3 2 1 0 Name M316CTF D6 M216CTF D4 M316CTE D2 M216CTE D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 M316CTF Touch key module 3 16 bit counter interrupt request flag 0 no request 1 interrupt request Bit 6 D6 Reserved bit must not be modified Bit 5 M216CTF Touch key module 2 16 bit counter interrupt request flag 0 no request 1 interrupt request Bit 4 D4 Reserved bit must not be ...

Page 104: ...orresponding interrupt vector The microcontroller will then fetch its next instruction from this interrupt vector The instruction at this vector will usually be a JMP instruction which will jump to another section of program which is known as the interrupt service routine Here is located the code to control the appropriate interrupt The interrupt service routine must be terminated with a RETI inst...

Page 105: ... S R R e q u e s t F l a g a u t o r e s e t i n I S R E M I I n t e r r u p t N a m e R e q u e s t F l a g s E n a b l e B i t s M a s t e r E n a b l e P r i o r i t y H i g h I N T F T o u c h K e y M o d u l e 0 M F u n c t i o n 0 T i m e r E v e n t C o u n t e r E M I E M I 2 C H T K M 3 F T o u c h K e y M o d u l e 3 T K M 3 E E M I M 3 1 6 C T E M 3 1 6 b i t C t r o v e r f l o w M 3 1...

Page 106: ... i m e r E v e n t C o u n t e r 0 E M I E M I 2 C H T K M 3 F T o u c h K e y M o d u l e 3 T K M 3 E E M I M 3 1 6 C T E M 3 1 6 b i t C t r o v e r f l o w M 3 1 6 C T F M 2 1 6 C T E M 2 1 6 b i t C t r o v e r f l o w M 2 1 6 C T F 2 4 H 2 8 H M F 1 F T K M 2 F T o u c h K e y M o d u l e 2 M F u n c t i o n 1 M F 1 E E M I T K M 2 E E M I E M I E M I M 0 1 6 C T E M 1 1 6 C T E I n t e r r u...

Page 107: ...er is used to select the type of active edge that will trigger the external interrupt A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt Note that the INTEG register can also be used to disable the external interrupt function Multi function Interrupt Within these devices there are one or two Multi function interrupts Unlike the other independent ...

Page 108: ...ically reset and the EMI bit will be cleared to disable other interrupts The purpose of the Time Base Interrupt is to provide an interrupt signal with a fixed time period Its clock source originates from the internal clock source fSYS or fLIRC This clock passes through a divider the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interru...

Page 109: ...uest flag will be also automatically cleared As the DEF flag will not be automatically cleared it has to be cleared by the application program Touch Key Interrupts For a Touch Key interrupt to occur the global interrupt enable bit EMI and the corresponding Touch Key interrupt enable TKMnE must be first set An actual Touch Key interrupt will take place when the Touch Key request flag TKMnF is set a...

Page 110: ...MFnF will be automatically cleared the individual request flag for the function needs to be cleared by the application program It is recommended that programs do not use the CALL instruction within the interrupt service subroutine Interrupts often occur in an unpredictable manner or need to be serviced immediately If only one stack is left and the interrupt is not well controlled the original cont...

Page 111: ...st be less than 1nF BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU Rev 1 50 111 April 28 2020 K E Y 1 K E Y 2 I O R E S V D D V S S 0 1 m F V D D R e s e t C i r c u i t 0 1 1 m F 1 0 k W 1 0 0 k W 3 0 0 W 0 0 1 m F 1 N 4 1 4 8 K E Y 2 3 K E Y 2 4 S P I I C 2 C o n t r o l D e v i c e S P I I C D e v o c e 2 V D D V P P S D A T A S C L K V S S T o o t h e r C i r c u i t P A 0 P A 2 ...

Page 112: ...ds of MOV instructions data can be transferred from registers to the Accumulator and vice versa as well as being able to move specific immediate data directly into the Accumulator One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports Arithmetic Operations The ability to perform certain arithmetic operations and data manip...

Page 113: ...of all Holtek microcontrollers This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET m i or CLR m i instructions respectively The feature removes the need for programmers to first read the 8 bit output port manipulate the input data to ensure that other bits are not changed and then output the port ...

Page 114: ... m AND A x OR A x XOR A x CPL m CPLA m Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC 1 1 1 1 Not...

Page 115: ... table current page to TBLH and Data Memory Read table last page to TBLH and Data Memory 2 Note 2 Note None None Miscellaneous NOP CLR m SET m CLR WDT CLR WDT1 CLR WDT2 SWAP m SWAPA m HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre clear Watchdog Timer Pre clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down m...

Page 116: ...mulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND o...

Page 117: ...hdog Timer Description The TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in con junction with CLR WDT2 and must be executed alternately with CLR WDT2 to have ef fect Repetitively executing this instruction without alternately...

Page 118: ... then a value of 6 will be added to the high nibble Essentially the decimal conversion is performed by adding 00H 06H 60H or 66H depending on the Accumulator and flag conditions Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H ...

Page 119: ...ne MOV A m Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator Operation ACC m Affected flag s None MOV A x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator Operation ACC x Affected flag s None MOV m A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specif...

Page 120: ... address Operation Program Counter Stack ACC x Affected flag s None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re enabled by set ting the EMI bit EMI is the master interrupt global enable bit If an interrupt was pend ing when the RETI instruction is executed the pending Interrupt routine will be processed before returning to the mai...

Page 121: ...e Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i m i 1 i 0 6 ACC 7 m 0 Affected flag s None RRC m Rotate Data Memory right through Carry Description The contents of the sp...

Page 122: ...If the result is 0 the following instruction is skipped As this requires the insertion of a dummy instruc tion while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SDZA m Skip if decrement Data Memory is zero with result in ACC Description The contents of the s...

Page 123: ...is fetched it is a two cycle instruction If the result is 0 the program proceeds with the following instruc tion Operation Skip if m i 0 Affected flag s None SUB A m Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator The re sult is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be clea...

Page 124: ...nts of the specified Data Memory are copied to the Accumulator If the value is zero the following instruction is skipped As this requires the insertion of a dummy in struction while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation ACC m Skip if m 0 Affected flag s None SZ m i Skip if bit i of Data Mem...

Page 125: ...eration The result is stored in the Accumulator Operation ACC ACC XOR m Affected flag s Z XORM A m Logical XOR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation The result is stored in the Data Memory Operation m ACC XOR m Affected flag s Z XOR A x Logical XOR immediate data to ACC Description Data in the Accumulator and th...

Page 126: ...of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Further Package Information include Outline Dimensions Product Tape and Reel Specifications Packing Meterials Information Carton Information Rev 1 50 126 April 28 2020 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit To...

Page 127: ... D 0 069 E 0 050 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 a 0 8 Symbol Dimensions in mm Min Nom Max A 6 00 BSC B 3 90 BSC C 0 31 0 51 C 9 90 BSC D 1 75 E 1 27 BSC F 0 10 0 25 G 0 40 1 27 H 0 10 0 25 a 0 8 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU Rev 1 50 127 April 28 2020 1 6 1 9 8 a A B C D E F G H C ...

Page 128: ... 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 a 0 8 Symbol Dimensions in mm Min Nom Max A 6 000 BSC B 3 900 BSC C 0 20 0 30 C 4 900 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 a 0 8 Rev 1 50 128 April 28 2020 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU 1 6 1 9 8 A B C D E F C G H a ...

Page 129: ... 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 a 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 50 BSC C 0 30 0 51 C 12 80 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 41 1 27 H 0 20 0 33 a 0 8 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU Rev 1 50 129 April 28 2020 2 0 1 1 1 1 0 A B C D E F C G H a ...

Page 130: ... 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 a 0 8 Symbol Dimensions in mm Min Nom Max A 6 000 BSC B 3 900 BSC C 0 20 0 30 C 8 660 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 a 0 8 Rev 1 50 130 April 28 2020 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU 2 0 1 1 1 1 0 A B C D E F C G H a ...

Page 131: ... 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 a 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 50 BSC C 0 30 0 51 C 15 40 BSC D 2 64 E 1 27 BSC F 0 10 0 30 G 0 41 1 27 H 0 20 0 33 a 0 8 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU Rev 1 50 131 April 28 2020 2 4 1 1 3 1 2 A B C D E F C G H a ...

Page 132: ... 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 a 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 20 0 30 C 8 66 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 a 0 8 Rev 1 50 132 April 28 2020 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU 2 4 1 1 3 1 2 A B C D E F C G H a ...

Page 133: ... 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 a 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 50 BSC C 0 31 0 51 C 17 90 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 a 0 8 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU Rev 1 50 133 April 28 2020 2 8 1 1 5 1 4 A B C D F C G H a E ...

Page 134: ... 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 a 0 8 Symbol Dimensions in mm Min Nom Max A 6 000 BSC B 3 900 BSC C 0 20 0 30 C 9 900 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 a 0 8 Rev 1 50 134 April 28 2020 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU 2 8 1 1 5 1 4 A B C D F C G H a E ...

Page 135: ... H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 a 0 7 Symbol Dimensions in mm Min Nom Max A 12 00 BSC B 10 00 BSC C 12 00 BSC D 10 00 BSC E 0 80 BSC F 0 30 0 37 0 45 G 1 35 1 40 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 a 0 7 BS83B08 3 B12 3 B16 3 B16G 3 C24 3 8 Bit Touch Key Flash MCU Rev 1 50 135 April 28 2020 3 4 1 1 1 4 4 A B 2 2 1 2 E F G H I J K a 3 3 2 3 C D ...

Page 136: ...erein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without fur ther modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems H...

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