Holtek BS82B12A-3 Manual Download Page 131 | Manualshive

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Rev. 1.20

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Rev. 1.20

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BS82B12A-3/BS82C16A-3/BS82D20A-3

Touch Key 8-Bit Flash MCU with LED/LCD Driver

BS82B12A-3/BS82C16A-3/BS82D20A-3

Touch Key 8-Bit Flash MCU with LED/LCD Driver

Note that the USR register flags are read only and cannot be cleared or set by the application
program, neither will they be cleared when the program jumps to the corresponding interrupt
servicing routine, as is the case for some of the other interrupts. The flags will be cleared
automatically when certain actions are taken by the UART, the details of which are given in the
UART register section. The overall UART interrupt can be disabled or enabled by the related
interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether
the interrupt requested by the UART module is masked out or allowed.

T�ansmitte� Empt�

Flag TXIF

USR Registe�

T�ansmitte� Idle

Flag TIDLE

Receive� Ove��n

Flag OERR

Receive� Data

Available RXIF

ADDEN

RX Pin

Wake-�p

WAKE

0

1

0

1

0

1

RX7 if BNO=0

RX8 if BNO=1

UCR2 Registe�

OR

RIE

0

1

TIIE

0

1

TEIE

0

1

UART Inte��pt

Req�est Flag

UARTF

UCR2 Registe�

UARTE

INTC2

Registe�

EMI

INTC0

Registe�

UART Interrupt Scheme

Address Detect Mode

Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode.
If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver
Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is "

1

", then when

data is available, an interrupt will only be generated, if the highest received bit has a high value.
Note that the related interrupt enable control bit and the EMI bit must also be enabled for correct
interrupt generation. This highest address bit is the 9th bit if BNO bit is

"1

" or the 8th bit if BNO

bit is

"

0". If this bit is high, then the received word will be defined as an address rather than data. A

Data Available interrupt will be generated every time the last bit of the received word is set. If the
ADDEN bit is "0", then a Receiver Data Available interrupt will be generated each time the RXIF
flag is set, irrespective of the data last bit status. The address detect mode and parity enable are
mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct
operation, the parity function should be disabled by resetting the parity enable bit PREN to zero.

ADDEN

Bit 9 if BNO=1, Bit 8 if BNO=0

UART Interrupt Generated

0

0

√

1

√

1

0

×

1

√

ADDEN Bit Function

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Summary of Contents for BS82B12A-3

Page 1: ...Touch Key 8 Bit Flash MCU with LED LCD Driver BS82B12A 3 BS82C16A 3 BS82D20A 3 Revision V1 20 Date January 23 2015 ...

Page 2: ...e 25 Clocking and Pipelining 25 Program Counter 26 Stack 27 Arithmetic and Logic Unit ALU 27 Flash Program Memory 28 Structure 28 Special Vectors 29 Look up Table 29 Table Program Example 29 In Circuit Programming ICP 30 On Chip Debug Support OCDS 31 RAM Data Memory 32 Structure 32 Special Function Register Description 36 Indirect Addressing Registers IAR0 IAR1 36 Memory Pointers MP0 MP1 36 Bank P...

Page 3: ...rating Mode Switching 53 NORMAL Mode to SLOW Mode Switching 53 SLOW Mode to NORMAL Mode Switching 54 Entering the SLEEP Mode 54 Entering the IDLE0 Mode 55 Entering the IDLE1 Mode 55 Standby Current Considerations 55 Wake up 56 Programming Considerations 56 Watchdog Timer 57 Watchdog Timer Clock Source 57 Watchdog Timer Control Register 57 Watchdog Timer Operation 58 Reset and Initialisation 59 Res...

Page 4: ...e 93 PWM Output Mode 93 Single Pulse Mode 95 Capture Input Mode 97 Touch Key Function 99 Touch Key Structure 99 Touch Key Register Definition 99 Touch Key Operation 104 Touch Key Interrupt 107 Programming Considerations 107 I2 C Interface 108 I2 C Interface Operation 108 I2 C Registers 109 I2 C Bus Communication 112 I2 C Bus Start Signal 113 Slave Address 113 I2 C Bus Read Write Signal 114 I2 C Bu...

Page 5: ...ons 141 SCOM and SSEG Function for LCD 142 LCD Operation 142 LCD Bias Control 144 Low Voltage Detector LVD 146 LVD Register 146 LVD Operation 147 Configuration Options 148 Application Circuit 149 Instruction Set 150 Introduction 150 Instruction Timing 150 Moving and Transferring Data 150 Arithmetic Operations 150 Logical and Rotate Operation 151 Branches and Control Transfer 151 Bit Operations 151...

Page 6: ...les Table read instructions 63 powerful instructions Up to 8 level subroutine nesting Bit manipulation instruction Peripheral Features Flash Program Memory 2K 16 8K 16 RAM Data Memory 384 8 768 8 EEPROM Memory 64 8 Fully integrated 12 16 20 touch key functions require no external components Watchdog Timer function Up to 26 bidirectional I O lines PMOS Source Current Adjustable Software controlled ...

Page 7: ...ge of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption Easy communication with the outside world is provided using the fully integrated I2 C interface functions while the inclusion of flexible I O programming features Timer Modules and many other features further enhance device functionality and flexibility T...

Page 8: ...CK OCDSCK PA7 SCL TX VDD VSS PA1 SCOM0 PA4 INT TCK0 SCOM1 PC TP0_0 SSEG1 PC4 TP1_0 SSEG12 BS82B12A 3 BS82BV12A 3 20 SOP A 20 19 18 17 16 1 14 1 12 11 1 2 4 6 7 8 9 10 PC SSEG11 KEY12 PC2 SSEG10 KEY11 PC1 SSEG9 KEY10 PC0 SSEG8 KEY9 PB SSEG KEY6 PB4 SSEG4 KEY PB SSEG KEY4 PB2 SSEG2 KEY PB1 SSEG1 KEY2 PB0 SSEG0 KEY1 PA SDA RX PA0 TCK1 SCOM2 ICPDA OCDSDA BS82B12A 3 BS82BV12A 3 24 SOP A PA2 SCOM ICPCK ...

Page 9: ... SCOM0 PA4 INT TCK0 SCOM1 PC7 TP0_1 SSEG1 KEY16 PC6 TP1_1 SSEG14 KEY1 PC SSEG1 KEY14 PC4 SSEG12 KEY1 PD1 TP0_0 SSEG17 XT2 PD0 TP1_0 SSEG16 XT1 PC SSEG11 KEY12 PC2 SSEG10 KEY11 PC1 SSEG9 KEY10 PC0 SSEG8 KEY9 PB7 SSEG7 KEY8 PB6 SSEG6 KEY7 PB SSEG KEY6 PB4 SSEG4 KEY PB SSEG KEY4 PB2 SSEG2 KEY PB1 SSEG1 KEY2 PB0 SSEG0 KEY1 PD2 SSEG18 PD SSEG19 28 27 26 2 24 2 22 21 20 19 18 17 16 1 1 2 4 6 7 8 9 10 11...

Page 10: ...ins all pins on the device can be referenced by their Port name e g PA0 PA1 etc which refer to the digital I O function of the pins However these Port pins are also shared with other function such as the Touch Key function Timer Modules etc The function of each pin is listed in the following tables however the details behind how each pin is configured is contained in other sections of the datashee...

Page 11: ...ter enabled pull up SSEG2 SLCDC1 CMOS LCD driver output for LCD panel segment KEY3 TKM0C1 NSI Touch key input PB3 SSEG3 KEY4 PB3 PBPU ST CMOS General purpose I O Register enabled pull up SSEG3 SLCDC1 CMOS LCD driver output for LCD panel segment KEY4 TKM0C1 NSI Touch key input PB4 SSEG4 KEY5 PB4 PBPU ST CMOS General purpose I O Register enabled pull up SSEG4 SLCDC1 CMOS LCD driver output for LCD pa...

Page 12: ... up TP0_1 TMPC CMOS CTM0 output SSEG15 SLCDC2 CMOS LCD driver output for LCD panel segment VDD VDD PWR Power supply VSS VSS PWR Ground Note I T Input type O T Output type OP Optional by configuration option CO or register selection PWR Power ST Schmitt Trigger input CMOS CMOS output NMOS NMOS output SCOM SCOM output AN Analog input NSI Non standard input The PTM pin names and output pin control bi...

Page 13: ...ter enabled pull up SSEG2 SLCDC1 CMOS LCD driver output for LCD panel segment KEY3 TKM0C1 NSI Touch key input PB3 SSEG3 KEY4 PB3 PBPU ST CMOS General purpose I O Register enabled pull up SSEG3 SLCDC1 CMOS LCD driver output for LCD panel segment KEY4 TKM0C1 NSI Touch key input PB4 SSEG4 KEY5 PB4 PBPU ST CMOS General purpose I O Register enabled pull up SSEG4 SLCDC1 CMOS LCD driver output for LCD pa...

Page 14: ...16 PC7 PCPU ST CMOS General purpose I O Register enabled pull up TP0_1 TMPC CMOS CTM0 output SSEG15 SLCDC2 CMOS LCD driver output for LCD panel segment KEY16 TKM3C1 NSI Touch key input PD0 TP1_0 SSEG16 XT1 PD0 PDPU ST CMOS General purpose I O Register enabled pull up TP1_0 TMPC CMOS PTM0 output SSEG16 SLCDC3 CMOS LCD driver output for LCD panel segment XT1 CO LXT LXT pin PD1 TP0_0 SSEG17 XT2 PD1 P...

Page 15: ...data input PA4 INT TCK0 SCOM1 KEY19 PA4 PAWU PAPU ST CMOS General purpose I O Register enabled pull up and wake up INT INTC0 INTEG ST External interrupt TCK0 CTM0C0 ST CTM0 clock input SCOM1 SLCDC0 SCOM LCD driver output for LCD panel common KEY19 TKM4C1 NSI Touch key input PA7 SCL TX PA7 PAWU PAPU ST CMOS General purpose I O Register enabled pull up and wake up SCL IICC0 ST NMOS I2 C Clock TX UCR...

Page 16: ...se I O Register enabled pull up SSEG10 SLCDC2 CMOS LCD driver output for LCD panel segment KEY13 TKM2C1 NSI Touch key input PC3 SSEG11 KEY14 PC3 PCPU ST CMOS General purpose I O Register enabled pull up SSEG11 SLCDC2 CMOS LCD driver output for LCD panel segment KEY14 TKM3C1 NSI Touch key input PC4 SSEG12 KEY15 PC4 PCPU ST CMOS General purpose I O Register enabled pull up SSEG12 SLCDC2 CMOS LCD dri...

Page 17: ...ype O T Output type OP Optional by configuration option CO or register selection PWR Power ST Schmitt Trigger input CMOS CMOS output NMOS NMOS output AN Analog input NSI Non standard input SCOM SCOM output LXT Low frequency crystal oscillator The PTM pin names and output pin control bits use 1 as their serial number but other PTM related regiter names or bit names use 0 Absolute Maximum Ratings Su...

Page 18: ...e 2 0 3 0 mA 5V 4 0 6 0 mA Operating Current Normal HIRC fSYS fL fS fSUB 3V No load fH 12MHz fL fH 2 WDT enable 1 2 2 0 mA 5V 2 2 3 3 mA 3V No load fH 12MHz fL fH 4 WDT enable 1 0 1 5 mA 5V 1 8 2 7 mA 3V No load fH 12MHz fL fH 8 WDT enable 0 9 1 4 mA 5V 1 6 2 4 mA 3V No load fH 12MHz fL fH 16 WDT enable 0 8 1 2 mA 5V 1 5 2 3 mA 3V No load fH 12MHz fL fH 32 WDT enable 0 8 1 2 mA 5V 1 5 2 3 mA 5V No...

Page 19: ...ystem HALT WDT enable LXTLP 1 LXT on 2 5 5 μA 5V 6 10 μA 3V No load system HALT WDT enable LIRC on 1 3 3 0 μA 5V 2 4 5 0 μA SLEEP Mode Standby Current HIRC fSYS off fS fSUB off 3V No load system HALT WDT disable LXT and LIRC off 0 1 1 μA 5V 0 3 2 μA SLEEP Mode Standby Current LXT LIRC fSYS off fS fSUB off 3V No load system HALT WDT disable LXT and LIRC off 0 1 1 μA 5V 0 3 2 μA VIL Input Low Voltag...

Page 20: ...mer Input Pulse Width 0 3 μs fLIRC System Clock 32kHz 5V Ta 25 C 10 32 10 kHz fLXT System Clock LXT 32768 Hz tINT Interrupt Pulse Width 1 5 10 μs tLVR Low Voltage Width to Reset 120 240 480 μs tLVD Low Voltage Width to Interrupt 60 120 240 μs tLVDS LVDO stable time 15 μs tEERD EEPROM Read Time 1 2 4 tSYS tEEWR EEPROM Write Time 1 2 4 ms tRSTD System Reset Delay Time Power on reset LVR reset WDT S ...

Page 21: ...1 30 60 μA 5V 60 120 3V fREFOSC 500kHz MnTSS 1 MnFILEN 0 30 60 μA 5V 60 120 3V fREFOSC 500kHz MnTSS 1 MnFILEN 1 40 80 μA 5V 80 160 CKEYOSC Sensor KEY Oscillator External Capacitance 5V fSENOSC 500kHz 5 10 20 pF CREFOSC Reference Oscillator Internal Capacitance 5V fSENOSC 500kHz 5 10 20 pF fKEYOSC Sensor KEY Oscillator Operating Frequency 5V External Capacitance 7 8 9 10 11 12 13 14 15 50pF 100 500...

Page 22: ...nTSS 1 MnFILEN 0 40 80 μA 5V 80 160 3V fREFOSC 1000kHz MnTSS 1 MnFILEN 1 60 120 μA 5V 150 300 CKEYOSC Sensor KEY Oscillator External Capacitance 5V fSENOSC 1000kHz 5 10 20 pF CREFOSC Reference Oscillator Internal Capacitance 5V fSENOSC 1000kHz 5 10 20 pF fKEYOSC Sensor KEY Oscillator Operating Frequency 5V External Capacitance 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 50pF 150 1000 2500 kHz fREFYOSC Ref...

Page 23: ...A 5V 120 240 3V fREFOSC 1500kHz MnTSS 1 MnFILEN 1 90 180 μA 5V 225 450 CKEYOSC Sensor KEY Oscillator External Capacitance 3V fSENOSC 1500kHz 4 8 16 pF 5V 5 10 20 CREFOSC Reference Oscillator Internal Capacitance 3V fSENOSC 1500kHz 4 8 16 pF 5V 5 10 20 fKEYOSC Sensor KEY Oscillator Operating Frequency 3V External Capacitance 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 50pF 150 1500 3000 kHz 5V 150 1500 300...

Page 24: ... 4 8 16 pF 5V 5 10 20 CREFOSC Reference Oscillator Internal Capacitance 3V fSENOSC 2000kHz 4 8 16 pF 5V 5 10 20 fKEYOSC Sensor KEY Oscillator Operating Frequency 3V External Capacitance 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 50pF 150 2000 4000 kHz 5V 150 2000 4000 fREFYOSC Reference Oscillator Operating Frequency 3V Internal Capacitance 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 50pF 150 2000 4000 kHz 5V 15...

Page 25: ... maximum reliability and flexibility This makes these devices suitable for low cost high volume production for controller applications Clocking and Pipelining The main system clock derived from either a LXT HIRC or LIRC oscillator is subdivided into four internally generated non overlapping clocks T1 T4 The Program Counter is incremented at the beginning of the T1 clock during which time a new ins...

Page 26: ... the Program Counter For conditional skip instructions once the condition has been met the next instruction which has already been fetched during the present instruction execution is discarded and a dummy cycle takes its place while the correct instruction is obtained Device Program Counter Program Counter High Byte PCL Register BS82B12A 3 PC10 PC8 PCL7 PCL0 BS82C16A 3 PC11 PC8 BS82D20A 3 PC12 PC8...

Page 27: ...on can still be executed which will result in a stack overflow Precautions should be taken to avoid such cases which might cause unpredictable program branching If the stack is overflow the first Program Counter save in the stack will be lost P r o g r a m C o u n t e r S t a c k L e v e l 1 S t a c k L e v e l 2 P r o g r a m M e m o r y T o p o f S t a c k S t a c k P o i n t e r B o t t o m o f...

Page 28: ...s the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating Structure The Program Memory has a capacity of 2K 16 bits to 8K 16 bits The Program Memory is addressed by the Program Counter and also contains data table information and interrupt entries Table data which can be setup in any location within the Program Memory is ad...

Page 29: ... L a s t p a g e o r T B H P R e g i s t e r Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller This example uses raw table data located in the Program Memory which is stored there using the ORG statement The value at this ORG statement is 0700H which refers to the start address of the last page within the 2K wor...

Page 30: ...ogramming the microcontroller in circuit using a 4 pin interface This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un programmed microcontroller and then programming or upgrading the program at a later stage This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases witho...

Page 31: ...CU device are almost functionally compatible except for the On Chip Debug function Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT IDE development tools The OCDSDA pin is the OCDS Data Address input output pin while the OCDSCK pin is the OCDS clock input pin When users use the EV chip for debugging other functions ...

Page 32: ...s addressed from 00H 7FH in Data Memory are common and accessible in all banks with the exception of the EEC register at address 40H which is only accessible in Bank 1 Switching between the different Data Memory sectors is achieved by setting the Bank Pointer to the correct value The start address of the Data Memory for all devices is the address 00H Memory Type Device Capacity Special Function Da...

Page 33: ...Rev 1 20 33 January 23 2015 BS82B12A 3 BS82C16A 3 BS82D20A 3 Touch Key 8 Bit Flash MCU with LED LCD Driver ...

Page 34: ...Rev 1 20 34 January 23 2015 BS82B12A 3 BS82C16A 3 BS82D20A 3 Touch Key 8 Bit Flash MCU with LED LCD Driver ...

Page 35: ...Rev 1 20 35 January 23 2015 BS82B12A 3 BS82C16A 3 BS82D20A 3 Touch Key 8 Bit Flash MCU with LED LCD Driver ...

Page 36: ...eration Memory Pointers MP0 MP1 Two Memory Pointers known as MP0 and MP1 are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing Registers is carried out the actual address that the microcontroller...

Page 37: ...ccessed from within any bank The EEC register in bank 1 can only be accessed by indirectly addressing the Data Memory Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer Accessing data from banks other than Bank 0 must be implemented using Indirect Addressing Device 7 6 5 4 3 2 1 0 BS82B12A 3 DMBP1 DMBP0 BS82C16A 3 DMBP1 DMB...

Page 38: ...gisters is permitted Program Counter Low Register PCL To provide additional program control functions the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory By manipulating this register direct jumps to other program locations are easily implemented Loading a value directly into this PCL register will cause a jump to ...

Page 39: ... the status of the latest operations C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation otherwise C is cleared C is also affected by a rotate through carry instruction AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtrac...

Page 40: ...OV Overflow flag 0 no overflow 1 an operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa Bit 2 Z Zero flag 0 The result of an arithmetic or logical operation is not zero 1 The result of an arithmetic or logical operation is zero Bit 1 AC Auxiliary flag 0 no auxiliary carry 1 an operation results in a carry out of the low nibbles in addi...

Page 41: ...ations to the EEPROM are carried out in single byte operations using an address and data register in Sector 0 and a single control register in Sector 1 Device Capacity Address BS82B12A 3 64 8 00H 3FH BS82C16A 3 BS82D20A 3 EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory These are the address register EEA the data register EED and a single control re...

Page 42: ...igh by the application program will activate a write cycle This bit will be automatically reset to zero by the hardware after the write cycle has finished Setting this bit high will have no effect if the WREN has not first been set high Bit 1 RDEN Data EEPROM Read Enable 0 Disable 1 Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried...

Page 43: ... set As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock a certain time will elapse before the data will have been written into the EEPROM Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt When the write cycle terminates the WR b...

Page 44: ...e that the devices should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally completed Otherwise the EEPROM read or write operation will fail Programming Examples Reading data from the EEPROM polling method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A 040H setup memory pointer MP1 MOV MP1 A MP1 points to EEC register MOV A 01H setup Bank Pointer BP MOV ...

Page 45: ... oscillators With the capability of dynamically switching between fast and slow system clock the devices have the flexibility to optimize the performance power ratio a feature especially important in power sensitive portable applications Device Type Name Freq Pins BS82B12A 3 BS82C16A 3 BS82D20A 3 Internal High Speed RC HIRC 8 12 16MHz Internal Low Speed RC LIRC 32kHz BS82C16A 3 BS82D20A 3 External...

Page 46: ...e trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage temperature and process variations on the oscillation frequency are minimised Internal 32kHz Oscillator LIRC The Internal 32kHz System Oscillator is a low frequency oscillator It is a fully integrated RC oscillator with a typica...

Page 47: ...ock independent of the system clock must be provided However for some crystals to ensure oscillation and accurate frequency generation it is necessary to add two small value external capacitors C1 and C2 The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer specification The external parallel feedback resistor Rp is required Note that the wire ...

Page 48: ...ction normally the only difference is that it will take more time to start up if in the Low power mode Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible conflicting requirements that are especially true in battery powered portable applications The fast clocks requ...

Page 49: ...ith LED LCD Driver System Clock Configurations Note The LXT oscillator is only for the BS82C16A 3 and BS82D20A 3 When the system clock source fSYS is switched to fSUB from fH the high speed oscillation will stop to conserve the power Thus there is no fH fH 64 for peripheral circuit to use ...

Page 50: ...gh a high speed oscillator is used running the microcontroller at a divided clock ratio reduces the operating current SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source The clock source used will be from fSUB Running the microcontroller in this mode allows it to run with much lower operating currents In the SLOW Mode the fH is of...

Page 51: ...cillator ready flag which indicates when the high speed system oscillator is stable after a wake up has occurred This flag is cleared to zero by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable Therefore this flag will always be read as 1 by the application program after device power on The flag will be low when in the SLEEP o...

Page 52: ...RCS0 HIRC frequency clock select 00 8MHz 01 12 MHz 10 16 MHz 11 8 MHz It is recommended that the HIRC frequency selected by these two bits is the same with the frequency determined by the configuration option to keep the HIRC frequency accuracy specified in the A C characteristics Bit 3 LXTLP LXT low power control 0 Quick Start mode 1 Low Power mode Bit 2 LVRF LVR function reset flag Describe else...

Page 53: ...es to a low level which implies that clock source is switched from the high speed clock source fH to the clock source fH 2 fH 64 or fSUB If the clock is from the fSUB the high speed clock source will stop running to conserve power When this happens it must be noted that the fH 16 and fH 64 internal clock sources will also stop running The accompanying flowchart shows what happens when the devices ...

Page 54: ...or high speed system oscillator stabilization is 15 16 clock cycles Entering the SLEEP Mode There is only one way for the devices to enter the SLEEP Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 0 When this instruction is executed under the conditions described above the following will occur The system clock and the fSUB cl...

Page 55: ...y contents and registers will maintain their present condition The WDT will be cleared and resume counting The I O ports will maintain their present conditions In the status register the Power Down flag PDF will be set and the Watchdog time out flag TO will be cleared Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the dev...

Page 56: ...on at the instruction following the HALT instruction In this situation the interrupt which woke up the device will not be immediately serviced but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free The other situation is where the related interrupt is enabled and the stack is not full in which case the regular interrupt response takes pla...

Page 57: ...then subdivided by a ratio of 28 to 218 to give longer timeouts the actual value being chosen using the WS2 WS0 bits in the WDTC register Watchdog Timer Control Register A single register WDTC controls the required timeout period as well as the enable operation The WDTC register is initiated to 01010011B at any reset except WDT time out hardware warm reset WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE...

Page 58: ...uted in the correct manner in which case the Watchdog Timer will overflow and reset the device There are five bits WE4 WE0 in the WDTC register to enable the WDT function When the WE4 WE0 bits value is equal to 01010B or 10101B the WDT function is enabled However if the WE4 WE0 bits are changed to any other values except 01010B and 10101B which is caused by the environmental noise it will reset th...

Page 59: ...t to defined states before the program commences One of these registers is the Program Counter which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address Another type of reset is when the Watchdog Timer overflows and resets the microcontroller All types of reset operations result in different register conditions being setup Another res...

Page 60: ...atically disabled when the device enters the SLEEP or IDLE mode Note tRSTD is power on delay typical time 50ms Low Voltage Reset Timing Chart CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON HIRCS1 HIRCS0 LXTLP LVRF D1 WRF R W R W R W R W R W R W R W R W POR 0 0 0 0 x 0 0 x unknown Bit 7 FSYSON fSYS Control in IDLE Mode Describe elsewhere Bit 6 Unimplemented read as 0 Bit 5 4 HIRCS1 HIRCS0 HIRC frequ...

Page 61: ...ction or Watchdog Timer The reset flags are shown in the table TO PDF RESET Conditions 0 0 Power on reset u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time out reset during NORMAL or SLOW Mode operation 1 1 WDT time out reset during IDLE or SLEEP Mode operation Note u stands for unchanged The following table indicates the way in which the various components of the microcontroller are...

Page 62: ...PA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u uuuu PAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u uuuu PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u uuuu PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u uuuu SLEDC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 uuuu uuuu SLEDC1 0 1 0 1 0 1 0 1 0 1 0 1 uuuu 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 uu uuuu WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuu...

Page 63: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TKM0ROL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TKM0ROH 0 0 0 0 0 0 uu TKM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TKM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u uu uuuu TKM116DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TKM116DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TKM1...

Page 64: ...M0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM0DH 0 0 0 0 0 0 uu PTM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM0AH 0 0 0 0 0 0 uu PTM0RPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PTM0RPH 0 0 0 0 0 0 uu TKM416DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TKM416DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TKM4R...

Page 65: ...t be ready at the T2 rising edge of instruction MOV A m where m denotes the port address For output operation all the data is latched and remains unchanged until the output latch is rewritten I O Register List Device Register Name Bit 7 6 5 4 3 2 1 0 BS82B12A 3 BS82C16A 3 BS82D20A 3 PAWU PAWU7 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA PA7 PA4 PA3 PA2 PA1 PA0 PAC PAC...

Page 66: ...l Registers Each I O port has its own control register known as PAC PDC to control the input output configuration With this control register each CMOS output or input can be reconfigured dynamically under software control Each pin of the I O ports is directly mapped to a bit in its associated port control register For the I O pin to function as an input the corresponding bit of the control registe...

Page 67: ...n the corresponding pin is configured as a CMOS output Bit 5 4 PBPS1 PBPS0 PB3 PB0 source current select 00 source Level 0 min 01 source Level 1 10 source Level 2 11 source Level 3 max These bits are available when the corresponding pin is configured as a CMOS output Bit 3 2 PAPS3 PAPS2 PA7 and PA4 source current select 00 source Level 0 min 01 source Level 1 10 source Level 2 11 source Level 3 ma...

Page 68: ...s Within the user program one of the first things to consider is port initialisation After a reset all of the I O data and port control registers will be set high This means that all I O pins will default to an input state the level of which depends on the other connected circuitry and whether pull high selections have been chosen If the port control registers PAC PDC are then programmed to setup ...

Page 69: ...sed in the accompanying table Function CTM PTM Timer Counter I P Capture Compare Match Output PWM Channels 1 1 Single Pulse Output 1 PWM Alignment Edge Edge PWM Adjustment Period Duty Duty or Period Duty or Period TM Function Summary CTM0 PTM0 10 bit CTM 10 bit PTM TM Name Type Reference TM Operation The two different types of TMs offer a diverse range of functions from simple timing operations to...

Page 70: ...rigger input pin in single pulse output mode for the PTM0 The TMs each has two output pins When the TM is in the Compare Match Output Mode these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs As the TM output pins are pin shared with other function the TM output function must first be setup using the associated register A single...

Page 71: ... Pin Control Block Diagram P C 6 O u t p u t F u n c t i o n 0 1 P C 6 1 0 O u t p u t C a p t u r e I n p u t P A 0 T C K 1 T C K I n p u t P C 6 T P 1 _ 1 T M 1 P C 1 P C 4 O u t p u t F u n c t i o n 0 1 P C 4 1 0 P C 4 T P 1 _ 0 T M 1 P C 0 1 0 T M 1 P C 1 1 0 T M 1 P C 0 0 1 P T 0 C K S BS82B12A 3 PTM Function Pin Control Block Diagram ...

Page 72: ...1 P D 0 1 0 P D 0 T P 1 _ 0 T M 1 P C 0 1 0 T M 1 P C 1 1 0 T M 1 P C 0 0 1 P 0 T C K S BS82C16A 3 BS82D20A 3 PTM Function Pin Control Block Diagram TMPC Register Bit 7 6 5 4 3 2 1 0 Name TM1PC1 TM1PC0 TM0PC1 TM0PC0 R W R W R W R W R W POR 0 0 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 TM1PC1 TP1_1 pin Control 0 Disabled 1 Enabled Bit 2 TM1PC0 TP1_0 pin control 0 Disabled 1 Enabled Bit 1 TM0PC1 TP0...

Page 73: ...ow byte registers named xTMnAL and PTMnRPL in the following access procedures Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values Data B s 8 bit B ffe xTMnDH xTMnDL xTMnAH xTMnAL xTMn Co nte Registe Read onl xTMn CCRA Registe Read W ite PTMn CCRP Registe Read W ite PTMnRPH PTMnRPL The following steps show the read and write pro...

Page 74: ...omparators will compare the value in the counter with CCRP and CCRA registers The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits The only way of changing the value of the 10 bit counter using the application program is to clear the counter by changing the CT0ON bit from low to hi...

Page 75: ... 6 5 4 3 2 1 0 Name CT0PAU CT0CK2 CT0CK1 CT0CK0 CT0ON CT0RP2 CT0RP1 CT0RP0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 CT0PAU CTM0 Counter Pause Control 0 Run 1 Pause The counter can be paused by setting this bit high Clearing the bit to zero restores normal counter operation When in a Pause condition the CTM0 will remain powered up and continue to consume power The counter will ...

Page 76: ...p the value on the internal CCRP 3 bit register which are then compared with the internal counter s highest three bits The result of this comparison can be selected to clear the internal counter if the CT0CCLR bit is set to zero Setting the CT0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter As the CCRP bits are only compared with the highest three...

Page 77: ...nged when The CTM0 is running Bit 3 CT0OC TP0 Output control bit Compare Match Output Mode 0 Initial low 1 Initial high PWM Mode 0 Active low 1 Active high This is the output control bit for the CTM0 output pin Its operation depends upon whether CTM0 is being used in the Compare Match Output Mode or in the PWM Mode It has no effect if the CTM0 is in the Timer Counter Mode In the Compare Match Outp...

Page 78: ...3 2 1 0 Name D9 D8 R W R R POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 CTM0 Counter High Byte Register bit 1 bit 0 CTM0 10 bit Counter bit 9 bit 8 CTM0AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 CTM0 CCRA Low Byte Register bit 7 bit 0 CTM0 10 bit CCRA bit 7 bit 0 CTM0AH Register Bit 7 6 5 4 3 2 1 0 Name D9 D8 R W ...

Page 79: ...tor A However here only the CTMA0F interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when CT0CCLR is high no CTMP0F interrupt request flag will be generated If the CCRA bits are all zero the counter will overflow when its reaches its maximum 10 bit 3FF Hex value however here the CTMA0F interrupt request flag will not be ge...

Page 80: ...t Now CT0IO 1 0 10 Active High O tp t Select O tp t not affected b CTMA0F flag Remains High ntil eset b CT0ON bit Compare Match Output Mode CT0CCLR 0 CT0CCLR 0 CT0M 1 0 00 CT0PAU Res me Stop Time CCRP 0 CCRP 0 CT0POL O tp t Pin Reset to initial val e O tp t inve ts when CT0POL is high O tp t cont olled b othe pin sha ed f nction Co nte Val e Compare Match Output Mode CT0CCLR 0 Note 1 With CT0CCLR ...

Page 81: ...ins High ntil eset b CT0ON bit Compare Match Output Mode C0TCCLR 1 CT0CCLR 1 CT0M 1 0 00 CT0PAU Res me Stop Time CCRA 0 CT0POL O tp t Pin Reset to initial val e O tp t inve ts when CT0POL is high O tp t cont olled b othe pin sha ed f nction Co nte Val e O tp t does not change No CTMA0F flag gene ated on CCRA ove flow CCRA 0 Co nte ove flow CTMP0F not gene ated Compare Match Output Mode CT0CCLR 1 N...

Page 82: ...enerate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the CT0DPX bit in the CTM0C1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCR...

Page 83: ... Mode CT0DPX 0 Counter Stop If CT0ON bit low Counter reset when CT0ON returns high PWM resumes operation Output controlled by Other pin shared function Time CT0DPX 0 CT0M 1 0 10 CT0POL Output Inverts When CT0POL 1 CT0PAU Resume Pause CTM0 O P Pin CT0OC 0 PWM Mode CT0DPX 0 Note 1 Here CT0DPX 0 Counter cleared by CCRP 2 A counter clear sets PWM Period 3 The internal PWM function continues running ev...

Page 84: ... PWM Mode CT0DPX 1 Counter Stop If CT0ON bit low Counter reset when CT0ON returns high PWM resumes operation Output controlled by Other pin shared function Time CT0DPX 1 CT0M 1 0 10 CT0POL Output Inverts When CT0POL 1 CT0PAU Resume Pause CTM0 O P Pin CT0OC 0 PWM Mode CT0DPX 1 Note 1 Here CT0DPX 1 Counter cleared by CCRA 2 A counter clear sets PWM Period 3 The internal PWM function continues even w...

Page 85: ...ith the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP comparator is 10 bit wide The only way of changing the value of the 10 bit counter using the application program is to clear the counter by changing the PT0ON bit from low to high The counter will also be cleared automatically by a counter overflow or a compare ...

Page 86: ...egister List PTM0C0 Register Bit 7 6 5 4 3 2 1 0 Name PT0PAU PT0CK2 PT0CK1 PT0CK0 PT0ON R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 PT0PAU PTM0 Counter Pause Control 0 Run 1 Pause The counter can be paused by setting this bit high Clearing the bit to zero restores normal counter operation When in a Pause condition the PTM1 will remain powered up and continue to consume power The counter will retai...

Page 87: ...0IO0 PT0OC PT0POL PT0CKS PT0CCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PT0M1 PT0M0 Select PTM0 Operating Mode 00 Compare Match Output Mode 01 Capture Input Mode 10 PWM Mode or Single Pulse Output Mode 11 Timer Counter Mode These bits setup the required operating mode for the PTM0 To ensure reliable operation the PTM0 should be switched off before any changes are made to t...

Page 88: ...ode 0 Initial low 1 Initial high PWM Mode Single Pulse Output Mode 0 Active low 1 Active high This is the output control bit for the PTM0 output pin Its operation depends upon whether PTM0 is being used in the Compare Match Output Mode or in the PWM Mode Single Pulse Output Mode It has no effect if the PTM0 is in the Timer Counter Mode In the Compare Match Output Mode it determines the logic level...

Page 89: ...gister bit 1 bit 0 PTM0 10 bit Counter bit 9 bit 8 PTM0AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 PTM0 CCRA Low Byte Register bit 7 bit 0 PTM0 10 bit CCRA bit 7 bit 0 PTM0AH Register Bit 7 6 5 4 3 2 1 0 Name D9 D8 R W R W R W POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 PTM0 CCRA High Byte Register bit 1 bit 0 PTM...

Page 90: ...igh then the counter will be cleared when a compare match occurs from Comparator A However here only the PTMA0F interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when PT0CCLR is high no PTMP0F interrupt request flag will be generated In the Compare Match Output Mode the CCRA can not be cleared to zero If the CCRA bits are ...

Page 91: ...p t pin set to initial Level Low if PT0OC 0 O tp t Toggle with PTMA0F flag Note PT0IO 1 0 10 Active High O tp t select He e PT0IO 1 0 11 Toggle O tp t select O tp t not affected b PTMA0F flag Remains High ntil eset b PT0ON bit O tp t Pin Reset to Initial val e O tp t Inve ts when PT0POL is high n defined Compare Match Output Mode PT0CCLR 0 Note 1 With PT0CCLR 0 a Comparator P match will clear the ...

Page 92: ...O 1 0 10 Active High O tp t select He e PT0IO 1 0 11 Toggle O tp t select O tp t not affected b PTMA0F flag Remains High ntil eset b PT0ON bit O tp t Pin Reset to Initial val e O tp t cont olled b othe pin sha ed f nction O tp t Inve ts when PT0POL is high PTMP0F not gene ated No PTMA0F flag gene ated on CCRA ove flow O tp t does not change Compare Match Output Mode PT0CCLR 1 Note 1 With PT0CCLR 1...

Page 93: ...e choice of generated waveform is extremely flexible In the PWM Output Mode the PT0CCLR bit has no effect on the PWM operation Both of the CCRA and CCRP registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle The PWM waveform frequency and duty cycle can ther...

Page 94: ...P Pa se Res me Co nte Stop if PT0ON bit low Co nte Reset when PT0ON et ns high PT0M 1 0 10 PWM D t C cle set b CCRA PWM es mes ope ation O tp t cont olled b othe pin sha ed f nction O tp t Inve ts When PT0POL 1 PWM Pe iod set b CCRP PTM0 O P Pin PT0OC 0 PWM Output Mode Note 1 A counter clear sets the PWM Period 2 The internal PWM function continues running even when PT0IO 1 0 00 or 01 3 The PT0CCL...

Page 95: ...he Single Pulse output When the PT0ON bit transitions to a high level the counter will start running and the pulse leading edge will be generated The PT0ON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the PT0ON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Co...

Page 96: ... 11 P lse Width set b CCRA O tp t Inve ts when PT0POL 1 No CCRP Inte pts gene ated PTM0 O P Pin PT0OC 0 TCK1 pin Softwa e T igge Clea ed b CCRA match TCK1 pin T igge A to set b TCK1 pin Softwa e T igge Softwa e Clea Softwa e T igge Softwa e T igge Single Pulse Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse is triggered by the TCK1 pin or by setting the PT0ON bit high 4 A TCK1 p...

Page 97: ...interrupt generated Irrespective of what events occur on the TP1_0 TP1_1 or TCK1 pin the counter will continue to free run until the PT0ON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a PTM0 interrupt will also be genera...

Page 98: ... o TCK1 XX Co nte Stop PT0IO 1 0 Val e XX YY XX YY Active edge Active edge Active edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capt e Capture Input Mode Note 1 PT0M 1 0 01 and active edge set by the PT0IO 1 0 bits 2 A PTM0 Capture input pin active edge transfers the counter value to CCRA 3 PT0CCLR bit not used 4 No output function PT0OC and PT0POL bits are not used 5 CCRP determine...

Page 99: ...y8 PB4 PB7 M2 Key9 Key12 PC0 PC3 M3 Key13 Key16 PC4 PC7 BS82D20A 3 20 M0 Key1 Key4 PB0 PB3 M1 Key5 Key8 PB4 PB7 M2 Key9 Key12 PD3 PD2 PC0 PC1 M3 Key13 Key16 PC2 PC5 M4 Key17 Key20 PC6 PC7 PA4 PA1 Touch Key Register Definition Each touch key module which contains four touch key functions has its own suite registers The following table shows the register set for each touch key module The Mn within t...

Page 100: ...W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 TKRCOV Time slot counter overflow flag 0 No overflow 1 Overflow If module 0 or all module time slot counter selected by the TSCS bit is overflow the Touch Key Interrupt request flag TKMF will be set and all module key OSCs and ref OSCs auto stop All module 16 bit C F counter 16 bit counter 5 bit time slot counter and 8 bit time slot timer cou...

Page 101: ...fSYS 8 TKC1 Register Bit 7 6 5 4 3 2 1 0 Name TKFS1 TKFS0 R W R W R W POR 1 1 Bit 7 2 Unimplemented read as 0 Bit 1 0 TKFS1 TKFS0 Touch key OSC frequency select 00 500kHz 01 1000 kHz 10 1500 kHz 11 2000 kHz TK16DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 Touch key module 16 bit counter low byte contents TK16DH Register Bit 7 6 5 4 3 ...

Page 102: ...rnal capacitor select OSC inernal capacitor select TKMnRO 9 0 50pF 1024 TKMnC0 Register Bit 7 6 5 4 3 2 1 0 Name MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF2 MnSOF1 MnSOF0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 MnMXS1 MnMXS0 Multiplexer Key Select Bit Module Number MnMXS1 MnMXS0 M0 M1 M2 M3 M4 0 0 Key 1 Key 5 Key 9 Key 13 Key 17 0 1 Key 2 Key 6 Key 10 Key 14 Key 18 1 0 Key 3...

Page 103: ...O MnK2IO MnK1IO R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 MnTSS Time slot counter clock select 0 Reference oscillator 1 fSYS 4 Bit 6 Unimplemented read as 0 Bit 5 MnROEN Reference OSC control 0 Disable 1 Enable Bit 4 MnKOEN Key OSC control 0 Disable 1 Enable Bit 3 0 MnK4IO MnK1IO I O pin or touch key function select MnK4IO M0 M1 M2 M3 M4 PB3 Key 4 PB7 Key 8 PC3 Key 12 or PC1 Key 12 P...

Page 104: ... the time slot counter for all modules All modules use the same started signal The16 bit C F counter 16 bit counter 5 bit time slot counter in all modules will be automatically cleared when this bit is cleared to zero but the 8 bit programmable time slot counter will not be cleared The overflow time is setup by user When this bit changes from low to high the 16 bit C F counter 16 bit counter 5 bit...

Page 105: ...w fSYS fSYS 2 fSYS 4 fSYS 8 TK16S1 TK16S0 bit time slot co nte Ove flow 8 bit time slot time co nte üüü MUX fSYS 4 MnTSS 8 bit time slot time co nte p eload egiste Ove flow M lti f eq enc 16 bit C F co nte Note 1 Each touch key module contains the content in the red dash line 2 The content in the black dash line is the module number 0 n Each module contains 4 touch keys Touch Key Module Block Diag...

Page 106: ...e touch key sense oscilltor and reference oscillator timing diagram is shown in the following figure TKST MnKOEN MnROEN KEY OSC CLK Refe ence OSC CLK fCFTMCK enable fCFTMCK MnDFEN 0 fCFTMCK MnDFEN 1 TKRCOV Set To ch Ke inte pt eq est flag Ha dwa e clea to 0 2 6 TKTMR ove flow 2 Touch Key or I O Function Select ...

Page 107: ...s to be cleared by the application program Module 0 only contains one 16 bit counter The TK16OV flag which is the 16 bit counter overflow flag will go high when the 16 bit counter overflows As this flag will not be automatically cleared it has to be cleared by the application program More details regarding the touch key interrupt is located in the interrupt section of the datasheet Programming Con...

Page 108: ...pes For this reason it is necessary that external pull high resistors are connected to these outputs Note that no chip select line exists as each device on the I2 C bus is identified by a unique address which will be transmitted and received on the I2 C bus When two devices communicate with each other on the bidirectional I2 C bus one is known as the master device and one as the slave device Both ...

Page 109: ...m the I2 C bus the microcontroller can read it from the IICD register Any transmission or reception of data from the I2 C bus must be made via the IICD register Register Name Bit 7 6 5 4 3 2 1 0 IICC0 I2CDBNC1 I2CDBNC0 IICEN IICC1 IICHCF IICHAAS IICHBB IICHTX IICTXAK IICSRW IICAMWU IICRXAK IICD IICD7 IICD6 IICD5 IICD4 IICD3 IICD2 IICD1 IICD0 IICA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 I2CTOC I2...

Page 110: ...d users read the 1st data byte from the IICD register by the application program and then the IICHCF bit is automatically cleared to zero Fourth the I2 C slave device finishes receiving the 2nd data byte and then the IICHCF bit is automatically set high and so on Finally the I2 C slave device receives a stop signal from the I2 C master and then the IICHCF bit is automatically set high Bit 6 IICHAA...

Page 111: ...s interrupt enable bit is set but setting IICAMWU 0 maybe can t generate an interrupt when I2 C address match even if this interrupt enable bit is set Bit 0 IICRXAK I2 C Bus Receive acknowledge flag 0 Slave receive acknowledge flag 1 Slave do not receive acknowledge flag The IICRXAK flag is the receiver acknowledge flag When the IICRXAK flag is 0 it means that a acknowledge signal has been receive...

Page 112: ...parate steps a START signal a slave device address transmission a data transmission and finally a STOP signal When a START signal is placed on the I2 C bus all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus The first seven bits of the data will be the slave address with the first bit being the MSB If the address of the slave device matches th...

Page 113: ...ress data will compare it with their own 7 bit slave address If the address sent out by the master matches the internal address of the microcontroller slave device then an internal I2 C bus interrupt signal will be generated The next bit following the address which is the 8th bit defines the read write status and will be saved to the IICSRW bit of the IICC1 register The slave device will then tran...

Page 114: ...a transmitter or a receiver If the IICSRW flag is high the slave device should be setup to be a transmitter so the IICHTX bit in the IICC1 register should be set high If the IICSRW flag is low then the microcontroller slave device should be setup as a receiver and the IICHTX bit in the IICC1 register should be cleared to zero I2 C Bus Data and Acknowledge Signal The transmitted data is 8 bits wide...

Page 115: ...Driver Note When a slave address is matched the device must be placed in either the transmit mode and then write data to the IICD register or in the receive mode where it must implement a dummy read from the IICD register to release the SCL line I2 C Communication Timing Diagram I2 C Bus ISR Flow Chart ...

Page 116: ...m e o u t c o u n t e r r e s e t o n S C L n e g a t i v e t r a n s i t i o n 1 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 1 S C L S t a r t S D A I I C S R W A C K S t o p S C L S D A S l a v e A d d r e s s 2 2 I2 C Time out When an I2 C time out counter overflow occurs the counter will stop and the I2CTOEN bit will be cleared to zero and the I2CTOF bit will be set high to indicate that a time out conditio...

Page 117: ...r two stop bits Baud rate generator with 8 bit prescaler Parity framing noise and overrun error detection Support for interrupt on address detect last character bit 1 Transmitter and receiver enabled independently 2 byte Deep FIFO Receive Data Buffer Transmit and Receive Multiple Interrupt Generation Sources Transmitter Empty Transmitter Idle Receiver Full Receiver Overrun Address Mode Detect RX p...

Page 118: ... onto the MCU Data Memory the Receiver Shift Register is not mapped and is therefore inaccessible to the application program It should be noted that the actual register for data transmission and reception although referred to in the text and in application programs as separate TXR and RXR registers only exists as a single shared register in the Data Memory This shared register known as the TXR_RXR...

Page 119: ...tus register USR followed by an access to the RXR data register Bit 5 FERR Framing error flag 0 No framing error is detected 1 Framing error is detected The FERR flag is the framing error flag When this read only flag is 0 it indicates that there is no framing error When the flag is 1 it indicates that a framing error has been detected for the current character The flag can also be cleared by a so...

Page 120: ...wn as the transmission complete flag When this read only flag is 0 it indicates that a transmission is in progress This flag will be set to 1 when the TXIF flag is 1 and when there is no transmit data or break character being transmitted When TIDLE is equal to 1 the TX pin becomes idle with the pin state in logic high condition The TIDLE flag is cleared by reading the USR register with TIDLE set a...

Page 121: ...sions and receptions will be terminated and the module will be reset as defined above When the UART is re enabled it will restart in the same configuration Bit 6 BNO Number of data transfer bits selection 0 8 bit data transfer 1 9 bit data transfer This bit is used to select the data length format which can have a choice of either 8 bit or 9 bit format When this bit is equal to 1 a 9 bit data leng...

Page 122: ...e baud rate speed receiver wake up enable and the address detect enable Further explanation on each of the bits is given below Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 TXEN UART Transmitter enabled control 0 UART transmitter is disabled 1 UART transmitter is enabled The bit named TXEN is the Transmitter Enable Bi...

Page 123: ...nables or disables the receiver wake up function If this bit is equal to 1 and the device is in the IDLE0 or SLEEP mode a falling edge on the RX input pin will wake up the device If this bit is equal to 0 and the device is in the IDLE or SLEEP mode any edge transitions on the RX pin will not wake up the device Bit 2 RIE Receiver interrupt enable control 0 Receiver related interrupt is disabled 1 R...

Page 124: ...e which in turn determines the formula that is used to calculate the baud rate The value in the BRG register N which is used in the following baud rate calculation formula determines the division factor Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255 UCR2 BRGH Bit 0 1 Baud Rate BR fSYS 64 N 1 fSYS 16 N 1 By programming the BRGH bit which allows sele...

Page 125: ... 103 4 808 0 16 9 6 12 9 615 0 16 51 9 615 0 16 19 2 6 17 8857 6 99 25 19 231 0 16 38 4 2 41 667 8 51 12 38 462 0 16 57 6 1 62 500 8 51 8 55 556 3 55 115 2 0 125 8 51 3 125 8 51 250 1 250 0 Baud Rates and Error Values UART Setup and Control For data transfer the UART function utilizes a non return to zero more commonly known as NRZ format This is composed of one start bit eight or nine data bits a...

Page 126: ... immediately suspended and the UART will be reset to a condition as defined above If the UART is then subsequently re enabled it will restart again in the same configuration Data Parity and Stop Bit Selection The format of the data to be transferred is composed of various factors such as data bit length parity on off parity type address bits and the number of stop bits These factors are determined...

Page 127: ...ft register with the least significant bit first In the transmit mode the TXR register forms a buffer between the internal bus and the transmitter shift register It should be noted that if 9 bit data format has been selected then the MSB will be taken from the TX8 bit in the UCR1 register The steps to initiate a data transfer can be summarized as follows Make the correct selection of the BNO PRT P...

Page 128: ...er is empty The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin It should be noted that the RSR register unlike many other registers is not directly mapped into the Data Memory area and as such is not available to the application program for direct read write operations Receivi...

Page 129: ...R RIDLE or RXIF flags will possibly be set Idle Status When the receiver is reading data which means it will be in between the detection of a start bit and the reading of a stop bit the receiver status flag in the USR register otherwise known as the RIDLE flag will have a zero value In between the reception of a stop bit and the detection of the next start bit the RIDLE flag will have a high value...

Page 130: ... Structure Several individual UART conditions can generate a UART interrupt When these conditions exist a low pulse will be generated to get the attention of the microcontroller These conditions are a transmitter data register empty transmitter idle receiver data available receiver overrun address detect and an RX pin wake up When any of these conditions are created if its corresponding interrupt ...

Page 131: ...eme Address Detect Mode Setting the Address Detect Mode bit ADDEN in the UCR2 register enables this special mode If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt which is requested by the RXIF flag If the ADDEN bit is 1 then when data is available an interrupt will only be generated if the highest received bit has a high va...

Page 132: ...microcontroller enters the IDLE or SLEEP mode The UART function contains a receiver RX pin wake up function which is enabled or disabled by the WAKE bit in the UCR2 register If this bit along with the UART enable bit UARTEN the receiver enable bit RXEN and the receiver interrupt bit RIE are all set before the device enters the IDLE0 or SLEEP Mode then a falling edge on the RX pin will wake up the ...

Page 133: ... registers located in the Special Purpose Data Memory as shown in the accompanying table The registers fall into two categories The first is the INTC0 INTC3 registers which setup the primary interrupts the second is the INTEG register to setup the external interrupt trigger edge type Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags...

Page 134: ...ag 0 No request 1 Interrupt request Bit 5 TKMF Touch key module interrupt request flag 0 No request 1 Interrupt request Bit 4 INTF INT pin interrupt request flag 0 No request 1 Interrupt request Bit 3 TB0E Time Base 0 interrupt control 0 Disable 1 Enable Bit 2 TKME Touch key module interrupt control 0 Disable 1 Enable Bit 1 INTE INT pin interrupt control 0 Disable 1 Enable Bit 0 EMI Global Interru...

Page 135: ...M0 CCRP comparator interrupt control 0 Disable 1 Enable INTC2 Register Bit 7 6 5 4 3 2 1 0 Name UARTF DEF IICF TB1F UARTE DEE IICE TB1E R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 UARTF UART interrupt request flag 0 No request 1 Interrupt request Bit 6 DEF Data EEPROM interrupt request flag 0 No request 1 Interrupt request Bit 5 IICF I2 C interrupt request flag 0 No request 1 Int...

Page 136: ...nother section of program which is known as the interrupt service routine Here is located the code to control the appropriate interrupt The interrupt service routine must be terminated with a RETI which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred The various interrupt enable...

Page 137: ...ust first be set Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type As the external interrupt pin is pin shared with I O pin it can only be configured as external interrupt pin if its external interrupt enable bit in the corresponding interrupt register has been set The pin must also b...

Page 138: ...e of the Time Base Interrupt is to provide an interrupt signal at fixed time periods Each Time Base clock source originates from an independent internal prescaler Each 15 bit prescaler can source from fSYS fSYS 4 fSUB or fH selected by CLKSELn1 CLKSELn0 bits in the PSCR register PSCR Register Bit 7 6 5 4 3 2 1 0 Name CLKSEL11 CLKSEL10 CLKSEL01 CLKSEL00 R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimp...

Page 139: ...n happens To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI the respective TM interrupt enable bit must first be set When the interrupt is enabled the stack is not full and a TM comparator match situation occurs a subroutine call to the relevant TM interrupt vector location will take place When the TM interrupt is serviced the TM interrup...

Page 140: ... the I2 C Interrupt request flag IICF is set which occurs when an address match occurs or an I2 C communication time out occurs or a byte of data has been received or transmitted by the I2 C interface To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and the I2 C Interface Interrupt enable bit IICE must first be set When the interrupt is ...

Page 141: ... until the request flag is cleared by the application program It is recommended that programs do not use the CALL instruction within the interrupt service subroutine Interrupts often occur in an unpredictable manner or need to be serviced immediately If only one stack is left and the interrupt is not well controlled the original control sequence will be damaged once a CALL subroutine is executed i...

Page 142: ...ring the I O pins as segment pins The LCD driver function is controlled using the LCD control registers which in addition to controlling the overall on off function also controls the SCOM and SSEG operating current This enables the LCD COM and SEG driver to generate the necessary VSS 1 3 VDD 2 3 VDD voltage and VDD levels for LCD 1 3 bias operation The LCDEN bit in the SLCDC0 register is the overa...

Page 143: ... the application program Note that the depiction of a 1 in the diagram illustrates an illuminated LCD pixel The COM signal polarity generated on pins SCOM0 SCOM3 whether 0 or 1 are generated using the corresponding I O data register bits which are bits PA0 PA2 PA4 in the PA register Note The logical values shown in the diagram are the PA I O register bit values PA0 PA2 PA4 1 3 Bias LCD Waveform ...

Page 144: ...he respective SEG pin to determine whether the SEG0 SEGn output has a value of either VDD VSS or Vbias LCD Bias Control The LCD COM and SEG driver enable a range of selections to be provided to suit the requirement of the LCD panel which are being used The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SLCDC0 register SLCDC0 Register Bit 7 6 5 4 3 2 1 0 Name FRAME ISEL1 ...

Page 145: ...unction 1 SSEG7 SSEG0 SLCDC2 Register Bit 7 6 5 4 3 2 1 0 Name SEG15EN SEG14EN SEG13EN SEG12EN SEG11EN SEG10EN SEG9EN SEG8EN R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 SEG15EN SEG8EN SSEG15 SSEG8 or other function selection 0 Other function 1 SSEG15 SSEG8 SLCDC3 Register BS82C16A 3 BS82D20A 3 Bit 7 6 5 4 3 2 1 0 Name SEG19EN SEG18EN SEG17EN SEG16EN R W R W R W R W R W POR 0 0 ...

Page 146: ...on is indicated when the LVDO bit is set If the LVDO bit is low this indicates that the VDD voltage is above the preset low voltage value The LVDEN bit is used to control the overall on off function of the low voltage detector Setting the bit high will enable the low voltage detector Clearing the bit to zero will switch off the internal low voltage detector circuits As the low voltage detector wil...

Page 147: ...e Low Voltage Detector a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit Note also that as the VDD voltage may rise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions LVD Operation The Low Voltage Detector also has its own interrupt providing an alternative means of low voltage detection in addition to p...

Page 148: ...ing tools once they are selected they cannot be changed later using the application program All options must be defined for proper system function the details of which are shown in the table No Options Oscillator Option 1 Low Speed System Oscillator Selection fSUB LIRC LXT 2 HIRC frequency selection 8MHz 12MHz 16MHz Note 1 The low speed system oscillator selection is only for the BS82C16A 3 and BS...

Page 149: ...3 2015 BS82B12A 3 BS82C16A 3 BS82D20A 3 Touch Key 8 Bit Flash MCU with LED LCD Driver Application Circuit VDD VSS KEY1 0 1 F I O Pins I2 C Pins VDD KEY2 KEYn UART Pins SCOM SSEG Pins XT1 XT2 OSC Ci c it See Oscillato Section ...

Page 150: ...also take one more cycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is invo...

Page 151: ...useful set of branch instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined b...

Page 152: ...t in Data Memory 1Note Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory 1Note Z AND A x L...

Page 153: ... Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDC m Read table current page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR m Clear Data Memory 1Note None SET m Set Data Memo...

Page 154: ...nts of the Accumulator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC...

Page 155: ... Description The TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Repetitively executing this instruction without alternately executing C...

Page 156: ...ay be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected flag s C DEC m Decrement Data Memory Description Data in the specified Data Memory is decremented by 1 Operation m m 1 Affected flag s Z DECA m Decrement Data Memory with result in ACC D...

Page 157: ...a Memory Operation m ACC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation The result is stored in the Accumulator Operation ACC ACC OR m Affe...

Page 158: ...e RLA m Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 m 7 Affected flag s None RLC m Rotate Data Memory left through Carry Description The contents of the spe...

Page 159: ...fected flag s C SBC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive or zero the C flag will be set to 1 Operation ACC...

Page 160: ...result is not 0 the program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped The result is stored in the Accumulator but the specified Data Memory contents rem...

Page 161: ...fied Data Memory are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruct...

Page 162: ...page to TBLH and Data Memory Description The low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logi...

Page 163: ... may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Further Package Information include Outline Dimensions Product Tape and Reel Specifications Packing Meterials...

Page 164: ...0mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 406 BSC C 0 012 0 020 C 0 504 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 5 BSC C 7 5 BSC C 12 8 BSC D 12 8 BSC E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 40 1 27 α 0 8 ...

Page 165: ...00mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 606 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 5 BSC C 0 31 0 51 C 15 4 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 166: ...00mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 705 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 5 BSC C 0 31 0 51 C 17 9 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 167: ... 150mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 390 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 20 0 30 C 9 9 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 168: ...ioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or sys...

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