Hitachi HTS543212L9A300 Oem Specification Download Page 26 | Manualshive

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5K320 SATA OEM Specification

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6.1.3

Radiation noise

The disk drive shall work without degradation of the soft error rate under the following magnetic flux
density limits at the enclosure surface.

Frequency (KHz)

Limits (uT RMS)

DC

1500 0-p

0 < Frequency =< 60

500 RMS

60 < Frequency =<100

250 RMS

100 < Frequency =< 200

100 RMS

200 < Frequency =< 400

50 RMS

Table 13. Magnetic flux density limits

6.1.4

Conductive noise

The disk drive shall work without soft error degradation in the frequency range from DC to 20 Mhz
injected through any two of the mounting screw holes of the drive when an AC current of up to 45 mA
(p-p) is applied through a 50-ohm resistor connected to any two mounting screw holes.

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Summary of Contents for HTS543212L9A300

Page 1: ...Disk Drive Specification Hitachi Travelstar 5K320 2 5 inch SATA hard disk drive Models HTS543232L9A300 HTS543232L9SA00 HTS543225L9A300 HTS543225L9SA00 HTS543216L9A300 HTS543216L9SA00 HTS543212L9A300 HTS543212L9SA00 HTS543280L9A300 HTS543280L9SA00 Revision 1 2 03 April 2008 ...

Page 2: ...ay make improvements or changes in any products or programs described in this publication at any time It is possible that this publication may contain reference to or information about Hitachi products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Hitachi intends to announce such Hitachi produc...

Page 3: ... 5 5 Data buffer test 23 5 6 Error recovery 23 5 7 Automatic reallocation 23 5 8 ECC 24 6 SPECIFICATION 25 6 1 Environment 25 6 2 DC power requirements 27 6 3 Reliability 29 6 4 Mechanical specifications 32 6 5 Vibration and shock 34 6 6 Acoustics 36 6 7 Identification labels 37 6 8 Electromagnetic compatibility 37 6 9 Safety 38 6 10 Packaging 38 6 11 Substance restriction requirements 38 7 ELECTR...

Page 4: ...OCOL 72 13 1 Data In Commands 72 13 2 Data Out Commands 72 13 3 Non Data Commands 73 13 4 DMA Data Transfer Commands 74 13 5 First parity DMA Commands 74 14 COMMAND DESCRIPTIONS 75 14 1 Check Power Mode E5h 98h 79 14 2 Device Configuration Overlay B1h 80 14 3 Download Microcode 92h 84 14 4 Execute Device Diagnostic 90h 86 14 5 Flush Cache E7h 87 14 6 Flush Cache Ext EAh 88 14 7 Format Track 50h Ve...

Page 5: ... 52 Write Sector s 30h 31h 171 14 53 Write Sector s Ext 34h 172 14 54 Write Uncorrectable Ext 45h 173 15 TIMINGS 175 List of Figures Figure 1 Limits of temperature and humidity 25 Figure 2 Mounting hole locations 32 Figure 3 Interface connector pin assignments 39 Figure 4 Parameter descriptions 42 Figure 5 Initial Setting 60 Figure 6 Usual Operation 61 Figure 7 Password Lost 62 Figure 8 Set Max se...

Page 6: ...1h 80 Table 45 Device Configuration Overlay Features register values 80 Table 46 Device Configuration Overlay Data structure 82 Table 47 DCO error information definition 83 Table 48 Download Command 92h 84 Table 49 Execute Device Diagnostic Command 90h 86 Table 50 Flush Cache Command E7h 87 Table 51 Flush Cache EXT Command EAh 88 Table 52 Format Track Command 50h 89 Table 53 Format Unit Command F7...

Page 7: ...k Information 134 Table 103 Seek Command 7xh 135 Table 104 Sense Condition Command F0h 136 Table 105 Set Features Command EFh 137 Table 106 Set Max Address Command F9h 139 Table 107 Set Max Address Ext Command 37h 141 Table 108 Set Multiple Command C6h 143 Table 109 Sleep Command E6h 99h 144 Table 110 S M A R T Function Set Command B0h 145 Table 111 Log sector addresses 148 Table 112 Device Attrib...

Page 8: ...5K320 SATA OEM Specification 8 Table 137 Write Sector s Ext Command 34h 172 Table 138 Write Uncorrectable Ext Command 45h 173 Table 139 Timeout Values 175 ...

Page 9: ...A300 3 0 Travelstar 5K320 160 HTS543216L9SA00 1 5 160 9 5 5400 HTS543212L9A300 3 0 Travelstar 5K320 120 HTS543212L9SA00 1 5 120 9 5 5400 HTS543280L9A300 3 0 Travelstar 5K320 80 HTS543280L9SA00 1 5 80 9 5 5400 1 1 Abbreviations Abbreviation Meaning 32 KB 32 x 1024 bytes 64 KB 64 x 1024 bytes inch A amp AC alternating current AT Advanced Technology ATA Advanced Technology Attachment Bels unit of sou...

Page 10: ...ILS integrated lead suspension imped impedance I O Input Output ISO International Standards Organization KB 1 000 bytes Kbit mm 1 000 bits per mm Kbit sq mm 1000 bits per square mm KHz kilohertz LBA logical block addressing Lw unit of A weighted sound power m meter max or Max maximum MB 1 000 000 bytes Mbps 1 000 000 Bit per second Mb sec 1 000 000 Bit per second MB sec 1 000 000 bytes per second ...

Page 11: ...requency interference RH relative humidity RH per cent relative humidity RMS root mean square RPM revolutions per minute RST reset R W read write sec second Sect Trk sectors per track SELV secondary low voltage S M A R T Self monitoring analysis and reporting technology Trk track TTL transistor transistor logic UL Underwriters Laboratory V volt VDE Verband Deutscher Electrotechniker W watt 3 state...

Page 12: ...hole on the top cover See figure below Do not touch the interface connector pins or the surface of the printed circuit board The drive can be damaged by shock or ESD Electric Static Discharge Any damages incurred to the drive after removing it from the shipping package and the ESD protective bag a re the responsibility of the user 1 4 Drive handling precautions Do not press on the drive cover duri...

Page 13: ...ead Solomon code Non interleave On The Fly correction Included 2 symbol system ECC Segmented Buffer with write cache 8192 KB Upper 736 KB is used for firmware Fast data transfer rate HTS5432xxL9A3xx model up to 3 0Gbit s HTS5432xxL9SAxx model up to 1 5Gbit s Media data transfer rate max 775 Mb s Average seek time 1 2 ms for read Closed loop actuator servo Embedded Sector Servo Rotary voice coil mo...

Page 14: ...5K320 SATA OEM Specification 14 Part 1 Functional Specification ...

Page 15: ...tor Servo Ÿ No ID TM formatting Ÿ Multizone recording Ÿ Code 100 102 bit parity 199 200 RC Modulation Encoding Ÿ System ECC Ÿ Enhanced Adaptive Battery Life Extender 3 2 Head disk assembly data The following technologies are used in the drive Ÿ Femto Slider Ÿ Perpendicular recording disk and write head Ÿ TMR head Ÿ Integrated lead suspension ILS Ÿ Load unload mechanism Ÿ Mechanical latch ...

Page 16: ... Sectors 625 142 448 488 397 168 Total Logical Data Bytes 320 072 933 376 250 059 350 016 Description HTS543216L9A300 HTS543216L9SA00 HTS543212L9A300 HTS543212L9SA00 HTS543280L9A300 HTS543280L9SA00 Physical Layout Bytes per Sector 512 512 512 Number of Heads 2 2 1 Number of Disks 1 1 1 Logical Layout Number of Heads 16 16 16 Number of Sectors Track 63 63 63 Number of Cylinders 16 383 16 383 16 383...

Page 17: ...e 2 Data sheet 4 3 Cylinder allocation Data format is allocated by each head characteristics Typical format is described below 160GB p Mid BIP Mid TPI format Zone Cylinder No of Sectors Trk 0 0 8187 1512 1 8188 12103 1476 2 12104 19045 1440 3 19046 26076 1404 4 26077 29903 1377 5 29904 35866 1350 6 35867 40672 1323 7 40673 49750 1269 8 49751 55624 1242 9 55625 59273 1224 10 59274 66126 1188 11 661...

Page 18: ... characteristics of the drive This specification does not include the system throughput as this is dependent upon the system and the application The following table gives a typical value for each parameter Function Average Random Seek Time Read ms 12 Average Random Seek Time Write ms 13 Rotational Speed RPM 5400 Power on to ready sec 3 5 Command overhead ms 1 0 Disk buffer data transfer Mb s max 7...

Page 19: ...yed to correct arrival problems The Average Seek Time is measured as the weighted average of all possible seek combinations max Σ max 1 n Tnin Tnout n 1 Weighted Average max 1 max Where max maximum seek length n seek length 1 to max Tnin inward measured seek time for an n track seek Tnout outward measured seek time for an n track seek 4 4 2 2 Full stroke seek Command Type Typical ms Max ms Read 20...

Page 20: ...ypical sec Max sec Power On To Ready 3 5 9 5 Table 9 Drive ready time Ready The condition in which the drive is able to perform a media access command for example read write immediately Power On To Ready This includes the time required for the internal self diagnostics ...

Page 21: ...tating at full speed Standby The device interface is capable of accepting commands The spindle motor is stopped All circuitry but the host interface is in power saving mode The execution of commands is delayed until the spindle becomes ready Sleep The device requires a soft reset or a hard reset to be activated All electronics including spindle motor and host interface are shut off Table 10 Operat...

Page 22: ...and Ÿ Standby Immediate command Ÿ Sleep command Confirm the command s completion 5 3 Equipment status The equipment status is available to the host system any time the drive is not ready to read w rite or seek This status normally exists at the power on time and will be maintained until the following conditions are satisfied Ÿ The access recalibration tuning is complete Ÿ The spindle speed meets t...

Page 23: ...e operation cannot be completed after the Error Recovery Procedure ERP is fully carried out the sectors are reallocated to the spare location An error is reported to the host system only when the write cache is disabled and the auto reallocation has failed 5 7 2 Nonrecoverable read error When a read operation fails after ERP is fully carried out a hard error is reported to the host system This loc...

Page 24: ...he first 6 symbol of ECC are 4 check symbols for user data and the 2 symbol system ECC The other 34 symbols are Read Solomon ECC Hardware logic corrects up to 16 symbols 20 bytes errors on the fly 2 symbol System ECC is generated when HDC receives user data from HOST and can correct up to 1 symbol 10bit errors on the fly when one transfers to HOST ...

Page 25: ...em is responsible for providing sufficient air movement to maintain surface temperatures below 60 C at the center of top cover and below 63 C at the center of the drive circuit board assembly The maximum storage period in the shipping package is one year Specification Environment 0 10 20 30 40 50 60 70 80 90 100 45 35 25 15 5 5 15 25 35 45 55 65 Temperature degC Relative Humidity Operating Non Ope...

Page 26: ... Frequency 60 500 RMS 60 Frequency 100 250 RMS 100 Frequency 200 100 RMS 200 Frequency 400 50 RMS Table 13 Magnetic flux density limits 6 1 4 Conductive noise The disk drive shall work without soft error degradation in the frequency range from DC to 20 Mhz injected through any two of the mounting screw holes of the drive when an AC current of up to 45 mA p p is applied through a 50 ohm resistor co...

Page 27: ...verage 5 2 2 Standby 0 2 Sleep 0 1 Startup maximum peak 6 5 0 Average from power on to ready 3 8 Table 14 DC Power requirements Footnotes 1 The maximum fixed disk ripple is measured at the 5 volt input of th e drive 2 The disk drive shall not incur damage for an over voltage condition of 25 maximum duration of 20 ms on the 5 volt nominal supply 3 The idle current is specified at an inner track 4 T...

Page 28: ...iciency Capacity 320GB 250GB 160GB 120GB 80GB Power Consumption Efficiency Watts GB 0 0017 0 0022 0 0034 0 0046 0 0069 Table 15 Power consumption efficiency Note Power consumption efficiency is calculated as Power Consumption of Low Power Idle Watt Capacity GB ...

Page 29: ...e life and usage condition The drive is designed to be used under the following conditions Ÿ The drive should be operated within specifications of shock vibration temperature humidity altitude and magnetic field Ÿ The drive should be protected from ESD Ÿ The breathing hole in the top cover of the drive should not be covered Ÿ Force should not be applied to the cover of the drive Ÿ The specified po...

Page 30: ...erently uncontrolled it is more mechanically stressful than a normal unload The drive supports a minimum of 20 000 emergency unloads 6 3 6 2 Required Power Off Sequence The required host system sequence for removing power from the drive is as follows Ÿ Step 1 Issue one of the following commands Ÿ Standby Ÿ Standby immediate Ÿ Sleep Note Do not use the Flush Cache command for the power off sequence...

Page 31: ...unload function Start Stop testing should be done by commands through the interface not by power cycling the drive Simple power cycling of the drive invokes the emergency unload mechanism and subjects the HDD to nontypical mechanical stress Power cycling testing may be required to test the boot up function of the system In this case HItachi recommends that the power off portion of the cycle contai...

Page 32: ...r the drive Model Height mm Width mm Length mm Weight gram 320GB 250GB models 9 5 0 2 69 85 0 25 100 2 0 25 102 Max 160GB 120GB 80GB models 9 5 0 2 69 85 0 25 100 2 0 25 95 Max Table 16 Physical dimensions and weight 6 4 2 Mounting hole locations The mounting hole locations and size of the drive are shown below Figure 2 Mounting hole locations ...

Page 33: ...rientation will be able to run vertically and vice versa The recommended mounting screw torque is 0 3 0 05 Nm The recommended mounting screw depth is 3 0 0 3 mm for bottom and 3 5 0 5 mm for horizontal mounting The user is responsible for using the appropriate screws or equivalent mounting hardware to mount the drive securely enough to prevent excessive motion or vibration of the drive at seek ope...

Page 34: ...ted to the following vibration levels 6 5 1 1 Random vibration The test consists of 30 minutes of random vibration using the power spectral density PSD levels below The vibration test level is 6 57 m sec 2 RMS Root Mean Square 0 67 G RMS Random vibration PSD profile Breakpoint Hz m x 10n m2 sec4 Hz 5 1 9 x E 3 17 1 1 x E 1 45 1 1 x E 1 48 7 7 x E 1 62 7 7 x E 1 65 9 6 x E 2 150 9 6 x E 2 200 4 8 x...

Page 35: ...ets the criteria in the table below while operating under these conditions Ÿ The shock test consists of 10 shock inputs in each axis and direction for a total of 60 Ÿ There must be a minimum delay of 3 seconds between shock pulses Ÿ The disk drive will operate without a hard error while subjected to the following half sine shock pulse Duration of1 ms Duration of 2 ms 1960 m sec 2 200 G 3920 m sec ...

Page 36: ...all be us ed The acoustical characteristics of the disk drive are measured under the following conditions Mode definitions Ÿ Idle mode Power on disks spinning track following unit ready to receive and respond to control line commands Ÿ Operating mode Continuous random cylinder selection and seek operation of the actuator with a dwell time at each cylinder The seek rate for the drive can be calcula...

Page 37: ...ession German National Requirements RFI Japan VCCI Requirements of HITACHI products EU EMC Directive Technical Requirements and Conformity Assessment Procedures 6 8 1 CE Mark The product is certified for compliance with EC directive 89 336 EEC The EC marking for the certification appears on the drive 6 8 2 C Tick Mark The product complies with the Australian EMC standard Limits and methods of meas...

Page 38: ... a UL recognized flammability rating of V 1 or better except minor mechanical parts 6 9 5 Secondary circuit protection This product utilizes p rinted circuit wiring that m ust be protected against the possibility of sustained combustion due to circuit or component failures as defined in C B 2 4700 034 Protection Against Combustion Adequate secondary over current protection is the responsibility of...

Page 39: ...ne blind mate connector only In this case the mating sequences are 1 the ground pins P4 and P12 2 the pre charge power pins and the other ground pins and 3 the signal pins and the rest of the power pins l There are three power pins for each voltage One pin from each voltage is used for pre charge in the backplane blind mate situation l If a device uses 3 3V then all V33 pins must be terminated Oth...

Page 40: ...V12 12V power pre chage 2nd mate V12 P14 V12 12V power V12 P15 V12 12V power V12 Table 23 Interface connector pins and I O signals Note 1 Pin P11 is used by the drive to provide the host with an activity indication and by the host to indicate whether staggered spinup should be used The signal the drive provides for activity indication is a low voltage low current driver If pin P11 is asserted low ...

Page 41: ...5K320 SATA OEM Specification 41 ...

Page 42: ...ling Figure 4 shows the timing of COMRESET COMINIT and COMWAKE COMRESET COMI NI T t1 t2 t3 t4 C O M W A K E PARAMETER DESCRIPTION Nominal ns T1 ALINE primitives 106 7 T2 Spacing 320 T3 ALIGN primitives 106 7 T4 Psacing 106 7 Figure 4 Parameter descriptions ...

Page 43: ...5K320 SATA OEM Specification 43 ...

Page 44: ...5K320 SATA OEM Specification 44 Part 2 Interface Specification ...

Page 45: ...ndard on Page 45 Serial ATA International Organization Serial ATA Revision 2 6 dated on 15 February 2007 AT Attachment 8 ATA ATAPI Command Set ATA8 ACS Revision 3f dated on 11 December 2006 HTS5432XXL9SA00 HTS5432XXL9A300 support following functions as Vendor Specific Function Format Unit Function SENSE CONDITION command 8 2 Terminology Device Device indicates HTS5432XXL9SA00 HTS5432XXL9A300 Host ...

Page 46: ...Sector Count Register when the device is in Idle mode This command does not support 80h as the return value 10 Physical Interface Physical Interface is described in Functional Specification part 11 Registers In Serial ATA the host adapter contains a set of registers that shadow the contents of the traditional device registers referred to as the Shadow Register Block Shadow Register Block registers...

Page 47: ... count exp Sector count previous Sector count HOB 1 LBA low LBA low current LBA low HOB 0 LBA low exp LBA low previous LBA low HOB 1 LBA mid LBA mid current LBA mid HOB 0 LBA mid exp LBA mid previous LBA mid HOB 1 LBA high LBA high current LBA mid HOB 0 LBA high exp LBA high previous LBA mid HOB 1 Device Device Device Command Command N A Control Device Control N A Status N A Status Error N A Error...

Page 48: ...by the device or a diagnostic code At the completion of any command except Execute Device Diagnostic the cont ents of this register are valid always even if ERR 0 in the Status Register Following a power on a reset or completion of an Execute Device Diagnostic command this register contains a diagnostic code See Table 31 Diagnostic Codes on Page 52 for the definition Bit Definitions ICRCE CRC Inte...

Page 49: ...e transferred on a read or write operation between the host and the device If the value in the register is set to 0 a count of 256 sectors in 28 bit addressing or 65 536 sectors in 48 bit addressing is specified If the register is zero at command completion the command was successful If not successfully completed the register contains the number of sectors which need to be transferred in order to ...

Page 50: ...an error occurs this bit is not changed until the Status Register is read by the host at which time the bit again indicates the current seek complete status When the device enters into or is in Standby mode or Sleep mode this bit is set by device in spite of not spinning up DRQ Data Request DRQ 1 indicates that the device is ready to transfer a word or byte of data between the host and the device ...

Page 51: ...ternal diagnostic O x x Starting spindle motor 5 x x Initialization of registers 2 O o o Reverting programmed parameters to default O 6 3 Number of CHS set by Initialize Device Parameter Multiple mode Write cache Read look ahead ECC bytes Volatile max address Power mode 5 4 4 Reset Standby timer value o o x O execute X not execute Note 1 Execute after the data in write cache has been written 2 Def...

Page 52: ...er microprocessor error Table 31 Diagnostic Codes 12 2 Diagnostic and Reset considerations The Set Max password the Set Max security mode and the Set Max unlock counter don t retain over a Power On Reset but persist over a COMRESET or Soft Reset For each Reset and Execute Device Diagnostic the Diagnostic is done as follows Execute Device Diagnostic In all the above cases P ower on COMRESET Soft re...

Page 53: ...be invoked in rare situations Because this operation is inherently uncontrolled it is more mechanically stressful than a normal unload A single emergency unload operation is more stressful than 100 normal unloads Use of emergency unload reduces the start stop life of the HDD at a rate at least 100X faster than that of normal unload and may damage the HDD 12 3 3 Required power off sequence Problems...

Page 54: ...e number of sectors per logical track and the number of heads per logical cylinder The device then computes the number of logical cylinders available in requested mode The default CHS translation mode is described in the Identify Device Information The current CHS translation mode also is described in the Identify Device Information 12 4 2 LBA Addressing Mode Logical sectors on the device shall be...

Page 55: ...ired to move a device out of sleep mode When a device exits sleep mode it will enter standby mode The Standby and Standby Immediate commands move a device to standby mode immediately from the active or idle modes The standby command also sets the standby timer count 12 5 3 Standby Sleep command completion timing 1 Confirm the completion of writing cached data in the buffer to media 2 Unload heads ...

Page 56: ...d Power Management feature is independent of the Standby timer setting If both Advanced Power Management level and the Standby timer are set the device will go to the Standby state when the timer times out or the device s Advanced Power Management algorithm indicates that it is time to enter the Standby state The IDENTIFY DEVICE response word 83 bit 3 indicates that Advanced Power Management featu...

Page 57: ...event unscheduled system downtime that may be caused by predictable degradation and or fault of the device By monitoring and storing critical performance and calibration parameters S M A R T devices employ sophisticated data analysis algorithms to predict the likelihood of near term degradation or fault condition By alerting the host system of a negative reliability status condition the host syste...

Page 58: ...ty condition 12 8 5 S M A R T commands The S M A R T commands provide access to attribute values attribute thresholds and other logging and reporting information 12 8 6 S M A R T operation with power management modes The device saves attribute values automatically on every head unload timing except the emergency unload even if the attribute auto save feature is not enabled The head unload is done ...

Page 59: ...r Password The User Password should be given or changed by a system user When the User Password is set the device enables the Device Lock Function and then the device is locked on next power on reset If Software Setting Preservation is disabled the device is locked on COMRESET as well The system manufacturer dealer who intends to enable the device lock function for the end users must set the maste...

Page 60: ...cification 60 Figure 5 Initial Setting Operation from POR after User Password is set When Device Lock Function is enabled the device rejects media access command until a Security Unlock command is successfully completed ...

Page 61: ...d Lost If the User Password is forgotten and High level security is set the system user can t access any data However the device can be unlocked using the Master Password If a system user forgets the User Password and Maximum security level is set data access is impossible However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the...

Page 62: ...match If the password does not match the device counts it up without distinguishing the Master password and the User password If the count reaches 5 EXPIRE bit bit 4 of Word 128 in Identify Device information is set and then SECURITY ERASE UNIT command and SECURITY UNLOCK command are aborted until a power off The count and EXPIRE bit are cleared after a power on reset 12 9 6 Command Table This tab...

Page 63: ...mmediate with Unload option o o o Initialize Device Parameters o o o Read Buffer o o o Read DMA x o o Read DMA Ext x o o Read FPDMA Queued x o o Read Log Ext o o o Read Multiple x o o Read Multiple Ext x o o Read Native Max Address o o o Read Native Max Address Ext o o o Read Sector s x o o Read Sector s Ext x o o Read Verify Sector s x o o Read Verify Sector s Ext x o o Recalibrate o o o Security...

Page 64: ...ffer o o o Write DMA x o o Write DMA Ext x o o Write DMA FUA Ext x o o Write FPDMA Queued x o o Write Log Ext x o o Write Multiple x o o Write Multiple Ext x o o Write Multiple FUA Ext x o o Write Sector s x o o Write Sector s Ext x o o Write Uncorrectable Ext x o o Table 36 Command table for device lock operation continued 12 10 Protected Area Function Protected Area Function is to provide the pr...

Page 65: ...essible including the protected area by setting device Max LBA as 0FFFFFh via Set Max Address command The option could be either nonvolatile or volatile Test the sectors for protected area LBA 0FC000h if required Write information data such as BIOS code within the protected area Change maximum LBA using Set Max Address command to 0FBFFFh with nonvolatile option From this point the protected area c...

Page 66: ... the Set Max Locked mode to the Set Max Unlocked mode This command requests a transfer of a single sector of data from the host The Table shown above defines the content of this sector of information The password supplied in the sector of data transferred is compared with the stored Set Max password If the password compare fails then the device returns command aborted and decrements the unlock cou...

Page 67: ...ncement whereby the device reports completion of the write command Write Sector s and Write Multiple to the host as soon as the device has received all of the data into its buffer The device assumes responsibility to write the data subsequently onto the disk l While writing data after completed acknowledgment of a write command soft reset or COMRESET does not affect its operation But power off ter...

Page 68: ...covered at the specific ERP step this sector of data is reallocated automatically A media verification sequence may be run prior to the relocation according to the pre defined conditions 12 14 48 bit Address Feature Set The 48 bit Address feature set allows devices with capacities up to 281 474 976 710 655 sectors This allows device capacity up to 144 115 188 075 855 360 bytes In addition the numb...

Page 69: ...f there is an asynchronous loss of signal Since COMRESET is equivalent to hardware reset in the case of an asynchronous loss of signal some software settings may be lost without legacy software knowledge In order to avoid losing important software settings without legacy driver knowledge the software settings preservation ensures that the value of important software settings is maintained across a...

Page 70: ...ATA II Sp ecification about Native Command Queuing The host shall not issue a legacy ATA command while a native queued command is outstanding Upon receiving a legacy ATA command while a native queued command is outstanding the device aborts the command and halts command processing of outstanding native queued commands 12 17 SMART Command Transport SCT SMART Command Transport SCT feature set is sup...

Page 71: ...tion 71 0003h Error Recovery Control command Feature Control command Feature code 0001h Write Cache 0004h Feature code 0003h Time Interval for temperature logging 0005h SCT Data Table command Table 39 SCT Action Code Supported ...

Page 72: ...he host reads the Status Register issues a reset or writes to the Command Register Table 139Timeout Values on P age 175 shows the device timeout values 13 1 Data In Commands These commands are l Device Configuration Identify l Identify Device l Read Buffer l Read Log Ext l Read Multiple l Read Multiple Ext l Read Sector s l Read Sector s Ext l S M A R T Read Attribute Values l S M A R T Read Attri...

Page 73: ...e select bit bit 6 of Device register on issuing the command 13 3 Non Data Commands These commands are l Check Power Mode l Device Configuration Freeze Lock l Device Configuration R estore l Execute Device Diagnostic l Flush Cache l Flush Cache Ext l Format Unit l Idle l Idle Immediate l Idle Immediate with Unload option l Initialize Device Parameters l Read Native Max Address l Read Native Max Ad...

Page 74: ...channel prior to issuing the command The DMA protocol allows high performance multi tasking operating systems to eliminate processor overhead associated with PIO transfers Refer Functional Specification part for further details 13 5 First parity DMA Commands These commands are l Read FPDMA Queued l Write FPDMA Queued Execution of this class of commands includes command queuing and the transfer of ...

Page 75: ...Device Parameters 91 1 0 0 1 0 0 0 1 1 Read Buffer E4 1 1 1 0 0 1 0 0 4 Read DMA C8 1 1 0 0 1 0 0 0 4 Read DMA C9 1 1 0 0 1 0 0 1 4 Read DMA Ext 25 0 0 1 0 0 1 0 1 5 Read FPDMA Queued 60 0 1 1 0 0 0 0 0 1 Read Log Ext 2F 0 0 1 0 1 1 1 1 1 Read Multiple C4 1 1 0 0 0 1 0 0 1 Read Multiple Ext 29 0 0 1 0 1 0 0 1 3 Read Native Max Address F8 1 1 1 1 1 0 0 0 3 Read Native Max Address Ext 27 0 0 1 0 0 1...

Page 76: ...1 0 1 1 0 0 0 0 3 S M A R T Save Attribute Values B0 1 0 1 1 0 0 0 0 2 S M A R T Write Log Sector B0 1 0 1 1 0 0 0 0 3 Standby E2 1 1 1 0 0 0 1 0 3 Standby 96 1 0 0 1 0 1 1 0 3 Standby Immediate E0 1 1 1 0 0 0 0 0 3 Standby Immediate 94 1 0 0 1 0 1 0 0 2 Write Buffer E8 1 1 1 0 1 0 0 0 4 Write DMA CA 1 1 0 0 1 0 1 0 4 Write DMA CB 1 1 0 0 1 0 1 1 4 Write DMA Ext 35 0 0 1 1 0 1 0 1 4 Write DMA FUA ...

Page 77: ...anagement feature EF 85 Disable Power Up in Standby feature EF 86 Disable use of Serial ATA featu re EF 90 Enable read look ahead feature EF AA Disable AAM EF C2 Enable reverting to power on defaults EF CC Set Max security extension Set Max Set Password F9 01 Set Max Lock F9 02 Set Max Unlock F9 03 Set Max Freeze Lock F9 04 Device Configuration Overlay Device Configuration Restore B1 C0 Device Con...

Page 78: ...he bit is not used Input Registers 0 Indicates that the bit is always set to 0 1 Indicates that the bit is always set to 1 H Head number Indicates that the head number part of the Device Register is an input parameter and will be set by the device V Valid Indicates that the bit is part of an input parameter and will be set to 0or 1 by the device N Not recommendable condition for start up Indicates...

Page 79: ...r Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 0 0 0 0 V Table 43 Check Power Mode Command E5h 98h The Check Power Mode command will report whether the device is spun up and the media is available for immediate access Input Parameters From The Device Sector Count The power mode code The command returns FFh in...

Page 80: ...EVICE CONFIGURATION IDENTIFY C3h DEVICE CONFIGURATION SET other Reserved Table 45 Device Configuration Overlay Features register values 14 2 1 DEVICE CONFIGURATION RESTORE subcommand C0h The DEVICE CONFIGURATI ON RESTORE command discard any setting previously made by a DEVICE CONFIGURATION SET command and return the content of the IDENTIFY DEVICE command response to the original settings as indica...

Page 81: ...the indicated command mode or feature set If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit The format of the overlay transmitted by the device is described in the table at next page The restrictions on changing these bits are described in the text following that table If any...

Page 82: ...ic acoustic management supported 5 Reserved 4 1 Power Up in Standby feature set supported 3 1 Security feature set supported 2 1 SMART error log supported 1 1 SMART self test supported 0 1 SMART feature set supported 8 SATA feature 15 5 Reserved 4 1 Software setting preservation supported 3 Reserved 2 1 Interface power management supported 1 1 Non zero buffer offset in DMA Setup FIS supported 0 1 ...

Page 83: ...escription 01h DCO feature is frozen 02h Device is now Security Locked mode 03h Device s feature is already modified with DCO 04h User attempt to disable any feature enabled 05h Device is now SET MAX Locked or Frozen mode 06h Protected area is now established 07h DCO is not supported 08h Subcommand code is invalid FFh other reason Table 47 DCO error information definition ...

Page 84: ...tents of the LBA Low and Sector Count registers The LBA Low register is used to extend the Sector Count register to create a 16 bit sector count value The LBA Low register is the most significant eight bits and the Sector Count register is the least significant eight bits ABT will be set to 1 in the Error Register if the value in the Feature register is neither 03h nor 07h or the device is in Secu...

Page 85: ...mand for the firmware download the device will perform any device required verification and save the complete set of downloaded microcode If the device receives a command other than download microcode prior to the receipt of the last segment the new command is executed and all previously downloaded microcode is discarded If a software or hardware Reset is issued to the device before all of the mic...

Page 86: ...low Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 V V V V V V V 0 0 0 0 0 0 Table 49 Execute Device Diagnostic Command 90h The Execute Device Diagnostic command performs the internal diagnostic tests implemented by the device The results of the test are stored in the Error Register The normal Error Register bit definiti...

Page 87: ...evice Device Command 1 1 1 0 0 1 1 1 Status See Below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 V 0 0 V Table 50 Flush Cache Command E7h This command causes the device to complete writing data from its cache The device returns a status RDY 1 and DSC 1 50h after following sequence l Data in the wr...

Page 88: ...A Low Previous LBA Low HOB 1 Current HOB 0 LBA Mid Previous LBA Mid HOB 1 Current HOB 0 LBA High Previous LBA High HOB 1 Device Device Command 1 1 1 0 1 0 1 0 Status See Below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 V 0 0 V Table 51 Flush Cache EXT Command EAh This command causes the device to c...

Page 89: ...e initialized to zero with write operation At this time whether the sector of data is initialized correctly is not verified with read operation Any data previously stored on the track will be lost Output Parameters To The Device LBA Low In LBA mode this register specifies LBA address bits 0 7 to be formatted L 1 LBA High Mid The cylinder number of the track to be formatted L 0 In LBA mode this reg...

Page 90: ... next power on reset Both previous information are erased from the device by this command Note that the Format Unit command initializes from LBA 0 to Native MAX LBA Host MAX LBA set by Initialize Drive Parameter or Set MAX ADDRESS command is ignored So the protected area by Set MAX ADDRESS commands is also initialized The security erase prepare command should be completed immediately prior to the ...

Page 91: ... High Device Device Command 1 1 1 0 1 1 0 0 Status See Below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 0 V Table 54 Identify Device Command ECh The Identify Device command requests the device to transfer configuration information to the host The device will transfer a sector to the host contain...

Page 92: ...E response is complete 37C8h SET FEATURES subcommand is required to spin up and IDENTIFY DEVICE response is incomplete 03 Note 2 Number of heads in default translate mode 04 05 0 Reserved 06 003FH Number of sectors per track in default translate mode 07 09 0 Reserved 10 19 XXXX Serial number in ASCII 0 not specified 20 0003H Controller type 0003 dual port ed multiple sector buffer with look ahead ...

Page 93: ... Validity flag of the word 15 8 xxh FFS Sense Level 7 3 0 Reserved 2 1 1 Word 88 is Valid 1 1 1 Word 64 70 are Valid 0 1 1 Word 54 58 are Valid 54 xxxxH Number of current cylinders 55 xxxxH Number of current heads 56 xxxxH Number of current sectors per track 57 58 xxxxH Current capacity in sectors Word 57 specifies the low word of the capacity 59 0xxxH Current Multiple setting bit assignments 15 9...

Page 94: ...imum PIO Transfer Cycle Time Without Flow Control 15 0 78h Cycle time in nanoseconds 120ns 16 6MB s 68 0078H Minimum PIO Transfer Cycle Time With IORDY Flow Control 15 0 78h Cycle time in nanoseconds 120ns 16 6MB s 69 74 0000H Reserved 75 001FH Queue depth 15 5 0 Reserved 4 0 1Fh Maximum queued depth 1 76 170xH SATA capabilities 15 13 0 Reserved 12 1 1 Native Command Queuing priority information s...

Page 95: ...in DMA Setup FIS enabled 0 0 Reserved 80 01FCH Major version number ATA 2 3 and ATA ATAPI 4 5 6 7 8 81 0042H Minor version number ATA8 ACS revision 3f 82 746BH Command set supported 15 0 Reserved 14 1 1 NOP command supported 13 1 1 READ BUFFER command supported 12 1 1 WRITE BUFFER command supported 11 0 Reserved 10 1 1 Host Protected Area Feature Set supported 9 0 1 DEVICE RESET command supported ...

Page 96: ...rted 3 1 1 Advanced Power Managem ent Feature Set supported 2 0 1 CFA Feature Set supported 1 0 1 READ WRITE DMA QUEUED supported 0 1 Download Microcode Command Supported 84 6163H Command set feature supported extension 15 0 Always 14 1 Always 13 1 1 IDLE IMMEDIATE with UNLOAD FEATURE supported 12 9 0 Reserved 8 1 1 64 bit World wide name supported 7 0 1 WRITE DMA QUEUED FUA EXT command supported ...

Page 97: ...d set feature enabled 15 1 1 Words 120 119 are valid 14 0 Reserved 13 1 1 FLUSH CACHE EXT command supported 12 1 1 FLUSH CACHE command supported 11 x 1 Device Configuration Overlay supported 10 1 1 48 bit Address feature set supported 9 x 1 Automatic Acoustic Management enabled 8 x 1 SET MAX security extension enabled 7 0 Reserved 6 1 1 SET FEATURES subcommand required to spin up 5 x 1 Power Up In...

Page 98: ... DMA Transfer mode mode 6 supported 15 0 Reserved 14 x 1 UltraDMA mode 6 is selected 13 x 1 UltraDMA mode 5 is selected 12 x 1 UltraDMA mode 4 is selected 11 x 1 UltraDMA mode 3 is selected 10 x 1 UltraDMA mode 2 is selected 9 x 1 UltraDMA mode 1 is selected 8 x 1 UltraDMA mode 0 is selected 7 0 Reserved 6 1 1 UltraDMA mode 6 is supported 5 1 1 UltraDMA mode 5 is supported 4 1 1 UltraDMA mode 4 is...

Page 99: ...8 bit Address feature set 104 0000H Streaming Transfer Time PIO 105 106 0000H Reserved 107 7AB8H Inter seek delay time 1 5tt 2 5tl 108 111 XXXX World Wide Name 112 118 0000H Reserved 119 4014H Supported Setting 15 0 Always 14 1 Always 13 6 0 Reserved 5 0 1 Free fall Control feature set is supported 4 1 1 Download Microcode with mode 3 is supported 3 0 1 Read and Write DMA Ext GPL is supported 2 1 ...

Page 100: ...5 1 1 SCT Data Tables supported 4 1 1 SCT Features Control supported 3 1 1 SCT Error Recovery Control supported 2 1 1 SCT Write Same supported 1 0 1 SCT Long Sector Access supported 0 1 1 SCT Command Transport supported 207 216 xxxxH Reserved 217 1518H Media Rotation Rate 218 221 xxxxH Reserved 222 101FH Transport Major Revision Number 15 12 Transport Type 0 Parallel 1 Serial 2 15 Reserved 11 5 0 ...

Page 101: ...20 SATA OEM Specification 101 Note 2 See following table Table 64 Number of cylinders heads sectors by models for HTS5432XXL9SA00 HTS5432XXL9A300 on Page 102 Table 63 Identify device information Continued ...

Page 102: ...BA address for 48 bit Address feature set word 100 103 DF94BB0h 950F8B0h Model Number in ASCII Hitachi HTS543232L9A300 Hitachi HTS543225L9A300 Hitachi HTS543216L9A300 Number of cylinders 3FFFh 3FFFh 3FFFh Number of heads 10h 10h 10h Buffer size 3795h 3795h 3795h Total number of user addressable sectors word 60 61 2542EAB0h FFFFFFF h FFFFFFF h Maximum user LBA address for 48 bit Address feature set...

Page 103: ...at ely and set auto power down timeout parameter standby timer And then the timer starts counting down When the device s power save mode is already any idle mode the device keep that mode When the Idle mode is entered the device is spun up to operating speed If the device is already spinning the spin up sequence is not executed During Idle mode the device is spinning and ready to respond to host c...

Page 104: ...0 CRC UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 V 0 0 V Table 66 Idle Immediate Command E1h 95h The Idle Immediate command causes the device to enter performance Idle mode The device is spun up to operating speed If the device is already spinning the spin up sequence is not executed During Idle mode the device is spinning and ready to respond to host commands im...

Page 105: ...0 0 0 V Table 67 Initialize Device Parameters Command 91h The Initialize Device Parameters command enables the host to set the number of sectors per track and the number of heads minus 1 per cylinder Words 54 58 in Identify Device Information reflects these parameters The parameters remain in effect until the following events l Another Initialize Device Parameters command is received l The device ...

Page 106: ...gister 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 0 V Table 68 Read Buffer Command E4h The Read Buffer command transfers a sector of data from the sector buffer of device to the host The sector is transferred through the Data Register 16 bits at a time The sector transferred will be from the same part of the buffer written to...

Page 107: ...has terminated and status is available If an uncorrectable error occurs the read will be terminated at the failing sector Output Parameters To The Device Sector Count The number of continuous sectors to be transferred If zero is specified then 256 sectors will be transferred LBA Low The sector number of the first sector to be transferred L 0 In LBA mode this register specifies LBA address bits 0 7...

Page 108: ...er 16 bits at a time The host initializes a slave DMA channel prior to issuing the command The data transfers are qualified by DMARQ and are performed by the slave DMA channel The device issues only one interrupt per command to indicate that data transfer has terminated and status is available If an uncorrectable error occurs the read will be terminated at the failing sector Output Parameters To T...

Page 109: ...er of sectors to be transferred low order bits 7 0 Feature Previous The number of sectors to be transferred high orde r bits 15 8 T TAG value It shall be assigned to be different from all other queued commands The value shall not exceed the maximum queue depth specified by the Word 75 of the Identify Device information LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA...

Page 110: ...ounter Reset bit When Log address is 11h Phy Event Counter and this bit is set to 1 all Phy Event Counter values are reset to 0 after sending the current counter valules Sector Count Current The number of sectors to be read from the specified log low order bits 7 0 The log transferred by the drive shall start at the sector in the specified log at the specified offset regardless of the sector count...

Page 111: ...ess 01h 15 8 1 03h Number of sectors in the log at log address 02h 7 0 1 04h Number of sectors in the log at log address 02h 15 8 1 05h Number of sectors in the log at log address 80h 7 0 1 100h Number of sectors in the log at log address 80h 15 8 1 101h Number of sectors in the log at log address FFh 7 0 1 1FEh Number of sectors in the log at log address FFh 15 8 1 1FFh 512 Table 74 General purpo...

Page 112: ...lid values for the error log index are 0 to 4 14 17 2 3 Extended Error log data structure An error log data structure shall be presented for each of the last four errors reported by the device These error log data structure entries are viewed as a circular buffer The fifth error shall create an error log structure that replaces the first error log data structure The next error after that shall cre...

Page 113: ...contents of the register prior to the most recent write to the register Table 77 Command data structure Error data structure Data format of error data structure is shown below Description Bytes Offset Reserved 1 00h Error register 1 01h Sector count register 7 0 see Note 1 02h Sector count register 15 8 see Note 1 03h Sector number register 7 0 1 04h Sector number register 15 8 1 05h Cylinder Low ...

Page 114: ...ines the format of each of the sectors that comprise the Extended SMART self test log The Extended SMART self test log sector shall support 48 bit and 28 bit addressing All 28 bit entries contained in the SMART self test log defined in Self test log data structure shall also be included in the Extended SMART self test log with all 48 bit entries Description Bytes Offset Self test log data structur...

Page 115: ...0 1 0Ah Vendor specific 15 0Bh 26 Table 80 Extended Self test log descriptor entry 14 17 4 Command Error The following table defines the format of the Command Error data structure Byte 7 6 5 4 3 2 1 0 0 NQ Rsv Rsv TAG 1 Reserved 2 Status 3 Error 4 LBA Low 5 LBA Mid 6 LBA High 7 Device 8 LBA Low Previous 9 LBA Mid Previous 10 LBA High Previous 11 Reserved 12 Sector Count 13 Sector Count Previous 14...

Page 116: ... the drive returns the current counter values for the command and then resets all Phy event counter values 14 17 5 2 Counter Identifiers Each counter begins with a 16 bit identifier The following table defines the counter value for each identifier For all counter descriptions transmitted refers to items sent by the drive to the host and received refers to items received by the drive from the host ...

Page 117: ...0Ah Value 16 17 Counter 000Bh Identifier 18 19 Counter 000Bh Value 20 21 Counter 000Dh Identifier 22 23 Counter 000Dh Value 24 00h 25 00h 26 510 Reserved 00h 511 Data Structure Checksum Table 83 Phy Event Counter information The Data Structure Checksum Byte 511 contains the 2 s complement of the sum of the first 511 bytes in the data structure The sum of all 512 bytes of the data structure will be...

Page 118: ...is generated for each block as defined by the Set Multiple command instead of for each sector Output Parameters To The Device Sector Count The number of continuous sectors to be transferred If zero is specified then 256 sectors will be transferred LBA Low The sector number of the first sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 LBA High Mid The cylinder number...

Page 119: ... AMN BSY RDY DF DSC DRQ COR IDX ERR 0 V 0 V 0 V 0 0 0 V 0 V 0 0 V Table 85 Read Multiple Ext Command 29h Output Parameters To The Device Sector Count Current The number of sectors to be transferred low order bits 7 0 Sector Count Previous The number of sectors to be transferred high order bits 15 8 If 0000h in the Sector Count register is specified then 65 536 sectors will be transferred LBA Low C...

Page 120: ...ive Max Address command return a value of 268 435 455 Output Parameters To The Device L LBA mode Indicates the addressing mode L 0 specifies CHS mode and L 1 does LBA addressing mode D The device number bit Indicates that the device number bit of the Device Register should be specified D 0 selects the master device and D 1 selects the slave device Indicates that the bit is not used Input Parameter...

Page 121: ...mand 0 0 1 0 0 1 1 1 Status See Below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 0 V Table 87 Read Native Max Address Ext Command 29h This command returns the native max LBA of HDD which is not effected by Set Max Address Ext command Input Parameters From The Device LBA Low HOB 0 LBA 7 0 of the a...

Page 122: ...rminated at the failing sector Output Parameters To The Device Sector Count The number of continuous sectors to be transferred If zero is specified then 256 sectors will be transferred LBA Low The sectornumber of the first sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 LBA High Mid The cylinder number of the first sector to be transferred L 0 In LBA mode this regi...

Page 123: ...1 to 65 536 sectors of data from disk media then transfers the data from the device to the host The sectors are transferred through the Data Register 16 bits at a time If an uncorrectable error occurs the read will be terminated at the failing sector Output Parameters To The Device Sector Count Current The number of sectors to be transferred low order bits 7 0 Sector Count Previous The number of s...

Page 124: ...rs the read verify will be terminated at the failing sector Output Parameters To The Device Sector Count The number of continuous sectors to be verified If zero is specified then 256 sectors will be verified LBA Low The sector number of the first sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 LBA High Mid The cylinder number of the first sector to be transferred L...

Page 125: ...evice No data is transferred to the host The difference between the Read Sector s Ext command and the Read Verify Sector s Ext command is whether the data is transferred to the host or not If an uncorrectable error occurs the Read Verify Sector s Ext will be terminated at the failing sector Output Parameters To The Device Sector Count Current The number of sectors to be transferred low order bits ...

Page 126: ...Mid LBA Mid LBA High LBA High Device Device Command 0 0 0 1 Status See Below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V V 0 0 V 0 V 0 0 V Table 92 Recalibrate Command 1xh The Recalibrate command moves the read write heads from anywhere on the disk to cylinder 0 If the device cannot reach cylinder 0 T0N Trac...

Page 127: ...rom the host including information specified in the following table Then the device checks the transferred password If the User Password or Master Password matches the given password the device disables the security mode feature device lock function T his command does not change the Master Password which may be re activated later by setting User Password This command should be executed in device u...

Page 128: ...ow Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 V 0 0 V Table 95 Security Erase Prepare Command F3h The Security Erase Prepare Command must be issued immediately before the Security Erase Unit Command to enable device erasing and unlocking The Security E rase Prepare Command must be issued immediate...

Page 129: ... If the password does not match then the device rejects the command with an Aborted error Word Description 00 Control word bit 0 Identifier 1 Mater 0 User bit 1 Erase mode 1 Enhanced Erase 0 Normal Er ase bit 2 15 Reserved 01 16 Password 32 bytes 17 255 Reserved Table 97 Erase Unit Information Identifier Zero indicates that the device should check the supplied password against the user password st...

Page 130: ...e device only erases all user data The execution time of this command in Normal Erase mode is shown below HTS543232L9SA00 HTS5432 32L9A300 126 min HTS543225L9SA00 HTS5432 25L9A300 100min HTS543216L9SA00 HTS5432 16L9A300 66 min HTS543212L9SA00 HTS5432 12L9A300 50 min HTS543280L9SA00 HTS5432 80L9A300 36 min The execution time of this command in Enhanced Erase mode is shown below HTS543232L9SA00 HTS5...

Page 131: ...C UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 0 V Table 98 Security Freeze Lock Command F5h The Security Freeze Lock Command allows the device to enter frozen mode immediately After this command is completed the command which updates Security Mode Feature Device Lock Function is rejected Frozen mode is quit only by Power off The following commands are rejected w...

Page 132: ...cked immediately The device is locked after next COMRESET with Software Setting Preservation disabled or power on reset When the MASTER password is set bythis command the master password is registered internally but the device is NOT locked after next power on reset This command requests a transfer of a single sector of data from the host including the information specified in the following table ...

Page 133: ...ntifier and Security level bits interact as follows Identifier User Security level High The password supplied with the command w ill be saved as the new user password The security mode feature lock function will be enabled from the next power on The file may then be unlocked by either the user password or the previously set master password Identifier Master Security level High This combination wil...

Page 134: ...e is in high security mode then the password supplied will be compared with the stored master password If the file is in maximum security mode then the security unlock will be rejected If the Identifier bit is set to user then the file compares the supplied password with the stored user password If the password compare fails then the device returns an abort error to the host and decrements the unl...

Page 135: ...0 V Table 103 Seek Command 7xh The Seek command initiates a seek to the designated track and selects the designated head The device need not be formatted for a seek to execute properly Output Parameters To The Device LBA Low In LBA mode this register specifies LBA address bits 0 7 for seek L 1 LBA High Mid The cylinder number of the seek In LBA mode this register specifies LBA address bits 8 15 Mi...

Page 136: ... command is used to sense temperature in a device This command is executable without spinning up even if a device is started with No Spin Up option If this command is issued at the temperature out of range which is specified for operating condition the error might be returned with IDN bit 1 Output Parameters To The Device Feature The Feature register must be set to 01h All other value are rejected...

Page 137: ... device is set to the following features as default Write cache Enable ECC bytes 4 bytes Read look ahead Enable Reverting to power on defaults Disable Device initiated interface power state transition Disable Software setting preservation Enable Output Parameters To The Device Feature Destination code for this command 02H Enable write cache Note 2 03H Set transfer mode based on value in sector cou...

Page 138: ... the write cache function will be automatically disabled Although the device still accepts the Set Features command with Feature register 02h without error the write cache function will remain disabled For current write cache function status please refer to the Identify Device Information 129word by Identify Device command Power off must not be done in 5 seconds after write command completion when...

Page 139: ...iately prior to issuing Set Max Address command Otherwise this command is interpreted as a Set Max security extension command which is destinated by feature register If Set Max security mode is in the Locked or Frozen the Set Max A ddress command is aborted For more information see 12 10 2 Set Max security extension commands on Page 66 In CHS mode LBA High LBA Mid specify the max cylinder number T...

Page 140: ... 8 15 Mid 16 23 High which is to be set L 1 In CHS mode this register contains max cylinder number which is to be set L 0 H In LBA mode this register contains LBA bits 24 27 which is to be input L 1 In CHS mode this register is ignored L 0 L LBA mode Indicates the addressing mode L 0 specifies CHS mode and L 1 does LBA addressing mode Input Parameters From The Device LBA Low In LBA mode this regis...

Page 141: ...T bit in status register When the address requested is greater than 268 435 455 words 103 100 shall be modified to reflect the requested value but words 61 60 shall not modified When the address requested is equal to or less than 268 435 455 words 103 100 shall be modified to reflect the requested value and words 61 60 shall also be modified If this command is not supported the maximum value to be...

Page 142: ...5K320 SATA OEM Specification 142 LBA Low HOB 1 Set Max LBA 31 24 LBA Mid HOB 0 Set Max LBA 15 8 LBA Mid HOB 1 Set Max LBA 39 32 LBA High HOB 0 Set Max LBA 23 16 LBA High HOB 1 Set Max LBA 47 40 ...

Page 143: ... Command C6h The Set Multiple command enables the device to perform Read and Write Multiple commands and establishes the block size for these commands The block size is the number of sectors to be transferred for each interrupt The default block size after power up is 0 and Read Multiple and Write Multiple commands are disabled If an invalid block size is specified an Abort error will be returned ...

Page 144: ...tatus Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 V 0 0 V Table 109 Sleep Command E6h 99h This command is the only way to cause the device to enter Sleep Mode When this command is issued the device confirms the completion of the cached write commands Then the device is spun down and the interface becomes inactive The on...

Page 145: ...ice s Features Register when the S M A R T Function Set command is issued by the host 14 40 1 S M A R T Sub commands In order to select a subcommand the host must write the subcommand code to the device s Features Register before issuing the S M A R T Function Set command The subcommands and their respective codes are listed below Code Subcommand D0h S M A R T Read Attribute Values D1h S M A R T R...

Page 146: ...by the host into this register before issuing the S M A R T Enable Disable Attribute Autosave subcommand will not change the current Autosave status but the device will respond with the error code specified in Table 124 S M A R T Error Codes on P age 159 The S M A R T Disable Operations subcommand disables the autosave feature along with the device s S M A R T operations Upon the receipt of the su...

Page 147: ... The user may choose to do read scan only on specific areas of the media To do this user shall set the test spans desired in the Selective self test log and set the flags in the Feature flags field of the Selective self test log to indicate do not perform off line scan In this case the test spans defined shall be rea d scanned in their entirety The Selective self test log is updated as the self te...

Page 148: ...e receipt of a S M A R T EXECUTE OFF LINE IMMEDIATE command with 0Fh Abort off line test routine in the LBA Low register shall abort Selective self test regardless of where the device is in the execution of the command If a second self test is issued while a selective self test is in progress the selective self test is aborted and the newly requested self test is executed S M A R T Read Log Sector...

Page 149: ... involving attributes are advisory the device loads 4Fh into the LBA Mid register C2h into the LBA High register If the device detects a Threshold Exceeded Condition for prefailure attributes the device loads F4h into the LBA Mid register 2Ch into the LBA High register Advisory attributes never result in negative reliability condition S M A R T Enable Disable Automatic Off Line Subcommand DBh This...

Page 150: ...using the S M A R T Read Attribute Values subcommand All multi byte fields shown in these data structures follow the ATA ATAPI 6 specification for byte ordering namely that the least significant byte occupies the lowest numbered byte address location in the field Description Bytes Offset Format Value Data Structure Revision Number 2 00h binary 0010h 1st Device Attribute 12 02h 1 2 30th Device Attr...

Page 151: ...not be 0 6 05h binary Reserved 00h 1 0Bh binary Total Bytes 12 Table 113 Individual Attribute Data Structure Attribute ID Numbers Any non zero value in the Attribute ID Number indicates an active attribute The device supports following Attribute ID N umbers Those marked with indicate that corresponding Attribute Values can be either collected on line or off line ID Attribute Name 0 Indicates that ...

Page 152: ...or the device For Performance and Error Rate Attributes values greater than 100 are also possible up to a maximum value of 253 FDh 14 40 2 3 Off Line Data Collection Status The value of this byte defines the current status of the off line activities of the device Bit 7 indicates Automatic Off Line Data Collection Status Bit 7 Automatic Off Line Data Collection Status 0 Automatic Off Line Data Coll...

Page 153: ...ta collection activity upon receipt of a new command 3 Off line Read Scanning implemented bit 0 The device does not support Off line Read Scanning 1 The device supports Off line Read Scanning 4 Self test implemented bit 0 Self test routine is not implemented 1 Self test routine is implemented 5 Reserved 0 6 Selective self test implemented bit 0 Selective s elf test routine is not implemented 1 Sel...

Page 154: ...sequence of active Attribute Thresholds will appear in the same order as their corresponding Attribute Values Description Bytes Offset Format Value Data Structure Revision Number 2 00h binary 0010h 1st Attribute Threshold 12 02h 1 2 30th Attribute Threshold 12 15Eh 1 2 Reserved 18 16Ah 3 Vendor specific 131 17Ch 3 Data structure checksum 1 1FFh 2 512 1 See following definitions 2 Value varied by a...

Page 155: ...bute Threshold subcommand to override these preset values in the Threshold sectors 14 40 3 5 Data Structure Checksum The Data Structure Checksum is the 2 s compliment of the result of a simple 8 bit addition of the first 511 bytes in the data structure 14 40 4 S M A R T Log Directory Following table defines the 512 bytes that make up the S M A R T Log Directory The S M A R T Log Directory is on S ...

Page 156: ...e 118 S M A R T error log sector 14 40 5 1 S M A R T error log version This value is set to 01h 14 40 5 2 Error log pointer This points the most recent error log data structure Only values 1 through 5 are valid 14 40 5 3 Device error count This field contains the total number of errors The value will not roll over 14 40 5 4 Error log data structure Data format of each error log structure is shown ...

Page 157: ...a format of error data structure is shown below Description Bytes Offset Reserved 1 00h Error register 1 01h Sector count register 1 02h LBA Low register 1 03h LBA Mid register 1 04h LBA High register 1 05h Device register 1 06h Status register 1 07h Extended error data vendor specific 19 08h State 1 1Bh Life timestamp hours 2 1Ch 30 Table 121 Error data structure State field c ontains a value ind...

Page 158: ...rst failure 4 n 18h 07h Vendor specific 15 n 18h 0Bh Vendor specific 2 1FAh Self test log pointer 1 1FCh Reserved 2 1FDh Data structure checksum 1 1FFh 512 Note n is 0 through 20 Table 122 Self test log data structure The data structure contains the descriptor of Self test that the device has performed Each descriptor is 24 bytes long and the self test data structure is capable to contain up to 21...

Page 159: ...A under test 8 1ECh Read Current span under test 2 1F4h Read Feature flags 2 1F6 R W Vendor specific 4 1F8h Vendor specific Selective self test pending time 2 1FCh R W Reserved 1 1FEh Reserved Data structure checksum 1 1FFh R W 512 Table 123 Selective self test log data structure 14 40 8 Error Reporting The following table shows the values returned in the Status and Error Registers when specific e...

Page 160: ...is issued the device confirms the completion of the cached write commands Then the device is spun down but the interface remains active If the device is already spun down the spin down sequence is not executed During the Standby mode the device will respond to commands but there is a delay while waiting for the spindle to reach operating speed The timer starts counting down when the device returns...

Page 161: ... BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 V 0 0 V Table 126 Standby Immediate Command E0h 94h The Standby Immediate command causes the device to enter Standby mode immediately When this command is issued the device confirms the completion of the cached write commands Then the device is spun down but the interface remains active If the device is already spun down the spin down sequence ...

Page 162: ...ow Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AM N BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 0 V Table 127 Write Buffer Command E8h The Write Buffer command transfers a sector of data from the host to the sector buffer of the device The sectors of data are transferred through the Data Register 16 bits at a time The Read Buffer and Write Buff...

Page 163: ...t per command to indicate that data transfer has terminated and status is available If an uncorrectable error occurs the write will be terminated at the failing sector Output Parameters To The Device Sector Count The number of continuous sectors to be transferred If zero is specified then 256 sectors will be transferred LBA Low The sector number of the first sector to be transferred L 0 In LBA mod...

Page 164: ...r 16 bits at a time The host initializes a slave DMA channel prior to issuing the command Data transfers are qualified by DMARQ and are performed by the slave DMA channel The device issues only one interrupt per command to indicate that data transfer has terminated and status is available If an uncorrectable error occurs the write will be terminated at the failing sector Output Parameters To The D...

Page 165: ...s command is reported also when write caching is enabled The sectors of data are transferred through the Data Register 16 bits at a time The host initializes a slave DMA channel prior to issuing the command Data transfers are qualified by DMARQ and are performed by the slave DMA channel The device issues only one interrupt per command to indicate that data transfer has terminated and status is ava...

Page 166: ...ber of sectors to be transferred low order bit 7 0 Feature Previous The number of sectors to be transferred high order bit 15 8 T TAG value It shall be assigned to be different from all other queued commands The value shall not exceed the maximum queue depth specified by the Word 75 of the Identify Device information LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA M...

Page 167: ...The number of sectors to be written to the specified log low order bits 7 0 Sector Count Previous The number of sectors to be written to the specified log high orders bits 15 8 If the number of sectors is greater than the number indicated in the Log directory which is available in Log number zero the device shall return command aborted The log transferred to the device shall be stored by the devic...

Page 168: ...tead of for each sector The sectors are transferred through the Data Register 16 bits at a time Output Parameters To The Device Sector Count The number of continuous sectors to be transferred If zero is specified then 256 sectors will be transferred LBA Low The sector number of the first sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 LBA High Mid The cylinder numb...

Page 169: ...ata is written to the disk media Command execution is identical to the Write Sector s Ext command except that an interrupt is generated for each block as defined by the Set Multiple command instead of for each sector The sectors are transferred through the Data Register 16 bits at a time Output Parameters To The Device Sector Count Current The number of continuous sectors to be transferred low ord...

Page 170: ...the device then the data is written to the disk media This command provides the same function as the Write Multiple Ext command except that the transferred data shall be written to the media before the ending status for this command is reported also when write caching is enabled Output Parameters To The Device Sector Count Current The number of continuous sectors to be transferred low order bits 7...

Page 171: ...ing sector when the auto reassign function is disable Output Parameters To The Device Sector Count The number of continuous sectors to be transferred If zero is specified then 256 sectors will be transferred LBA Low The sector number of the first sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 LBA High Mid The cylinder number of the first sector to be transferred L...

Page 172: ...ore sectors from the host to the device then the data is written to the disk media The sectors are transferred through the Data Register 16 bits at a time If an uncorrectable error occurs the write will be terminated at the failing sector Output Parameters To The Device Sector Count Current The number of continuous sectors to be transferred low order bits 7 0 Sector Count Previous The number of co...

Page 173: ...ors In this case whenever a pseudo uncorrectable sector is accessed via a read command the device performs normal error recovery and then set the UNC and ERR bits to indicate she sector is bad When the feature field contains a value of Axh the Write Uncorrectable Ext command causes the device to flag the specified sector as flagged uncorrectable Flagging a logical sector as uncorrectable causes th...

Page 174: ...urrent LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Input Parameters From The Device LBA Low HOB 0 LBA 7 0 of the address of the first unrecoverable error LBA Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unre...

Page 175: ...e host 30 sec Data In Command Device Busy After Data Transfer In A PIO SETUP FIS is transferred to the host Status Register BSY 1 10 us Device Busy After a Register FIS to issue a command Sets proper values in the registers and sends a Register FIS Status Register BSY 1 400 ns Device Busy After Data Transfer Out Sends a Data FIS to the device Status Register BSY 1 5 us Data Out Command PIO SETUP F...

Page 176: ...n 176 Note 1 For SECURITY ERASE UNIT command the execution time is referred to 14 29 Security Erase Unit F4h on Page 129 Note 2 FORMAT UNIT command the execution time is referred to 14 8 Format Unit F7h Vendor Specific on Page 90 ...

Page 177: ...trademarks or registered trademarks of their respective companies References in this publication to Hitachi Global Storage Technologies products programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates Product information is provided for information pur poses only and does not c...

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