372
IRR1—Interrupt request register 1
H'F6
System control
Bit
Initial value
Read/Write
7
IRRTA
0
R/W
6
IRRS1
0
R/W
5
—
1
—
4
IRRI4
0
R/W
3
IRRI3
0
R/W
0
IRRI0
0
R/W
2
IRRI2
0
R/W
1
IRRI1
0
R/W
Timer A interrupt request flag
0
[Clearing condition]
When IRRTA = 1, it is cleared by writing 0
1
[Setting condition]
When the timer A counter overflows from H'FF to H'00
Note: Only a write of 0 for flag clearing is possible.
*
*
*
*
*
SCI1 interrupt request flag
0
[Clearing condition]
When IRRS1 = 1, it is cleared by writing 0
1
[Setting condition]
When an SCI1 transfer is completed
IRQ to IRQ interrupt request flag
0
[Clearing condition]
When IRRIn = 1, it is cleared by writing 0 to IRRIn.
1
[Setting condition]
When pin IRQ is set to interrupt input and the designated signal edge is
detected.
*
*
*
4
0
n
(n = 4 to 0)