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Compare Match Flag Set Timing: The compare match flags (CMFH or CMFL) are set to 1
when a compare match occurs between TCF and OCRF. A compare match signal is generated in
the final state in which the values match (when TCF changes from the matching count value to the
next value). When TCF and OCRF match, a compare match signal is not generated until the next
counter clock pulse.

Timer F Operation States: Table 9.7 summarizes the timer F operation states.

Table 9.7

Timer F Operation States

Operation Mode

Reset

Active

Sleep

Watch

Sub-
active

Sub-
sleep

Standby

TCF

Reset

Functions

Functions

Halted

Halted

Halted

Halted

OCRF

Reset

Functions

Retained

Retained

Retained

Retained

Retained

TCRF

Reset

Functions

Retained

Retained

Retained

Retained

Retained

TCSRF

Reset

Functions

Retained

Retained

Retained

Retained

Retained

9.3.5

Application Notes

The following conflicts can arise in timer F operation.

16-Bit Timer Mode: The output at pin TMOFH toggles when all 16 bits match and a compare
match signal is generated. If the compare match signal occurs at the same time as new data is
written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be
output at pin TMOFH. The TMOFL output in 16-bit mode is indeterminate, so this output should
not be used. Use the pin as a general input or output port.

If an OCRFL write occurs at the same time as a compare match signal, the compare match signal
is inhibited. If a compare match occurs between the written data and the counter value, however, a
compare match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFL clock, so if this clock is stopped no compare match signal will be
generated, even if a compare match occurs.

Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated;
bit CMFL is set when the setting conditions are met for the lower 8 bits.

The overflow flag (OVFH) is set when TCF overflows; bit OVFL is set if the setting conditions
are met when the lower 8 bits overflow. If a write to TCFL occurs at the same time as an overflow
signal, the overflow signal is not output.

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Summary of Contents for H8/3635

Page 1: ...H8 3637 Series H8 3637 H8 3636 H8 3635 Hardware Manual ADE 602 152 Rev 1 0 8 1 98 Hitachi Ltd MC Setsu ...

Page 2: ...the characteristics and performance of Hitachi s semiconductor products Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein 5 No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi Ltd 6 MEDICAL APPLICATIONS Hitachi s products are ...

Page 3: ...atible with the H8 300 CPU On chip peripheral functions of the H8 3637 Series include a high precision DTMF generator for tone dialing a 14 bit PWM five types of timers two serial communication interface channels and an A D converter This manual describes the hardware of the H8 3637 Series For details on the H8 3637 Series instruction set refer to the H8 300L Series Programming Manual ...

Page 4: ... 3 2 Memory Data Formats 19 2 4 Addressing Modes 20 2 4 1 Addressing Modes 20 2 4 2 Effective Address Calculation 22 2 5 Instruction Set 26 2 5 1 Data Transfer Instructions 28 2 5 2 Arithmetic Operations 30 2 5 3 Logic Operations 31 2 5 4 Shift Operations 31 2 5 5 Bit Manipulations 33 2 5 6 Branching Instructions 37 2 5 7 System Control Instructions 39 2 5 8 Block Data Transfer Instruction 40 2 6 ...

Page 5: ...se Time 75 3 4 Application Notes 76 3 4 1 Notes on Stack Area Use 76 3 4 2 Notes on Rewriting Port Mode Registers 76 Section 4 Clock Pulse Generators 79 4 1 Overview 79 4 1 1 Block Diagram 79 4 1 2 System Clock and Subclock 79 4 2 System Clock Generator 80 4 3 Subclock Generator 83 4 4 Prescalers 84 4 5 Note on Oscillators 84 Section 5 Power Down Modes 87 5 1 Overview 87 5 1 1 System Control Regis...

Page 6: ...0 5 7 3 Operating Frequency in Active medium speed Mode 100 5 8 Direct Transfer 101 5 8 1 Overview 101 5 8 2 Direct Transfer Time 102 Section 6 ROM 105 6 1 Overview 105 6 1 1 Block Diagram 105 6 2 PROM Mode 106 6 2 1 Selection of PROM Mode 106 6 2 2 Socket Adapter Pin Arrangement and Memory Map 106 6 3 Programming 109 6 3 1 Programming and Verification 110 6 3 2 Programming Precautions 114 6 4 Rel...

Page 7: ...3 8 6 1 Overview 143 8 6 2 Register Configuration and Description 143 8 6 3 Pin Functions 145 8 6 4 Pin States 145 8 7 Port 8 146 8 7 1 Overview 146 8 7 2 Register Configuration and Description 146 8 7 3 Pin Functions 148 8 7 4 Pin States 148 8 8 Port 9 149 8 8 1 Overview 149 8 8 2 Register Configuration and Description 149 8 8 3 Pin Functions 151 8 8 4 Pin States 151 8 9 Port A 152 8 9 1 Overview...

Page 8: ...scriptions 183 9 4 3 Noise Canceller Circuit 187 9 4 4 Timer Operation 188 9 4 5 Application Notes 192 9 4 6 Sample Timer G Application 196 9 5 Timer Y 196 9 5 1 Overview 196 9 5 2 Register Descriptions 198 9 5 3 Interface with the CPU 200 9 5 4 Operation 203 9 5 5 Timer Y Operating Modes 204 9 6 Watchdog Timer 204 9 6 1 Overview 204 9 6 2 Register Descriptions 206 9 6 3 Operation 208 9 6 4 Watchd...

Page 9: ...MF Control Register DTCR 275 11 2 2 DTMF Load Register DTLR 277 11 3 Operation 278 11 3 1 Output Waveform 278 11 3 2 Operation Flow 279 11 4 Typical Use 280 11 5 Application Notes 280 Section 12 A D Converter 281 12 1 Overview 281 12 1 1 Features 281 12 1 2 Block Diagram 282 12 1 3 Pin Configuration 283 12 1 4 Register Configuration 283 12 2 Register Descriptions 284 12 2 1 A D Result Register ADR...

Page 10: ...istics 300 14 2 3 AC Characteristics 305 14 2 4 A D Converter Characteristics 308 14 2 5 DTMF Characteristics 309 14 3 Operation Timing 310 14 4 Output Load Circuits 313 Appendix A CPU Instruction Set 315 A 1 Instructions 315 A 2 Operation Code Map 323 A 3 Number of Execution States 325 Appendix B On Chip Registers 332 B 1 I O Registers 1 332 B 2 I O Registers 2 336 Appendix C I O Port Block Diagr...

Page 11: ...viii Appendix D Port States in the Different Processing States 397 Appendix E Product Line Up 398 Appendix F Package Dimensions 399 ...

Page 12: ...tions include five types of timers two serial communication interface channels an A D converter and a 14 bit pulse width modulator PWM The H8 3637 Series includes three models the H8 3637 H8 3636 and H8 3635 with different amounts of on chip memory the H8 3637 has 60 kbytes of ROM and 2 kbytes of RAM the H8 3636 has 48 kbytes of ROM and 2 kbytes of RAM and the H8 3635 has 40 kbytes of ROM and 2 kb...

Page 13: ...asic arithmetic operations between registers MOV instruction for data transfer between memory and registers Instruction features Multiply 8 bits 8 bits Divide 16 bits 8 bits Bit accumulator Register indirect designation of bit position Interrupts 30 interrupt sources 13 external interrupt sources IRQ4 to IRQ0 WKP7 to WKP0 17 internal interrupt sources Clock pulse generators Two on chip clock pulse...

Page 14: ...als or event input from external pin Compare match function with toggle output Timer G 8 bit timer with built in input capture interval functions Count up timer with selection of four internal clock signals Input capture function with built in noise canceller circuit Timer Y 16 bit timer with built in interval auto reload functions Count up timer with selection of seven internal clocks or event in...

Page 15: ... ripple Can be used as a 14 bit D A converter by connecting a low pass filter externally Product lineup Product Code Mask ROM Version ZTAT Version Package ROM RAM Size HD6433637F HD6473637F 80 pin QFP FP 80B ROM 60 kbytes RAM 2 kbytes HD6433637X HD6473637X 80 pin TQFP TFP 80F HD6433637W HD6473637W 80 pin TQFP TFP 80C HD6433636F 80 pin QFP FP 80B ROM 48 kbytes RAM 2 kbytes HD6433636X 80 pin TQFP TF...

Page 16: ...G P21 SCK1 P22 SI1 P23 SO1 P24 SCK3 P25 RXD P26 TXD P27 IRQ0 P50 WKP0 P51 WKP1 P52 WKP2 P53 WKP3 P54 WKP4 P55 WKP5 P56 WKP6 P57 WKP7 P60 P61 P62 P63 P64 P65 P66 P67 AV CC AV SS PB 4 AN 4 PB 5 AN 5 PB 6 AN 6 PB 7 AN 7 SCI3 PWM WDT DTMF SCI1 PE3 PE2 VT ref TONED Data bus lower System clock pulse generator Subclock pulse generator Address bus Data bus upper ROM 40 k 48 k 60 kbytes RAM 2 kbytes Timer ...

Page 17: ...F P1 6 IRQ 2 TMCIY P1 5 IRQ 1 P1 4 PWM P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PE2 PE3 TONED VTref AVCC PB7 AN7 PB6 AN6 PB5 AN5 PB4 AN4 AVSS P61 P60 P57 WKP7 P56 WKP6 P55 WKP5 P54 WKP4 P53 WKP3 P52 WKP2 P51 WKP1 P50 WKP0 PA0 PA1 PA2 PA3 VCC VSS P10 TMOW P11 TMOFL P12 TMOFH P13 TMIG 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 ...

Page 18: ...28 27 26 25 P8 7 P8 6 P8 5 P8 4 P8 3 P8 2 P8 1 P8 0 P7 7 P7 6 P7 5 P7 4 P7 3 P7 2 P7 1 P7 0 P6 7 P6 6 P6 5 P6 4 P6 3 P6 2 P6 1 P6 0 P90 P91 P92 P93 P94 P95 P96 P97 PE2 PE3 TONED VTref AVCC PB7 AN7 PB6 AN6 PB5 AN5 P57 WKP7 P56 WKP6 P55 WKP5 P54 WKP4 P53 WKP3 P52 WKP2 P51 WKP1 P50 WKP0 PA0 PA1 PA2 PA3 VCC VSS P10 TMOW P11 TMOFL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 ...

Page 19: ...is the A D converter ground pin It should be connected to the system power supply 0 V VTref 74 76 Input DTMF generator reference level This is a power supply pin for the reference level for DTMF Clock pins OSC1 5 7 Input System clock These pins connect to a crystal or ceramic oscillator or can be OSC2 4 6 Output used to input an external clock See section 4 Clock Pulse Generators for a typical con...

Page 20: ... is an output pin for wave forms generated by the timer A output circuit TMIF 17 19 Input Timer F event counter input This is an event input pin for input to the timer F counter TMOFL 23 25 Output Timer FL output This is an output pin for waveforms generated by the timer FL output compare function TMOFH 22 24 Output Timer FH output This is an output pin for waveforms generated by the timer FH outp...

Page 21: ...o 11 I O Port 2 bits 6 to 0 This is a 7 bit I O port Input or output can be designated for each bit by means of port control register 2 PCR2 P57 to P50 38 to 31 40 to 33 I O Port 5 This is an 8 bit I O port Input or output can be designated for each bit by means of port control register 5 PCR5 P67 to P60 46 to 39 48 to 41 I O Port 6 This is an 8 bit I O port Input or output can be designated for e...

Page 22: ...n RXD 14 16 Input SCI3 receive data input This is the SCI3 data input pin TXD 15 17 Output SCI3 send data output This is the SCI3 data output pin SCK3 13 15 I O SCI3 clock I O This is the SCI3 clock I O pin A D converter AN7 to AN4 76 to 79 78 to 80 1 Input Analog input channels 4 to 7 These are analog data input channels to the A D converter ADTRG 9 11 Input A D converter trigger input This is th...

Page 23: ...divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post increment or pre decrement Absolute address Immediate Program counter relative Memory indirect 64 kbyte address space High speed operation All frequently used instructions are executed in two to four states High speed ar...

Page 24: ...e H8 300L CPU There are two groups of registers the general registers and control registers 7 0 7 0 15 0 PC R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP SP Stack Pointer PC Program Counter CCR Condition Code Register Carry flag Overflow flag Zero flag Negative flag Half carry flag Interrupt mask bit User bit User bit CCR I U H U N Z V C General registers Rn Control registers ...

Page 25: ...he stack pointer SP used implicitly by hardware in exception handling and subroutine calls When it functions as the stack pointer as indicated in figure 2 2 SP R7 points to the top of the stack Lower address side H 0000 Upper address side H FFFF Unused area Stack area SP R7 Figure 2 2 Stack Pointer 2 2 2 Control Registers The CPU control registers include a 16 bit program counter PC and an 8 bit c...

Page 26: ...row at bit 3 and is cleared to 0 otherwise The H flag is used implicitly by the DAA and DAS instructions When the ADD W SUB W or CMP W instruction is executed the H flag is set to 1 if there is a carry or borrow at bit 11 and is cleared to 0 otherwise Bit 4 User Bit U Can be used freely by the user Bit 3 Negative Flag N Indicates the most significant bit sign bit of the result of an instruction Bi...

Page 27: ...ied out immediately after a reset 2 3 Data Formats The H8 300L CPU can process 1 bit data 4 bit BCD data 8 bit byte data and 16 bit word data Bit manipulation instructions operate on 1 bit data specified as bit n in a byte operand n 0 1 2 7 All arithmetic and logic instructions except ADDS and SUBS can operate on byte data The MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits 8 bits and DIVXU 16 bits...

Page 28: ... 7 0 1 bit data RnL MSB LSB Don t care 7 0 Byte data RnH Byte data RnL Word data Rn 4 bit BCD data RnH 4 bit BCD data RnL Legend RnH RnL MSB LSB Upper byte of general register Lower byte of general register Most significant bit Least significant bit MSB LSB Don t care 7 0 MSB LSB 15 0 Upper digit Lower digit Don t care 7 0 3 4 Don t care Upper digit Lower digit 7 0 3 4 Figure 2 3 Register Data For...

Page 29: ...ormat 7 6 5 4 3 2 1 0 Address Data Type 7 0 Address n MSB LSB MSB LSB Upper 8 bits Lower 8 bits MSB LSB CCR CCR MSB LSB MSB LSB Address n Even address Odd address Even address Odd address Even address Odd address 1 bit data Byte data Word data Byte data CCR on stack Word data on stack CCR Condition code register Note Ignored on return Figure 2 4 Memory Data Formats When the stack is accessed using...

Page 30: ... Register Direct Rn The register field of the instruction specifies an 8 or 16 bit general register containing the operand Only the MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits 8 bits and DIVXU 16 bits 8 bits instructions have 16 bit operands 2 Register Indirect Rn The register field of the instruction specifies a 16 bit general register containing the address of the operand in memory 3 Register...

Page 31: ...operand in memory The absolute address may be 8 bits long aa 8 or 16 bits long aa 16 The MOV B and bit manipulation instructions can use 8 bit absolute addresses The MOV B MOV W JMP and JSR instructions can use 16 bit absolute addresses For an 8 bit absolute address the upper 8 bits are assumed to be 1 H FF The address range is H FF00 to H FFFF 65280 to 65535 6 Immediate xx 8 or xx 16 The instruct...

Page 32: ... causing word access to be performed at the address preceding the specified address See 2 3 2 Memory Data Formats for further information 2 4 2 Effective Address Calculation Table 2 2 shows how effective addresses are calculated in each of the addressing modes Arithmetic and logic instructions use register direct addressing 1 The ADD B ADDX SUBX CMP B AND OR and XOR instructions can also use immed...

Page 33: ...ts 16 bits of register indicated by rm 0 15 0 15 3 Register indirect with displacement d 16 Rn op rm 7 6 3 4 0 15 disp 0 15 disp 0 15 Contents 16 bits of register indicated by rm 4 op rm 7 6 3 4 0 15 Register indirect with post increment Rn op rm 7 6 3 4 0 15 Register indirect with pre decrement Rn Incremented or decremented by 1 if operand is byte size and by 2 if word size 0 15 1 or 2 0 15 0 15 ...

Page 34: ...dress Calculation Method Effective Address EA 5 Absolute address aa 8 aa 16 op 8 7 0 15 0 15 abs H FF 8 7 0 15 0 15 abs op 6 op 0 15 IMM xx 16 op 8 7 0 15 IMM Immediate xx 8 Operand is 1 or 2 byte immediate data 7 op disp 7 0 15 Program counter relative d 8 PC PC contents 0 15 0 15 8 Sign extension disp ...

Page 35: ...nd Instruction Format Effective Address Calculation Method Effective Address EA 8 Memory indirect aa 8 op 8 7 0 15 Memory contents 16 bits 0 15 abs H 00 8 7 0 15 abs Legend rm rn Register field op Operation field disp Displacement IMM Immediate data abs Absolute address ...

Page 36: ...R BLD BILD BST BIST 14 Branch Bcc 2 JMP BSR JSR RTS 5 System control RTE SLEEP LDC STC ANDC ORC XORC NOP 8 Block data transfer EEPMOV 1 Total 55 Notes 1 PUSH Rn is equivalent to MOV W Rn SP POP Rn is equivalent to MOV W SP Rn The machine language is also the same 2 Bcc is a conditional branch instruction in which cc represents a condition code The following sections give a concise summary of the i...

Page 37: ...e flag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Logical negation logical complement 3 3 bit length 8 8 bit length 16 16 bit length Contents of operand indicated by effective address ...

Page 38: ...ster The Rn Rn d 16 Rn aa 16 xx 16 Rn and Rn addressing modes are available for byte or word data The aa 8 addressing mode is available for byte data only The R7 and R7 modes require word operands Do not specify byte size for these two modes POP W SP Rn Pops a 16 bit general register from the stack Equivalent to MOV W SP Rn PUSH W Rn SP Pushes a 16 bit general register onto the stack Equivalent to...

Page 39: ...n or Rn Rm 15 0 8 7 op rn abs aa 8 Rn 15 0 8 7 op rn aa 16 Rn abs 15 0 8 7 op rn IMM xx 8 Rn 15 0 8 7 op rn xx 16 Rn IMM 15 0 8 7 op rn PUSH POP Legend op rm rn disp abs IMM Operation field Register field Displacement Absolute address Immediate data SP Rn or Rn SP 1 1 1 Figure 2 5 Data Transfer Instruction Codes ...

Page 40: ...l register ADDS SUBS W Rd 1 Rd Rd 2 Rd Adds or subtracts immediate data to or from data in a general register The immediate data must be 1 or 2 DAA DAS B Rd decimal adjust Rd Decimal adjusts adjusts to packed 4 bit BCD an addition or subtraction result in a general register by referring to the CCR MULXU B Rd Rs Rd Performs 8 bit 8 bit unsigned multiplication on data in two general registers provid...

Page 41: ... on a general register and another general register or immediate data NOT B Rd Rd Obtains the one s complement logical complement of general register contents Note Size Operand size B Byte 2 5 4 Shift Operations Table 2 7 describes the eight shift instructions Table 2 7 Shift Instructions Instruction Size Function SHAL SHAR B Rd shift Rd Performs an arithmetic shift operation on general register c...

Page 42: ... IMM Operation field Register field Immediate data 15 0 8 7 op rn ADDS SUBS INC DEC DAA DAS NEG NOT 15 0 8 7 op rn MULXU DIVXU rm 15 0 8 7 rn IMM ADD ADDX SUBX CMP XX 8 op 15 0 8 7 op rn AND OR XOR Rm rm 15 0 8 7 rn IMM AND OR XOR xx 8 op 15 0 8 7 rn SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR op Figure 2 6 Arithmetic Logic and Shift Instruction Codes ...

Page 43: ...f a general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND B C bit No of EAd C ANDs the C flag with a specified bit in a general register or memory and stores the result in the C flag BIAND B C bit No of EAd C ANDs t...

Page 44: ...of EAd C Copies a specified bit in a general register or memory to the C flag BILD B bit No of EAd C Copies the inverse of a specified bit in a general register or memory to the C flag The bit number is specified by 3 bit immediate data BST B C bit No of EAd Copies the C flag to a specified bit in a general register or memory BIST B C bit No of EAd Copies the inverse of the C flag to a specified b...

Page 45: ...8 7 op 0 Operand Bit No register indirect Rn register direct Rm rn 0 0 0 0 0 0 0 rm op 15 0 8 7 op Operand Bit No absolute aa 8 immediate xx 3 abs 0 0 0 0 IMM op op 15 0 8 7 op Operand Bit No absolute aa 8 register direct Rm abs 0 0 0 0 rm op 15 0 8 7 op IMM rn Operand Bit No register direct Rn immediate xx 3 BAND BOR BXOR BLD BST 15 0 8 7 op 0 Operand Bit No register indirect Rn immediate xx 3 rn...

Page 46: ...op IMM rn Operand Bit No register direct Rn immediate xx 3 BIAND BIOR BIXOR BILD BIST 15 0 8 7 op 0 Operand Bit No register indirect Rn immediate xx 3 rn 0 0 0 0 0 0 0 IMM op 15 0 8 7 op Operand Bit No absolute aa 8 immediate xx 3 abs 0 0 0 0 IMM op Figure 2 7 Bit Manipulation Instruction Codes cont ...

Page 47: ...BT Always true Always BRN BF Never false Never BHI High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address ...

Page 48: ...ement Absolute address 15 0 8 7 op cc disp Bcc 15 0 8 7 op rm 0 JMP Rm 0 0 0 15 0 8 7 op JMP aa 16 abs 15 0 8 7 op abs JMP aa 8 15 0 8 7 op disp BSR 15 0 8 7 op rm 0 JSR Rm 0 0 0 15 0 8 7 op JSR aa 16 abs 15 0 8 7 op abs JSR aa 8 15 0 8 7 op RTS Figure 2 8 Branching Instruction Codes ...

Page 49: ...wn Modes for details LDC B Rs CCR IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to a specified general register ANDC B CCR IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR IMM CCR Logically ORs the condition code register with immediate data XORC B CCR IMM CCR Logically exclus...

Page 50: ...ject code format Table 2 11 Block Data Transfer Instruction Instruction Size Function EEPMOV If R4L 0 then repeat R5 R6 R4L 1 R4L until R4L 0 else next Block transfer instruction Transfers the number of bytes specified by R4L from locations starting at the address specified by R5 to locations starting at the address specified by R6 On completion of the transfer the next instruction is executed Cer...

Page 51: ...41 Legend op Operation field 15 0 8 7 op op Figure 2 10 Block Data Transfer Instruction Code ...

Page 52: ...fers depending on whether access is to on chip memory or to on chip peripheral modules 2 6 1 Access to On Chip Memory RAM ROM Acess to on chip memory takes place in two states The data bus width is 16 bits allowing access in byte or word size Figure 2 11 shows the on chip memory access cycle T1 state Bus cycle T2 state Internal address bus Internal read signal Internal data bus read access Interna...

Page 53: ...ules Figure 2 12 shows operation timings for accessing on chip peripheral modules in 2 states T1 state Bus cycle T2 state ø or ø Internal address bus Internal read signal Internal data bus read access Internal write signal Read data Address Write data Internal data bus write access SUB Figure 2 12 On Chip Peripheral Module Access Cycle 2 State Access Three state access to on chip peripheral module...

Page 54: ...ule Access Cycle 3 State Access 2 7 CPU States 2 7 1 Overview There are four CPU states the reset state program execution state program halt state and exception handling state The program execution state includes active high speed or medium speed mode and subactive mode In the program halt state there are a sleep mode standby mode watch mode and sub sleep mode These states are shown in figure 2 14...

Page 55: ... executes successive program instructions at reduced speed synchronized by the system clock The CPU executes successive program instructions at reduced speed synchronized by the subclock A state in which some or all of the chip functions are stopped to conserve power A transient state in which the CPU changes the processing flow due to a reset or an interrupt exception handling source The CPU is i...

Page 56: ...ith the system clock in active mode high speed and medium speed and with the subclock in subactive mode See section 5 Power Down Modes for details on these modes 2 7 3 Program Halt State In the program halt state there are four modes sleep mode standby mode watch mode and subsleep mode See section 5 Power Down Modes for details on these modes 2 7 4 Exception Handling State The exception handling s...

Page 57: ...vectors 42 bytes On chip ROM On chip RAM Reserved Internal I O registers 112 bytes 40 kbytes H8 3635 H 0000 H 0029 H 002A H 9FFF H FFFF H BFFF H EDFF H F77F H F780 H FF7F H FF80 H FF8F H FF90 Reserved H8 3637 H8 3636 48 kbytes 60 kbytes 2 kbytes Figure 2 16 H8 3637 Series Memory Map ...

Page 58: ...r Internal data transfer to or from on chip modules other than the ROM and RAM areas makes use of an 8 bit data width If word access is attempted to these areas the following results will occur Word access from CPU to I O register area Upper byte Will be written to I O register Lower byte Transferred data will be lost Word access from I O register to CPU Upper byte Will be written to upper part of...

Page 59: ...chip RAM Reserved Internal I O registers 112 bytes 40 kbytes H 0000 H 0029 H 002A H 9FFF H FFFF H BFFF H EDFF H F77F H F780 H FF7F H FF80 H FF8F H FF90 Reserved 48 kbytes 60 kbytes 2 kbytes 2 H8 3635 H8 3637 H8 3636 Figure 2 17 Data Size and Number of States for Access to and from On Chip Peripheral Modules ...

Page 60: ...nd the timer counter Figure 2 18 shows an example in which two timer registers share the same address When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer since these two registers share the same address the following operations take place Order of Operation Operation 1 Read Timer counter data is read one byte 2 Modify The CPU modifies sets o...

Page 61: ... After executing BSET P67 P66 P65 P64 P63 P62 P61 P60 Input output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR6 0 0 1 1 1 1 1 1 PDR6 0 1 0 0 0 0 0 1 D Explanation of how BSET operates When the BSET instruction is executed first the CPU reads port 6 Since P67 and P66 are input pins the CPU read...

Page 62: ...t Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR6 0 0 1 1 1 1 1 1 PDR6 1 0 0 0 0 0 0 0 RAM0 1 0 0 0 0 0 0 0 B BSET instruction executed BSET 0 RAM0 The BSET instruction is executed designating the PDR6 work area RAM0 C After executing BSET MOV B RAM0 R0L MOV B R0L PDR6 The work area RAM0 value is written to PDR6 P67 P66 P65 P64 P63 P62 P61 P60 Input ...

Page 63: ... 0 0 1 1 1 1 1 1 PDR6 1 0 0 0 0 0 0 0 B BCLR instruction executed BCLR 0 PCR6 The BCLR instruction is executed designating PCR6 C After executing BCLR P67 P66 P65 P64 P63 P62 P61 P60 Input output Output Output Output Output Output Output Output Input Pin state Low level High level Low level Low level Low level Low level Low level High level PCR6 1 1 1 1 1 1 1 0 PDR6 1 0 0 0 0 0 0 0 D Explanation o...

Page 64: ...t Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR6 0 0 1 1 1 1 1 1 PDR6 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 1 B BCLR instruction executed BCLR 0 RAM0 The BCLR instruction is executed designating the PCR6 work area RAM0 C After executing BCLR MOV B RAM0 R0L MOV B R0L PCR6 The work area RAM0 value is written to PCR6 P67 P66 P65 P64 P63 P62 P61 P60 Input ...

Page 65: ...t data register 9 PDR9 H FFDC Port data register A PDRA H FFDD Port data register E PDRE H FFD3 Note The port data register addresses are also assigned directly to input pins Table 2 13 Registers with Write Only Bits Register Name Abbreviation Address Port control register 1 PCR1 H FFE4 Port control register 2 PCR2 H FFE5 Port control register 5 PCR5 H FFE8 Port control register 6 PCR6 H FFE9 Port...

Page 66: ...ytes specified by R4L from the address specified by R5 to the address specified by R6 R6 R6 R4L R5 R5 R4L When setting R4L and R6 make sure that the final destination address R6 R4L does not exceed H FFFF The value in R6 must not change from H FFFF to H 0000 during execution of the instruction H FFFF Not allowed R6 R6 R4L R5 R5 R4L ...

Page 67: ... are initialized 3 2 2 Reset Sequence As soon as the RES pin goes low all processing is stopped and the H8 3637 Series enters the reset state To make sure the chip is reset properly observe the following precautions At power on Hold the RES pin low until the clock pulse generator output stabilizes When an external clock or ceramic oscillator is used also at power on the RES pin must be held low fo...

Page 68: ...tch 1 Reset exception handling vector address H 0000 2 Program start address 3 First instruction of program 2 3 2 Reset cleared 1 Figure 3 1 Reset Sequence 3 2 3 Interrupt Immediately after Reset After a reset if an interrupt were to be accepted before the stack pointer SP R7 was initialized PC and CCR would not be pushed onto the stack correctly resulting in program runaway To prevent this immedi...

Page 69: ...ties and their vector addresses When more than one interrupt is requested the interrupt with the highest priority is processed The interrupts have the following features Internal and external interrupts can be masked by the I bit of CCR When this bit is set to 1 interrupt request flags are set but interrupts are not accepted IRQ0 to IRQ4 can each be set independently to either rising edge sensing ...

Page 70: ...verflow 11 H 0016 to H 0017 Timer Y Timer Y overflow 12 H 0018 to H 0019 Timer FL Timer FL compare match Timer FL overflow 14 H 001C to H 001D Timer FH Timer FH compare match Timer FH overflow 15 H 001E to H 001F Timer G Timer G input capture Timer G overflow 16 H 0020 to H 0021 SCI3 SCI3 receive data full SCI3 transmit data empty SCI3 transmit end SCI3 overrun error SCI3 framing error SCI3 parity...

Page 71: ...iting of 0 to clear a flag Interrupt Edge Select Register IEGR Bit 7 6 5 4 3 2 1 0 IEG4 IEG3 IEG2 IEG1 IEG0 Initial value 0 1 1 0 0 0 0 0 Read Write R W R W R W R W R W IEGR is an 8 bit read write register used to designate whether pins IRQ0 to IRQ4 are set to rising edge sensing or falling edge sensing Bit 7 Reserved Bit Bit 7 is reserved it is always read as 0 and should be used cleared to 0 Bit...

Page 72: ...ion 0 Falling edge of IRQ2 TMCIY pin input is detected initial value 1 Rising edge of IRQ2 TMCIY pin input is detected Bit 1 IRQ1 Edge Select IEG1 Bit 1 selects the input sensing of pin IRQ1 Bit 1 IEG1 Description 0 Falling edge of IRQ1 pin input is detected initial value 1 Rising edge of IRQ1 pin input is detected Bit 0 IRQ0 Edge Select IEG0 Bit 0 selects the input sensing of pin IRQ0 Bit 0 IEG0 ...

Page 73: ...rrupt Enable IENS1 Bit 6 enables or disables SCI1 transfer complete interrupt requests Bit 6 IENS1 Description 0 Disables SCI1 interrupts initial value 1 Enables SCI1 interrupts Bit 5 Wakeup Interrupt Enable IENWP Bit 5 enables or disables WKP7 to WKP0 interrupt requests Bit 5 IENWP Description 0 Disables interrupt requests from WKP7 to WKP0 initial value 1 Enables interrupt requests from WKP7 to ...

Page 74: ...NAD Bit 6 enables or disables A D converter end interrupt requests Bit 6 IENAD Description 0 Disables A D converter interrupt requests initial value 1 Enables A D converter interrupt requests Bit 5 Reserved Bit Bit 5 is reserved it is always read as 0 and should be used cleared to 0 Bit 4 Timer G Interrupt Enable IENTG Bit 4 enables or disables timer G input capture and overflow interrupt requests...

Page 75: ...rial Control Register 3 SCR3 in section 10 3 2 Interrupt Request Register 1 IRR1 Bit 7 6 5 4 3 2 1 0 IRRTA IRRS1 IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value 0 0 1 0 0 0 0 0 Read Write R W R W R W R W R W R W R W Note Only a write of 0 for flag clearing is possible IRR1 is an 8 bit read write register in which the corresponding bit is set to 1 when a timer A SCI1 or IRQ4 to IRQ0 interrupt is reques...

Page 76: ...upt input and the designated signal edge is detected n 4 to 0 Interrupt Request Register 2 IRR2 Bit 7 6 5 4 3 2 1 0 IRRDT IRRAD IRRTG IRRTFH IRRTFL IRRTY IRRTYC Initial value 0 0 0 0 0 0 0 1 Read Write R W R W R W R W R W R W Note Only a write of 0 for flag clearing is possible IRR2 is an 8 bit register containing direct transfer A D converter timer G timer FH timer FL and timer Y interrupt flags ...

Page 77: ...s reserved it is always read as 0 and should be used cleared to 0 Bit 4 Timer G Interrupt Request Flag IRRTG Bit 4 IRRTG Description 0 Clearing conditions initial value When IRRTG 1 it is cleared by writing 0 1 Setting conditions When pin TMIG is set to TMIG input and the designated signal edge is detected or when TCG overflows from H FF to H 00 while TMG OVIE is set to 1 Bit 3 Timer FH Interrupt ...

Page 78: ...ar Flag IRRTYC Bit 0 is a special bit for clearing the IRRTY interrupt request flag Writing 0 to this bit clears bit 1 IRRTY to 0 Note that writing 0 to this bit does not give the bit itself a value of 0 Bit 0 is always read as 1 and only a write of 0 to this bit is valid Wakeup Interrupt Request Register IWPR Bit 7 6 5 4 3 2 1 0 IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value 0 0 0 ...

Page 79: ...t exception handling request is received for interrupts WKP0 to WKP7 the CCR I bit is set to 1 The vector number for interrupts WKP0 to WKP7 is 9 Since all eight interrupts are assigned the same vector number the interrupt source must be determined by the exception handling routine Interrupts IRQ0 to IRQ4 Interrupts IRQ0 to IRQ4 are requested by inputs into pins IRQ0 to IRQ4 These interrupts are d...

Page 80: ...ity of interrupts from on chip peripheral modules 3 3 5 Interrupt Operations Interrupts are controlled by an interrupt controller Figure 3 2 shows a block diagram of the interrupt controller Figure 3 3 shows the flow up to interrupt acceptance Interrupt controller Priority decision logic Interrupt request CCR CPU I External or internal interrupts External interrupts or internal interrupt enable si...

Page 81: ...lue pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling 6 The I bit of CCR is set to 1 masking all further interrupts 7 The vector address corresponding to the accepted interrupt is generated and the interrupt handling routine located at the address indicated by the contents of the vector address is executed Notes 1 When disabling interr...

Page 82: ... No Yes Yes No Legend PC CCR I Program counter Condition code register I bit of CCR IEN0 1 No Yes IENDT 1 No Yes IRRDT 1 No Yes Branch to interrupt handling routine IRRI0 1 No Yes IEN1 1 No Yes IRRI1 1 No Yes IEN2 1 No Yes IRRI2 1 Figure 3 3 Flow up to Interrupt Acceptance ...

Page 83: ...code register Stack pointer Ignored on return from interrupt Notes CCR CCR PCH PCL 1 2 PC shows the address of the first instruction to be executed upon return from the interrupt handling routine Register contents must always be saved and restored by word access starting from an even numbered address Figure 3 4 Stack State after Completion of Interrupt Exception Handling Figure 3 5 shows a typical...

Page 84: ...is saved as PC contents becoming return address 2 4 Instruction code not executed 3 Instruction prefetch address Instruction is not executed 5 SP 2 6 SP 4 7 CCR 8 Vector address 9 Starting address of interrupt handling routine contents of vector 10 First instruction of interrupt handling routine 3 9 8 6 5 4 1 7 10 Stack access Internal processing Instruction prefetch Interrupt level decision and w...

Page 85: ...t until the first instruction of the interrupt handler is executed Table 3 4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction 1 to 13 15 to 27 Saving of PC and CCR to stack 4 Vector fetch 2 Instruction fetch 4 Internal processing 4 Note Not including EEPMOV instruction ...

Page 86: ... FEFF Stack accessed beyond SP BSR instruction Contents of PC are lost H Legend PCH PCL R1L SP Upper byte of program counter Lower byte of program counter General register R1L Stack pointer Figure 3 6 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when RTE is executed this also takes place in word size Both the upper...

Page 87: ...GR bit IEG3 1 IRRI2 When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR bit IEG2 0 When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR bit IEG2 1 IRRI1 When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit IEG1 0 When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit IEG1 1 IRRI0 When PMR2 bit IRQ0 is changed fr...

Page 88: ...uction the flag will not be cleared An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3 5 do not occur CCR I bit 1 Set port mode register bit Execute NOP instruction Interrupts masked Another possibility is to disable the relevant interrupt in interrupt enable register 1 Aft...

Page 89: ...rescaler W 5 bits OSC OSC 1 2 X X 1 2 øOSC f OSC øW f W ø 2 OSC ø 2 W ø 8 W øSUB ø 2 to ø 8192 ø 2 W ø 4 W ø 8 to ø 128 W W ø ø 16 OSC ø 4 W øW øOSC Figure 4 1 Block Diagram of Clock Pulse Generators 4 1 2 System Clock and Subclock The basic clock signals that drive the CPU and on chip peripheral modules are ø and øSUB Four of the clock signals have names ø is the system clock øSUB is the subclock...

Page 90: ...Connection to Crystal Oscillator Figure 4 3 shows the equivalent circuit of a crystal oscillator An oscillator having the characteristics given in table 4 1 should be used CS C0 RS OSC1 OSC2 LS Figure 4 3 Equivalent Circuit of Crystal Oscillator Table 4 1 Crystal Oscillator Parameters Frequency 2 MHz 4 MHz 8 MHz 10 MHz RS max 500 Ω 100 Ω 50 Ω 30 Ω C0 max 7 pF 7 pF 7 pF 7 pF ...

Page 91: ...ing clock pulses by connecting a crystal or ceramic oscillator pay careful attention to the following points Avoid running signal lines close to the oscillator circuit since the oscillator may be adversely affected by induction currents See figure 4 5 The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2 OSC OSC C1 C2 Signal ...

Page 92: ...nnect an external clock signal to pin OSC1 and leave pin OSC2 open Figure 4 6 shows a typical connection 1 2 OSC OSC External clock input Open Figure 4 6 External Clock Input Example Frequency Oscillator Clock øOSC Duty cycle 45 to 55 ...

Page 93: ...ure 4 7 Typical Connection to 32 768 kHz Crystal Oscillator Figure 4 8 shows the equivalent circuit of the 32 768 kHz crystal oscillator CS C0 L RS X1 X2 C 1 5 pF typ R 14 k typ f 32 768 kHz Crystal oscillator MX38T Nihon Denpa Kogyo 0 S W Ω S Figure 4 8 Equivalent Circuit of 32 768 kHz Crystal Oscillator Pin Connection when Not Using Subclock When the subclock is not used connect pin X1 to VCC an...

Page 94: ...speed mode the clock input to prescaler S is øOSC 16 Prescaler W PSW Prescaler W is a 5 bit counter using a 32 768 kHz signal divided by 4 øW 4 as its input clock Prescaler W is initialized to H 00 by a reset and starts counting on exit from the reset state Even in standby mode watch mode subactive mode or subsleep mode prescaler W continues functioning so long as clock signals are supplied to pin...

Page 95: ...85 X X 1 2 VSS AVSS OSC2 OSC TEST VSS 1 Figure 4 10 Example of Crystal and Ceramic Oscillator Layout ...

Page 96: ...bactive mode The CPU runs on the subclock executing program instructions at reduced speed Sleep mode The CPU halts On chip peripheral modules continue to operate on the system clock Subsleep mode The CPU halts Timer A and timer G continue to operate on the subclock Watch mode The CPU halts The time base function of Timer A continues to operate on the subclock Standby mode The CPU and all on chip p...

Page 97: ... TMA3 1 LSON 0 MSON 1 LSON 0 MSON 0 SSBY 0 LSON 1 TMA3 1 SSBY 0 LSON 0 SSBY 1 TMA3 0 LSON 0 SSBY 1 TMA3 1 SLEEP instruction D TO N 1 D TO N 1 D TO N 1 SLEEP instruction A transition between different modes cannot be made to occur simply because an interrupt request is generated Make sure that the interrupt is accepted and interrupt handling is performed Transition caused by exception handling Subs...

Page 98: ...1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Peripheral Timer A Functional Functional Functional Functional 3 Functional 3 Functional 3 Retained module Timer F Retained Retained Retained functions Timer G Functional Retained 2 Functional Retained 2 Timer Y Functional Functional Functional Retained Retained Retained Retained Watchdog timer SCI1 Functional Functional Functional Retained Retained Retained Retaine...

Page 99: ...ignates transition to standby mode or watch mode Bit 7 SSBY Description 0 When a SLEEP instruction is executed in active mode a transition is made to sleep mode When a SLEEP instruction is executed in subactive mode a transition is made to subsleep mode initial value 1 When a SLEEP instruction is executed in active mode a transition is made to standby mode or watch mode When a SLEEP instruction is...

Page 100: ...n of other control bits and interrupt input Bit 3 LSON Description 0 The CPU operates on the system clock ø initial value 1 The CPU operates on the subclock øSUB Bits 2 to 0 Reserved Bits These bits are reserved they are always read as 1 and cannot be modified System Control Register 2 SYSCR2 Bit 7 6 5 4 3 2 1 0 NESEL DTON MSON SA1 SA0 Initial value 1 1 1 0 0 0 0 0 Read Write R W R W R W R W R W S...

Page 101: ... to standby mode watch mode or sleep mode initial value When a SLEEP instruction is executed in subactive mode a transition is made to watch mode or subsleep mode 1 When a SLEEP instruction is executed in active high speed mode a direct transition is made to active medium speed mode if SSBY 0 MSON 1 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is executed in...

Page 102: ...s are operational The CPU register contents are retained 5 2 2 Clearing Sleep Mode Sleep mode is cleared by an interrupt timer A timer F timer G timer Y IRQ0 to IRQ4 WKP0 to WKP7 SCI1 SCI3 A D converter or by reset input Clearing by Interrupt When an interrupt is requested sleep mode is cleared and interrupt exception handling starts Operation resumes in active high speed mode if MSON 0 in SYSCR2 ...

Page 103: ...aring by Interrupt When an interrupt is requested the system clock pulse generator starts After the time set in bits STS2 to STS0 in SYSCR1 has elapsed a stable system clock signal is supplied to the entire chip standby mode is cleared and interrupt exception handling starts Operation resumes in active high speed mode if MSON 0 in SYSCR2 or active medium speed mode if MSON 1 Standby mode is not cl...

Page 104: ...0 ms Table 5 4 Clock Frequency and Settling Time times are in ms STS2 STS1 STS0 Waiting Time 5 MHz 4 MHz 2 MHz 1 MHz 0 5 MHz 0 0 0 8 192 states 1 6 2 0 4 1 8 2 16 4 0 0 1 16 384 states 3 2 4 1 8 2 16 4 32 8 0 1 0 32 768 states 6 6 8 2 16 4 32 8 65 5 0 1 1 65 536 states 13 1 16 4 32 8 65 5 131 1 1 131 072 states 26 2 32 8 65 5 131 1 262 1 Note Don t care When an External Clock is Used Any values ma...

Page 105: ...ared to 0 and bit TMA3 in TMA is cleared to 0 At the same time pins go to the high impedance state except pins with MOS pull up turned on The timing in this case is shown in figure 5 2 SLEEP instruction fetch Internal data bus Next instruction fetch Port output Pins High impedance Active high speed mode or active medium speed mode Standby mode SLEEP instruction execution Internal processing ø Figu...

Page 106: ...ared by a timer A IRQ0 or WKP0 to WKP7 interrupt request the mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2 If both LSON and MSON are cleared to 0 transition is to active high speed mode if LSON 0 and MSON 1 transition is to active medium speed mode if LSON 1 transition is to subactive mode When the transition is to active mode after the time set in...

Page 107: ...les and the on chip RAM contents are retained I O ports keep the same states as before the transition Note The contents of SCI3 DTMF generator registers are reset 5 5 2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt timer A timer G IRQ0 to IRQ4 WKP0 to WKP7 or by a low input at the RES pin Clearing by Interrupt When an interrupt is requested subsleep mode is cleared and interrupt ...

Page 108: ...ng Subactive Mode Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin Clearing by SLEEP Instruction If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 subactive mode is cleared and watch mode is entered If a SLEEP instruction is executed while SSBY 0 and LSON 1 in SYSCR1 and TMA3 1 in TMA subsleep mode is entere...

Page 109: ... mode takes place if a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 the LSON bit in SYSCR1 is cleared to 0 and bit TMA3 in TMA is cleared to 0 The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 when a SLEEP instruction is executed Sleep mode is entered if both SSBY and LSON are cleared to 0 when a SLEEP instruction is execu...

Page 110: ... SYSCR1 are cleared to 0 the MSON bit in SYSCR2 is cleared to 0 and the DTON bit in SYSCR2 is set to 1 a transition is made to active high speed mode via sleep mode Direct Transfer from Active High Speed Mode to Subactive Mode When a SLEEP instruction is executed in active high speed mode while the SSBY and LSON bits in SYSCR1 are set to 1 the DTON bit in SYSCR2 is set to 1 and bit TMA3 in TMA is ...

Page 111: ...terrupt exception handling execution states tcyc after transition 1 Example H8 3637 Series direct transfer time 2 1 2tosc 14 16tosc 230tosc Legend tosc OSC clock cycle time tcyc System clock ø cycle time Time for Direct Transfer from Active Medium Speed Mode to Active High Speed Mode When a SLEEP instruction is executed in active medium speed mode while the SSBY bit in SYSCR1 is cleared to 0 the L...

Page 112: ...k cycle time tw Watch clock cycle time tcyc System clock ø cycle time tsubcyc Subclock øSUB cycle time Time for Direct Transfer from Subactive Mode to Active Medium Speed Mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1 the LSON bit in SYSCR1 is cleared to 0 the MSON bit in SYSCR2 is set to 1 the DTON bit in SYSCR2 is set to 1 and bit TMA3 in TMA...

Page 113: ...a bus allowing high speed 2 state access for both byte data and word data 6 1 1 Block Diagram Figure 6 1 shows a block diagram of the on chip ROM H 9FFE H 9FFF Internal data bus upper 8 bits Internal data bus lower 8 bits Even numbered address Odd numbered address H 9FFE H 0002 H 0000 H 0000 H 0002 H 0001 H 0003 On chip ROM H BFFE H BFFF H EDFE H EDFF 40 k H8 3635 48 k H8 3636 60 k H8 3637 H BFFE ...

Page 114: ...ge programming is not supported Table 6 1 shows how to set PROM mode Table 6 1 Setting PROM Mode Pin Name Setting TEST High level PB7 AN7 Low level PB6 AN6 PB5 AN5 High level 6 2 2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer can be used to program the PROM A socket adapter is required for conversion to 32 pins Figure 6 2 shows the pin to pin wiring of the socket adapte...

Page 115: ... 40 41 42 43 44 45 46 62 61 60 59 58 57 56 55 47 16 49 50 51 52 53 20 19 54 48 21 7 26 75 6 1 78 23 22 18 3 25 80 76 77 10 41 42 43 44 45 46 47 48 64 63 62 61 60 59 58 57 49 18 51 52 53 54 55 22 21 56 50 23 9 28 77 8 3 80 25 24 20 5 27 2 78 79 Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 CE OE PGM VCC VSS Note Pins not indicated in the fi...

Page 116: ...t if this area is read in PROM mode When programming with a PROM programmer be sure to specify addresses from H 0000 to H EDFF If H EE00 and higher addresses are programmed by mistake it may become impossible to program or verify the PROM When programming specify H FF for this address area H EE00 to H 1FFFF Figure 6 3 Memory Map in PROM Mode ...

Page 117: ...sabled L H H H L L H H H Legend L Low level H High level VPP VPP level VCC VCC level The programming and verifying specifications in PROM mode are the same as the specifications of the standard HN27C101 EPROM Page programming is not supported however The PROM programmer must not be set to page mode PROM programmers that support only page programming cannot be used When selecting a PROM programmer ...

Page 118: ...a in unused address areas is H FF Figure 6 4 shows the basic high speed high reliability programming flow chart Start Set program verify mode V 6 0 V 0 25 V V 12 5 V 0 3 V CC PP Address 0 n 0 n 1 n Program with t 0 2 ms 5 PW Verification OK Overprogram with t 0 2n ms OPW Last address Set read mode V 5 0 V 0 25 V V V CC PP CC All addresses read End Fail n 25 Address 1 address No Yes No Yes Yes No N...

Page 119: ...it Test Condition Input high level voltage EO7 to EO0 EA16 to EA0 OE CE PGM VIH 2 4 VCC 0 3 V Input low level voltage EO7 to EO0 EA16 to EA0 OE CE PGM VIL 0 3 0 8 V Output high level voltage EO7 to EO0 VOH 2 4 V IOH 200 µA Output low level voltage EO7 to EO0 VOL 0 45 V IOL 0 8 mA Input leakage current EO7 to EO0 EA16 to EA0 OE CE PGM ILI 2 µA Vin 5 25 V 0 5 V VCC current ICC 40 mA VPP current IPP ...

Page 120: ...PS 2 µs Programming pulse width tPW 0 19 0 20 0 21 ms PGM pulse width for over programming tOPW 3 0 19 5 25 ms VCC setup time tVCS 2 µs CE setup time tCES 2 µs Data output delay time tOE 0 200 ns Notes 1 Input pulse level 0 45 V to 2 4 V Input rise time fall time 20 ns Timing reference levels Input 0 8 V 2 0 V Output 0 8 V 2 0 V 2 tDF is defined at the point at which the output is floating and the...

Page 121: ...VCC CE PGM OE VPP VCC VCC VCC Program Verify Input data Output data tAS tDS tVPS tVCS tCES tPW tOPW tDH tOES tOE tDF tAH Note tOPW is defined by the value given in the high speed high reliability programming flow chart in figure 6 4 1 Figure 6 5 PROM Program Verify Timing ...

Page 122: ...If they are not the chip may be destroyed by excessive current flow Before programming be sure that the chip is properly mounted in the PROM programmer Avoid touching the socket adapter or chip while programming since this may cause contact faults and write errors Select the programming mode carefully The chip cannot be programmed in page programming mode When programming with a PROM programmer be...

Page 123: ...this screening procedure Install Write program and verify contents Bake at high temperature with power off 125 C to 150 C 24 hrs to 48 hrs Read and check program Figure 6 6 Recommended Screening Procedure If write errors occur repeatedly while the same PROM programmer is being used stop programming and check for problems in the PROM programmer and socket adapter etc Please notify your Hitachi repr...

Page 124: ... allowing high speed 2 state access for both byte data and word data 7 1 1 Block Diagram Figure 7 1 shows a block diagram of the on chip RAM H FF7E H FF7F Internal data bus upper 8 bits Internal data bus lower 8 bits Even numbered address Odd numbered address H FF7E H F782 H F780 H F780 H F782 H F781 H F783 On chip RAM Figure 7 1 RAM Block Diagram ...

Page 125: ...indicates the functions of each port Each port has of a port control register PCR that controls input and output and a port data register PDR for storing output data Input or output can be controlled by individual bits See 2 9 2 Notes on Bit Manipulation for information on executing bit manipulation instructions to write data in PCR or PDR Block diagrams of each port are given in Appendix C I O Po...

Page 126: ...on P26 TXD P25 RXD P24 SCK3 SCI3 data output TXD data input RXD clock input output SCK3 SCR3 SMR3 PMR6 P23 SO1 P22 SI1 P21 SCK1 SCI1 data output SO1 data input SI1 clock input output SCK1 PMR2 P20 IRQ4 ADTRG External interrupt 4 and A D converter external trigger PMR2 Port 5 8 bit I O port Input pull up MOS option P57 to P50 WKP7 to WKP0 Wakeup input WKP7 to WKP0 PMR5 Port 6 8 bit I O port Input p...

Page 127: ...Port 1 Figure 8 1 Port 1 Pin Configuration 8 2 2 Register Configuration and Description Table 8 2 shows the port 1 register configuration Table 8 2 Port 1 Registers Name Abbrev R W Initial Value Address Port data register 1 PDR1 R W H 00 H FFD4 Port control register 1 PCR1 W H 00 H FFE4 Port pull up control register 1 PUCR1 R W H 00 H FF9C Port mode register 1 PMR1 R W H 10 H FF98 ...

Page 128: ...he port 1 pins P17 to P10 functions as an input pin or output pin Setting a PCR1 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I O pin Upon reset PCR1 is initialized to H 00 PCR1 is a write only register All bits are read as 1 Por...

Page 129: ... sensing can be designated for IRQ3 TMIF For information about TMIF pin settings see 9 3 2 3 Timer Control Register F TCRF Bit 6 P16 IRQ2 TMCIY Pin Function Switch IRQ2 This bit selects whether pin P16 IRQ2 TMCIY is used as P16 or as IRQ2 TMCIY Bit 6 IRQ2 Description 0 Functions as P16 I O pin initial value 1 Functions as IRQ2 TMCIY input pin Note Rising or falling edge sensing can be designated f...

Page 130: ... 2 P12 TMOFH Pin Function Switch TMOFH This bit selects whether pin P12 TMOFH is used as P12 or as TMOFH Bit 2 TMOFH Description 0 Functions as P12 I O pin initial value 1 Functions as TMOFH output pin Bit 1 P11 TMOFL Pin Function Switch TMOFL This bit selects whether pin P11 TMOFL is used as P11 or as TMOFL Bit 1 TMOFL Description 0 Functions as P11 I O pin initial value 1 Functions as TMOFL outp...

Page 131: ...ble IRQ3 interrupts P16 IRQ2 TMCIY The pin function depends on bit IRQ2 in PMR1 bits TMY2 to TMY0 in TMY and bit PCR16 in PCR1 IRQ2 0 1 PCR16 0 1 TMY2 to TMY0 Not 111 111 Pin function P16 input pin P16 output pin IRQ2 input pin IRQ2 TMCIY input pin Note When using this pin for TMCIY input clear bit IEN2 in IENR1 to disable IRQ2 interrupts P15 IRQ1 The pin function depends on bit IRQ1 in PMR1 and b...

Page 132: ...n depends on bit TMOFH in PMR1 and bit PCR12 in PCR1 TMOFH 0 1 PCR12 0 1 Pin function P12 input pin P12 output pin TMOFH output pin P11 TMOFL The pin function depends on bit TMOFL in PMR1 and bit PCR11 in PCR1 TMOFL 0 1 PCR11 0 1 Pin function P11 input pin P11 output pin TMOFL output pin P10 TMOW The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1 TMOW 0 1 PCR10 0 1 Pin function P10...

Page 133: ...ous state High impedance Retains previous state Functional Functional Note A high level signal is output when the MOS pull up is in the on state 8 2 5 MOS Input Pull Up Port 1 has a built in MOS input pull up function that can be controlled by software When a PCR1 bit is cleared to 0 setting the corresponding PUCR1 bit to 1 turns on the MOS pull up for that pin The MOS input pull up function is in...

Page 134: ...2 Port 2 Pin Configuration 8 3 2 Register Configuration and Description Table 8 5 shows the port 2 register configuration Table 8 5 Port 2 Registers Name Abbrev R W Initial Value Address Port data register 2 PDR2 R W H 00 H FFD5 Port control register 2 PCR2 W H 00 H FFE5 Port mode register 2 PMR2 R W H 40 H FF99 Port mode register 6 PMR6 R W H F8 H FF9A Port pull up control register 2 PUCR2 R W H ...

Page 135: ...ister 2 PCR2 Bit 7 6 5 4 3 2 1 0 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W PCR2 is an 8 bit register for controlling whether each of the port 2 pins P27 to P20 functions as an input pin or output pin Setting a PCR2 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The settings in ...

Page 136: ... selects whether pin P27 IRQ0 is used as P27 or as IRQ0 Bit 7 IRQ0 Description 0 Functions as P27 input pin initial value 1 Functions as IRQ0 input pin Bit 6 Reserved Bit Bit 6 is reserved it is always read as 1 and cannot be modified Bit 5 P23 SO1 pin PMOS control POF1 This bit turns on and off the PMOS transistor in the P23 SO1 pin output buffer Bit 5 POF1 Description 0 CMOS output initial value...

Page 137: ...lue 1 Functions as SI1 input pin Bit 1 P21 SCK1 Pin Function Switch SCK1 This bit selects whether pin P21 SCK1 is used as P21 or as SCK1 Bit 1 SCK1 Description 0 Functions as P21 I O pin initial value 1 Functions as SCK1 I O pin Bit 0 P20 IRQ4 ADTRG Pin Function Switch IRQ4 This bit selects whether pin P20 IRQ4 ADTRG is used as P20 or as IRQ4 ADTRG Bit 0 IRQ4 Description 0 Functions as P20 I O pin...

Page 138: ...pin Bits 1 and 0 Reserved Bits Bits 1 and 0 are reserved they should be used cleared to 0 Port Pull Up Control Register 2 PUCR2 Bit 7 6 5 4 3 2 1 0 PUCR27 PUCR26 PUCR25 PUCR24 PUCR23 PUCR22 PUCR21 PUCR20 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W PUCR2 controls whether the MOS pull up of each port 2 pin is on or off When a PCR2 bit is cleared to 0 setting the correspo...

Page 139: ...n function P26 input pin P26 output pin TXD output pin P25 RXD The pin function depends on bit RE in SCR of SCI3 and bit PCR25 in PCR2 RE 0 1 PCR25 0 1 Pin function P25 input pin P25 output pin RXD input pin P24 SCK3 The pin function depends on bits CKE1 and CKE0 in SCR of SCI3 bit COM in SMR of SCI3 and bit PCR24 in PCR2 CKE1 0 1 CKE0 0 0 1 COM 0 1 PCR24 0 1 Pin function P24 input pin P24 output ...

Page 140: ...SCK1 in PMR2 bit CKS3 in SCR1 and bit PCR21 in PCR2 SCK1 0 1 CKS3 0 1 PCR21 0 1 Pin function P21 input pin P21 output pin SCK1 output pin SCK1 input pin P20 IRQ4 ADTRG The pin function depends on bit IRQ4 in PMR2 bit TRGE in AMR and bit PCR20 in PCR2 IRQ4 0 1 PCR20 0 1 TRGE 0 1 Pin function P20 input pin P20 output pin IRQ4 input pin IRQ4 ADTRG input pin Note When using this pin for ADTRG input cl...

Page 141: ...ious state High impedance Retains previous state Functional Functional Note High level output if the MOS pull up is on 8 3 5 MOS Input Pull Up Port 2 has a built in MOS input pull up function that can be controlled by software When a PCR2 bit is cleared to 0 setting the corresponding PUCR2 bit to 1 turns on the MOS pull up for that pin The MOS input pull up function is in the off state after a res...

Page 142: ...ort 5 Figure 8 3 Port 5 Pin Configuration 8 4 2 Register Configuration and Description Table 8 8 shows the port 5 register configuration Table 8 8 Port 5 Registers Name Abbrev R W Initial Value Address Port data register 5 PDR5 R W H 00 H FFD8 Port control register 5 PCR5 W H 00 H FFE8 Port pull up control register 5 PUCR5 R W H 00 H FF9E Port mode register 5 PMR5 R W H 00 H FF9B ...

Page 143: ...of the port 5 pins P57 to P50 functions as an input pin or output pin Setting a PCR5 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The settings in PCR5 and in PDR5 are valid only when the corresponding pin is designated as a general I O pin in PMR5 Upon reset PCR5 is initialized to H 00 PCR5 is a write only register All bits are read as 1...

Page 144: ...n WKPn Pin Function Switch WKPn This bit selects whether it is used as P5n or as WKPn Bit n WKPn Description 0 Functions as P5n I O pin initial value 1 Functions as WKPn input pin n 7 to 0 8 4 3 Pin Functions Table 8 9 shows the port 5 pin functions Table 8 9 Port 5 Pin Functions Pin Pin Functions and Selection Method P57 WKP7 to P50 WKP0 The pin function depends on bit WKPn in PMR5 and bit PCR5n ...

Page 145: ...tains previous state Functional Functional Note A high level signal is output when the MOS pull up is in the on state 8 4 5 MOS Input Pull Up Port 5 has a built in MOS input pull up function that can be controlled by software When a PCR5 bit is cleared to 0 setting the corresponding PUCR5 bit to 1 turns on the MOS pull up for that pin The MOS pull up function is in the off state after a reset PCR5...

Page 146: ...6 Figure 8 4 Port 6 Pin Configuration 8 5 2 Register Configuration and Description Table 8 11 shows the port 6 register configuration Table 8 11 Port 6 Registers Name Abbrev R W Initial Value Address Port data register 6 PDR6 R W H 00 H FFD9 Port control register 6 PCR6 W H 00 H FFE9 Port pull up control register 6 PUCR6 R W H 00 H FF9F ...

Page 147: ...W W PCR6 is an 8 bit register for controlling whether each of the port 6 pins P67 to P60 functions as an input pin or output pin Setting a PCR6 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin Upon reset PCR6 is initialized to H 00 PCR6 is a write only register All bits are read as 1 Port Pull Up Control Register 6 PUCR6 Bit 7 6 5 4 3 2 1 0 ...

Page 148: ... Standby Watch Subactive Active P67 to P60 High impedance Retains previous state Retains previous state High impedance Retains previous state Functional Functional Note A high level signal is output when the MOS pull up is in the on state 8 5 5 MOS Input Pull Up Port 6 has a built in MOS input pull up function that can be controlled by software When a PCR6 bit is cleared to 0 setting the correspon...

Page 149: ...P7 P7 7 6 5 4 3 2 1 0 Port 7 Figure 8 5 Port 7 Pin Configuration 8 6 2 Register Configuration and Description Table 8 14 shows the port 7 register configuration Table 8 14 Port 7 Registers Name Abbrev R W Initial Value Address Port data register 7 PDR7 R W H 00 H FFDA Port control register 7 PCR7 W H 00 H FFEA ...

Page 150: ...R7 bits are cleared to 0 the pin states are read Upon reset PDR7 is initialized to H 00 Port Control Register 7 PCR7 Bit 7 6 5 4 3 2 1 0 PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W PCR7 is an 8 bit register for controlling whether each of the port 7 pins P77 to P70 functions as an input pin or output pin Setting a PCR7 bit to 1 makes the...

Page 151: ... bit PCR7n in PCR7 n 7 to 0 PCR7n 0 1 Pin function P7n input pin P7n output pin 8 6 4 Pin States Table 8 16 shows the port 7 pin states in each operating mode Table 8 16 Port 7 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P77 to P70 High impedance Retains previous state Retains previous state High impedance Retains previous state Functional Functional ...

Page 152: ...P8 P8 7 6 5 4 3 2 1 0 Port 8 Figure 8 6 Port 8 Pin Configuration 8 7 2 Register Configuration and Description Table 8 17 shows the port 8 register configuration Table 8 17 Port 8 Registers Name Abbrev R W Initial Value Address Port data register 8 PDR8 R W H 00 H FFDB Port control register 8 PCR8 W H 00 H FFEB ...

Page 153: ...PCR8 bits are cleared to 0 the pin states are read Upon reset PDR8 is initialized to H 00 Port Control Register 8 PCR8 Bit 7 6 5 4 3 2 1 0 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W PCR8 is an 8 bit register for controlling whether each of the port 8 pins P87 to P80 functions as an input or output pin Setting a PCR8 bit to 1 makes the c...

Page 154: ... bit PCR8n in PCR8 n 7 to 0 PCR8n 0 1 Pin function P8n input pin P8n output pin 8 7 4 Pin States Table 8 19 shows the port 8 pin states in each operating mode Table 8 19 Port 8 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P87 to P80 High impedance Retains previous state Retains previous state High impedance Retains previous state Functional Functional ...

Page 155: ...P9 P9 7 6 5 4 3 2 1 0 Port 9 Figure 8 7 Port 9 Pin Configuration 8 8 2 Register Configuration and Description Table 8 20 shows the port 9 register configuration Table 8 20 Port 9 Registers Name Abbrev R W Initial Value Address Port data register 9 PDR9 R W H 00 H FFDC Port control register 9 PCR9 W H 00 H FFEC ...

Page 156: ...PCR9 bits are cleared to 0 the pin states are read Upon reset PDR9 is initialized to H 00 Port Control Register 9 PCR9 Bit 7 6 5 4 3 2 1 0 PCR97 PCR96 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W PCR9 is an 8 bit register for controlling whether each of the port 9 pins P97 to P90 functions as an input or output pin Setting a PCR9 bit to 1 makes the c...

Page 157: ... bit PCR9n in PCR9 n 7 to 0 PCR9n 0 1 Pin function P9n input pin P9n output pin 8 8 4 Pin States Table 8 22 shows the port 9 pin states in each operating mode Table 8 22 Port 9 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P97 to P90 High impedance Retains previous state Retains previous state High impedance Retains previous state Functional Functional ...

Page 158: ... PA 3 2 1 0 Port A Figure 8 8 Port A Pin Configuration 8 9 2 Register Configuration and Description Table 8 23 shows the port A register configuration Table 8 23 Port A Registers Name Abbrev R W Initial Value Address Port data register A PDRA R W H F0 H FFDD Port control register A PCRA W H F0 H FFED ...

Page 159: ...PCRA bits are cleared to 0 the pin states are read Upon reset PDRA is initialized to H F0 Port Control Register A PCRA Bit 7 6 5 4 3 2 1 0 PCRA3 PCRA2 PCRA1 PCRA0 Initial value 1 1 1 1 0 0 0 0 Read Write W W W W PCRA is an 8 bit register for controlling whether each of the port A pins PA3 to PA0 functions as an input or output pin Setting a PCRA bit to 1 makes the corresponding pin an output pin w...

Page 160: ... bit PCRAn in PCRA n 3 to 0 PCRAn 0 1 Pin function PAn input pin PAn output pin 8 9 4 Pin States Table 8 25 shows the port A pin states in each operating mode Table 8 25 Port A Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active PA3 to PA0 High impedance Retains previous state Retains previous state High impedance Retains previous state Functional Functional ...

Page 161: ...ription Table 8 26 shows the port B register configuration Table 8 26 Port B Register Name Abbrev R W Address Port data register B PDRB R H FFDE Port Data Register B PDRB Bit 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 Read Write R R R R Reading PDRB always gives the pin states However if a port B pin is selected as an analog input channel for the A D converter by AMR bits CH3 to CH0 that pin reads 0 regardle...

Page 162: ...ddress Port data register E PDRE R W H F0 H FFD3 Port control register E PCRE W H F0 H FFE3 Port Data Register E PDRE Bit 7 6 5 4 3 2 1 0 PE3 PE2 Initial value 1 1 1 1 0 0 0 0 Read Write R W R W PDRE is a 2 bit register that stores data for port E pins PE3 and PE2 If port E is read while PCRE bits are set to 1 the values stored in PDRE are directly read regardless of the actual pin states If port ...

Page 163: ...0 PCRE is a write only register All bits are read as 1 8 11 3 Pin Functions Table 8 28 shows the port E pin functions Table 8 28 Port E Pin Functions Pin Pin Functions and Selection Method PE3 PE2 The pin function depends on bit PCREn in PCRE n 3 2 PCREn 0 1 Pin function PEn input pin PEn output pin 8 11 4 Pin States Table 8 29 shows the port E pin states in each operating mode Table 8 29 Port E P...

Page 164: ...f 4 overflow periods Clock output ø 4 to ø 32 øW 4 to øW 32 8 choices TMOW Timer F 16 bit free running timer Event counter Can be used as two independent 8 bit timers Output compare ø 2 to ø 32 4 choices TMIF TMOFL TMOFH Timer G 8 bit timer Input capture Interval timer ø 2 to ø 64 øW 2 4 choices TMIG Counter clear designation possible Built in noise canceller circuit for input capture Timer Y 16 b...

Page 165: ...sing a 32 768 kHz crystal oscillator An interrupt is requested when the counter overflows Any of eight clock signals can be output from pin TMOW 32 768 kHz divided by 32 16 8 or 4 1 kHz 2 kHz 4 kHz 8 kHz or the system clock divided by 32 16 8 or 4 Block Diagram Figure 9 1 shows a block diagram of timer A ø PSW Internal data bus PSS Legend TMOW 1 4 TMA TCA ø 32 ø 16 ø 8 ø 4 W W W W ø 32 ø 16 ø 8 ø ...

Page 166: ...B1 9 2 2 Register Descriptions Timer Mode Register A TMA Bit 7 6 5 4 3 2 1 0 TMA7 TMA6 TMA5 TMA3 TMA2 TMA1 TMA0 Initial value 0 0 0 1 0 0 0 0 Read Write R W R W R W R W R W R W R W TMA is an 8 bit read write register for selecting the prescaler input clock and output clock Upon reset TMA is initialized to H 10 Bits 7 to 5 Clock Output Select TMA7 to TMA5 Bits 7 to 5 choose which of eight clock sig...

Page 167: ... TMA3 to TMA0 Bits 3 to 0 select the clock input to TCA The selection is made as follows Description Bit 3 TMA3 Bit 2 TMA2 Bit 1 TMA1 Bit 0 TMA0 Prescaler and Divider Ratio or Overflow Period Function 0 0 0 0 PSS ø 8192 initial value Interval timer 1 PSS ø 4096 1 0 PSS ø 2048 1 PSS ø 512 1 0 0 PSS ø 256 1 PSS ø 128 1 0 PSS ø 32 1 PSS ø 8 1 0 0 0 PSW 1 s Clock time base 1 PSW 0 5 s 1 0 PSW 0 25 s 1...

Page 168: ...erval timing resume immediately The clock input to timer A is selected by bits TMA2 to TMA0 in TMA any of eight internal clock signals output by prescaler S can be selected After the count value in TCA reaches H FF the next clock signal input causes timer A to overflow setting bit IRRTA to 1 in interrupt request register 1 IRR1 If IENTA 1 in interrupt enable register 1 IENR1 a CPU interrupt is req...

Page 169: ...arizes the timer A operation states Table 9 4 Timer A Operation States Operation Mode Reset Active Sleep Watch Sub active Sub sleep Standby TCA Interval Reset Functions Functions Halted Halted Halted Halted Clock time base Reset Functions Functions Functions Functions Functions Halted TMA Reset Functions Retained Retained Functions Retained Retained Note When real time clock time base functions ar...

Page 170: ...al Two interrupt sources counter overflow and compare match Can operate as two independent 8 bit timers timer FH and timer FL in 8 bit mode Timer FH 8 bit timer clocked by timer FL overflow signals when timer F operates as a 16 bit timer Choice of four internal clocks ø 32 ø 16 ø 4 ø 2 Output from pin TMOFH is toggled by one compare match signal the initial value of the toggle output can be set Co...

Page 171: ... OCRFH OCRFL Timer control register F Timer control status register F 8 bit timer counter FH 8 bit timer counter FL Output compare register FH Output compare register FL IRRTFH IRRTFL PSS Timer FH interrupt request flag Timer FL interrupt request flag Prescaler S IRRTFH IRRTFL TMIF TMOFL TMOFH TCFL TCRF OCRFL TCFH Compare circuit TCSRF Figure 9 2 Block Diagram of Timer F ...

Page 172: ...mer counter FH TCFH R W H 00 H FFB8 8 bit timer counter FL TCFL R W H 00 H FFB9 Output compare register FH OCRFH R W H FF H FFBA Output compare register FL OCRFL R W H FF H FFBB 9 3 2 Register Descriptions 16 Bit Timer Counter TCF 8 Bit Timer Counter TCFH 8 Bit Timer Counter TCFL TCF Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read Write R W R W R W R W ...

Page 173: ... F TCRF is set to 1 timer F functions as two separate 8 bit counters TCFH and TCFL The TCFH TCFL input clock is selected by TCRF bits CKSH2 to CKSH0 CKSL2 to CKSL0 TCFH TCFL can be cleared by a compare match signal This designation is made in bit CCLRH CCLRL in TCSRF When TCFH TCFL overflows from H FF to H 00 the overflow flag OVFH OVFL in TCSRF is set to 1 If bit OVIEH OVIEL in TCSRF is set to 1 ...

Page 174: ...f bit IENTFH in interrupt enable register 2 IENR2 is set to 1 a CPU interrupt is requested Output for pin TMOFH can be toggled by compare match The output level can also be set to high or low by bit TOLH of timer control register F TCRF 8 Bit Mode OCRFH OCRFL Setting bit CKSH2 in TCRF to 1 results in two 8 bit independent registers OCRFH and OCRFL The OCRFH contents are always compared with TCFH a...

Page 175: ...ing goes into effect immediately after this bit is written Bit 7 TOLH Description 0 Low level initial value 1 High level Bits 6 to 4 Clock Select H CKSH2 to CKSH0 Bits 6 to 4 select the input to TCFH from four internal clock signals or the overflow of TCFL Bit 6 CKSH2 Bit 5 CKSH1 Bit 4 CKSH0 Description 0 16 bit mode selected TCFL overflow signals are counted initial value 1 0 0 Internal clock ø 3...

Page 176: ...rom 0 to 1 or from 1 to 0 while the TMIF pin is at the low level may cause the timer F counter to be incremented Timer Control Status Register F TCSRF Bit 7 6 5 4 3 2 1 0 OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W TCSRF is an 8 bit read write register It is used for counter clear selection overflow and compare match indicati...

Page 177: ... mode bit 4 selects whether or not TCF is cleared when a compare match occurs between TCF and OCRF In 8 bit mode bit 4 selects whether or not TCFH is cleared when a compare match occurs between TCFH and OCRFH Bit 4 CCLRH Description 0 16 bit mode TCF clearing by compare match disabled initial value 8 bit mode TCFH clearing by compare match disabled 1 16 bit mode TCF clearing by compare match enabl...

Page 178: ...g conditions Set when the TCFL value matches the OCRFL value Bit 1 Timer Overflow Interrupt Enable L OVIEL Bit 1 enables or disables TCFL overflow interrupts Bit 1 OVIEL Description 0 TCFL overflow interrupt disabled initial value 1 TCFL overflow interrupt enabled Bit 0 Counter Clear L CCLRL Bit 0 selects whether or not TCFL is cleared when a compare match occurs between TCFL and OCRFL Bit 0 CCLRL...

Page 179: ...cess Write Access When the upper byte is written the upper byte data is loaded into the TEMP register Next when the lower byte is written the data in TEMP goes to the upper byte of the register and the lower byte data goes directly to the lower byte of the register Figure 9 3 shows a TCF write operation when H AA55 is written to TCF Read Access When the upper byte of TCF is read the upper byte dat...

Page 180: ...ace CPU H AA TEMP H AA TCFH TCFL Internal data bus When writing the upper byte CPU H 55 TEMP H AA TCFH H AA TCFL H 55 Internal data bus When writing the lower byte Bus interface Figure 9 3 TCF Write Operation CPU TCF ...

Page 181: ...EMP H FF TCFH H AA TCFL H FF Internal data bus When reading the upper byte CPU H FF TEMP H FF TCFH AB TCFL 00 Internal data bus When reading the lower byte Note Becomes H AB00 if counter is incremented once Figure 9 4 TCF Read Operation TCF CPU ...

Page 182: ...nal clock TCF is continuously compared with the contents of OCRF When these two values match the CMFH bit in TCSRF is set to 1 At this time if IENTFH of IENR2 is 1 a CPU interrupt is requested and the output at pin TMOFH is toggled If the CCLRH bit in TCSRF is 1 TCF is cleared The output at pin TMOFH can also be set by the TOLH bit in TCRF If timer F overflows from H FFFF to H 0000 the OVFH bit in...

Page 183: ...ed by bit IEG3 in IEGR An external clock pulse width of at least two system clock cycles ø is necessary otherwise the counter will not operate properly TMOFH and TMOFL Output Timing The outputs at pins TMOFH and TMOFL are the values set in bits TOLH and TOLL in TCRF When a compare match occurs the output value is inverted Figure 9 5 shows the output timing ø TMIF when IEG3 1 Count input clock TCF ...

Page 184: ...match and a compare match signal is generated If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction however the new value written in bit TOLH will be output at pin TMOFH The TMOFL output in 16 bit mode is indeterminate so this output should not be used Use the pin as a general input or output port If an OCRFL write occurs at the same time as a comp...

Page 185: ...time as an overflow signal the overflow signal is not output TCFL and OCRFL The output at pin TMOFL toggles when there is a compare match If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction however the new value written in bit TOLL will be output at pin TMOFL If an OCRFL write occurs at the same time as a compare match signal the compare match si...

Page 186: ...ion Separate input capture functions are provided for the rising and falling edges Counter overflow detection Can detect whether overflow occurred when the input capture signal was high or low Choice of counter clear It is possible to select whether or not the counter is cleared at the rising edge falling edge or both edges of the input capture input signal Two interrupt sources There is one input...

Page 187: ...NCS W TMG TCG ICRGF ICRGR IRRTG NCS PSS Timer mode register G Timer counter G Input capture register GF Input capture register GR Timer G interrupt request flag Noise canceller select Prescaler S Figure 9 6 Block Diagram of Timer G Pin Configuration Table 9 8 shows the timer G pin configuration Table 9 8 Pin Configuration Name Abbrev I O Function Input capture input TMIG Input Input capture ...

Page 188: ...KS0 in timer mode register G TMG To use TCG as an input capture timer set bit TMIG to 1 in PMR1 to use TCG as an interval timer clear bit TMIG to 0 When TCG is used as an input capture timer the TCG value can be cleared at the rising edge falling edge or both edges of the input capture signal depending on settings in TMG When TCG overflows goes from H FF to H 00 if the timer overflow interrupt ena...

Page 189: ... used the pulse width of the input capture signal should be at least 2ø or 2øSUB Upon reset ICRGF is initialized to H 00 Input Capture Register GR ICRGR Bit 7 6 5 4 3 2 1 0 ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 Initial value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R ICRGR is an 8 bit read only register When the rising edge of the input capture signal is detected the TCG value at...

Page 190: ...d cleared by software It cannot be set by software Bit 7 OVFH Description 0 Clearing conditions initial value After reading OVFH 1 cleared by writing 0 to OVFH 1 Setting conditions Set when the value of TCG overflows from H FF to H 00 Bit 6 Timer Overflow Flag L OVFL Bit 6 is a status flag indicating that TCG overflowed from H FF to H 00 when the input capture signal was low or in interval timer o...

Page 191: ... cleared at the rising falling or both edges of the input capture signal or is not cleared Bit 3 CCLR1 Bit 2 CCLR0 Description 0 0 TCG is not cleared initial value 1 TCG is cleared at the falling edge of the input capture signal 1 0 TCG is cleared at the rising edge of the input capture signal 1 TCG is cleared at both edges of the input capture signal Bits 1 0 Clock Select CKS1 CKS0 Bits 1 and 0 s...

Page 192: ...n is disabled NCS 0 the system clock is selected as the sampling clock When the noise canceller is enabled NCS 1 the internal clock selected by bits CKS1 and CKS0 in TMG becomes the sampling clock The input signal is sampled at the rising edge of this clock pulse Data is considered correct when the outputs of all five latch circuits match If they do not match the previous value is retained Upon re...

Page 193: ... counting an internal clock with a frequency of ø divided by 64 ø 64 The clock to be input can be selected by using bits CKS1 and CKS0 in TMG from four internal clock sources At the rising edge falling edge of the input capture signal input to pin TMIG the value of TCG is copied into ICRGR ICRGF If the input edge is the same as the edge selected by the IIEGS bit of TMG then bit IRRTG is set to 1 i...

Page 194: ...o 1 If bit OVIE of TMG is currently set to 1 then bit IRRTG is set to 1 in IRR2 If bit IENTG is also set to 1 in IENR2 then timer G requests a CPU interrupt For further details see 3 3 Interrupts Count Timing TCG is incremented by input pulses from an internal clock TMG bits CKS1 and CKS0 select one of four internal clocks ø 64 ø 32 ø 2 øW 2 derived by dividing the system clock ø and the watch clo...

Page 195: ... clock cycles Figure 9 10 shows the timing External input capture signal Sampling clock Noise canceller circuit output Internal input capture signal R Figure 9 10 Input Capture Signal Timing Noise Canceller Function Enabled Timing of Input Capture Figure 9 11 shows the input capture timing in relation to the internal input capture signal Internal input capture signal TCG Input capture register N 1...

Page 196: ... Halted Functions Halted Halted ICRGF Reset Functions Functions Retained Functions Halted Functions Halted Retained ICRGR Reset Functions Functions Retained Functions Halted Functions Halted Retained TMG Reset Functions Retained Retained Functions Retained Retained Note In active mode and sleep mode if øW 2 is selected as the TCG internal clock since the system clock and internal clock are not syn...

Page 197: ...ted For this reason in a case like No 3 in table 9 11 where the clock is switched at a time such that the clock signal goes from high level before switching to low level after switching the switchover is seen as a falling edge to generate the count clock causing TCG to be incremented Table 9 11 Internal Clock Switching and TCG Operation No Clock Levels Before and After Modifying Bits CKS1 and CKS0...

Page 198: ... 3 Goes from high level to low level N 1 N N 2 Clock before switching Clock after switching Count clock TCG CKS bits modified 4 Goes from high level to high level N 1 N 2 N Clock before switching Clock after switching Count clock CKS bits modified TCG Note The switchover is seen as a falling edge of the clock pulse and TCG is incremented ...

Page 199: ...ed from 0 to 1 then TMIG bit is changed from 0 to 1 before noise canceller circuit completes five samples TMIG pin level is high and NCS bit is changed from 0 to 1 then TMIG bit is changed from 1 to 0 before noise canceller circuit completes five samples Note When pin P13 is not used for input capture the input capture signal input to timer G is low Switching the input capture noise canceling func...

Page 200: ...o 0 assuming it has been set to 1 An alternative procedure is to avoid having the interrupt request flag set when the pin function is switched either by controlling the level of the input capture pin so that it does not satisfy the conditions in tables 9 12 and 9 13 or by setting the IIEGS bit of TMG to select the edge opposite to the falsely generated edge Set I bit to 1 in CCR Clear I bit to 0 i...

Page 201: ...ster GR H 00 Counter cleared TCG Figure 9 14 Sample Timer G Application 9 5 Timer Y 9 5 1 Overview Timer Y is a 16 bit up counter which is incremented by an input clock Timer Y has two functions an interval function and an auto reload function Features Features of timer Y are given below Choice of eight clocks The clock can be selected from seven internal clocks ø 8192 ø 2048 ø 512 ø 256 ø 64 ø 16...

Page 202: ... Table 9 14 shows the timer Y pin configuration Table 9 14 Timer Y Pin Configuration Name Abbrev I O Function Timer Y event input TMCIY Input Pin for event input to TCY Register Configuration Table 9 15 shows the timer Y register configuration Table 9 15 Timer Y Registers Name Abbrev R W Initial Value Address Timer mode register Y TMY R W H 78 H FFCD Timer counter YH TCYH R H 00 H FFCE Timer count...

Page 203: ...to 3 Reserved Bits Bits 6 to 3 are reserved bits They are always read as 1 and cannot be modified Bits 2 to 0 Clock Select TMY2 to TMY0 Bits 2 to 0 select the clock input to TCY For external event input the rising or falling edge can be selected Bit 2 TMY2 Bit 1 TMY1 Bit 0 TMY0 Description 0 0 0 Count on internal clock ø 8192 initial value 1 Count on internal clock ø 2048 1 0 Count on internal clo...

Page 204: ...y an input internal clock or external events The input clock is selected with bits TMY2 to TMY0 in TMY When TCY overflows from H FFFF to H 0000 or from H FFFF to the TLY set value IRRTY in IRR2 is set to 1 The TCY value can be read by the CPU at any time but as it is a 16 bit register data transfer between TCY and the CPU is carried out via a temporary register TEMP For details see 9 5 3 CPU Inter...

Page 205: ...Y Upon reset TLY is initialized to H 0000 9 5 3 Interface with the CPU TCY and TLY are 16 bit registers whereas the data bus between the CPU and on chip peripheral modules has an 8 bit width For this reason when the CPU accesses TCY or TLY it makes use of an 8 bit temporary register TEMP An access must be performed as a 16 bit unit using two consecutive byte size MOV instructions accessing the upp...

Page 206: ...ta bus When writing the lower byte Bus interface Figure 9 16 TLY Write Operation CPU TLY Read Access When the upper byte is read the upper byte data is sent directly to the CPU and the lower byte is loaded into TEMP Next when the lower byte is read the lower byte in TEMP is sent to the CPU Figure 9 17 shows a TCY read operation when H AAFF is read from TCY ...

Page 207: ...L H FF Module internal data bus When reading the upper byte CPU H FF TEMP H FF TCYH AB TCYL 00 Module internal data bus When reading the lower byte Note Becomes H AB00 if counter is incremented once Bus interface Figure 9 17 TCY Read Operation TCY CPU ...

Page 208: ...t see section 3 3 Interrupts Auto Reload Timer Operation When TMY7 in TMY is set to 1 timer Y operates as a 16 bit auto reload timer When a reload value is set in TLY it is simultaneously loaded into TCY and TCY starts counting up from that value When a clock pulse is input after the TCY count value has reached H FFFF timer Y overflows the TLY value is loaded into TCY and the count up continues fr...

Page 209: ...nctions Retained Retained Retained Retained Retained 9 6 Watchdog Timer 9 6 1 Overview The watchdog timer is equipped with an 8 bit counter that is incremented by an input clock An internal chip reset can be executed if the counter overflows because it is not updated normally due to a system crash etc Features Features of the watchdog timer are given below Incremented by a ø 8192 internal clock Re...

Page 210: ...og timer register configuration Table 9 17 Watchdog Timer Registers Name Abbrev R W Initial Value Address Timer control status register W TCSRW R W H AA H FFB4 Timer counter W TCW R W H 00 H FFB5 9 6 2 Register Descriptions Timer Control Status Register W TCSRW Bit 7 6 5 4 3 2 1 0 B6WI TCWE B4WI TCSRWE B2WI WDON BOWI WRST Initial value 1 0 1 0 1 0 1 0 Read Write R R W R R W R R W R R W Note Can be...

Page 211: ...n 0 Writing of 8 bit data to TCW is disabled initial value 1 Writing of 8 bit data to TCW is enabled Bit 5 Bit 4 Write Inhibit B4WI Bit 5 controls writing of data to bit 4 of TCSRW This bit is always read as 1 Data is not stored if written to this bit Bit 5 B4WI Description 0 Writing to bit 4 is enabled 1 Writing to bit 4 is disabled initial value Bit 4 Timer Control Status Register W Write Enable...

Page 212: ...peration enabled Setting condition When 1 is written to WDON while writing 0 to B2WI when TCSRWE is set to 1 Bit 1 Bit 0 Write Inhibit B0WI Bit 1 controls writing of data to bit 0 of timer control status register W This bit is always read as 1 Data is not stored if written to this bit Bit 1 B0WI Description 0 Writing to bit 0 is enabled 1 Writing to bit 0 is disabled initial value Bit 0 Watchdog T...

Page 213: ...to H 00 an internal reset signal is generated and WRST in TCSRW is set to 1 Upon reset TCW is initialized to H 00 9 6 3 Operation The watchdog timer is provided with an 8 bit timer that increments with each input clock ø 8192 If 1 is written to WDON while writing 0 to B2WI when TCSRWE in TCSRW is set to 1 TCW begins counting up When a clock pulse is input after the TCW count value has reached H FF...

Page 214: ...4 MHz Therefore 256 15 241 H F1 is set in TCW Figure 9 19 Example of Watchdog Timer Operation 9 6 4 Watchdog Timer Operating Modes Watchdog timer operating modes are shown in table 9 18 Table 9 18 Watchdog Timer Operating Modes Operation Mode Reset Active Sleep Watch Sub active Sub sleep Standby TCW Reset Functions Functions Halted Halted Halted Halted TCSRW Reset Functions Functions Retained Reta...

Page 215: ...fer SCI3 Synchronous serial transfer 8 bit data transfer Send receive or simultaneous send receive Asynchronous serial transfer Multiprocessor communication function Choice of 7 bit or 8 bit data length Choice of 1 bit or 2 bit stop bit length Odd or even parity Built in baud rate generator Receive error detection Break detection Interrupt requested at completion of transfer or error 10 2 SCI1 10 ...

Page 216: ...1 Serial control status register 1 Serial data register U Serial data register L SCI1 interrupt request flag Prescaler S IRRS1 Figure 10 1 SCI1 Block Diagram Pin Configuration Table 10 2 shows the SCI1 pin configuration Table 10 2 Pin Configuration Name Abbrev I O Function SCI1 clock pin SCK1 I O SCI1 clock input or output SCI1 data input pin SI1 Input SCI1 receive data input SCI1 data output pin ...

Page 217: ... R W R W R W R W R W R W SCR1 is an 8 bit read write register for selecting the operation mode the transfer clock source and the prescaler division ratio Upon reset SCR1 is initialized to H 00 Writing to this register stops a transfer in progress Bits 7 and 6 Operation Mode Select 1 0 SNC1 SNC0 Bits 7 and 6 select the operation mode Bit 7 SNC1 Bit 6 SNC0 Description 0 0 8 bit synchronous transfer ...

Page 218: ...CKS1 Bit 0 CKS0 Prescaler Division ø 5 MHz ø 2 5 MHz 0 0 0 ø 1024 initial value 204 8 µs 409 6 µs 1 ø 256 51 2 µs 102 4 µs 1 0 ø 64 12 8 µs 25 6 µs 1 ø 32 6 4 µs 12 8 µs 1 0 0 ø 16 3 2 µs 6 4 µs 1 ø 8 1 6 µs 3 2 µs 1 0 ø 4 0 8 µs 1 6 µs 1 ø 2 0 8 µs Serial Control Status Register 1 SCSR1 Bit 7 6 5 4 3 2 1 0 SOL ORER STF Initial value 1 0 0 1 1 1 0 0 Read Write R W R W R R W Note Only a write of 0 ...

Page 219: ...l clock is used bit 5 indicates the occurrence of an overrun error If a clock pulse is input after transfer completion this bit is set to 1 indicating an overrun If noise occurs during a transfer causing an extraneous pulse to be superimposed on the normal serial clock incorrect data may be transferred Bit 5 ORER Description 0 Clearing conditions initial value After reading ORER 1 cleared by writi...

Page 220: ...tten or read only after data transmission or reception is complete If this register is written or read while a data transfer is in progress the data contents are not guaranteed The SDRU value upon reset is not fixed Serial Data Register L SDRL Bit 7 6 5 4 3 2 1 0 SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Unde...

Page 221: ... format Figure 10 2 shows the data transfer format Data is sent and received starting from the least significant bit in LSB first format Transmit data is output from one falling edge of the serial clock until the next falling edge Receive data is latched at the rising edge of the serial clock SCK SO SI 1 1 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 10 2 Transfer Format 3 Data transfe...

Page 222: ...nternal state of SCI1 3 Set the SCSR1 start flag STF to 1 SCI1 starts operating and receives data at pin SI1 4 After data reception is complete bit IRRS1 in interrupt request register 1 IRR1 is set to 1 5 Read the received data from SDRL and SDRU as follows 8 bit transfer mode SDRL 16 bit transfer mode Upper byte in SDRU lower byte in SDRL 6 After data reception is complete an overrun occurs if th...

Page 223: ...itted and received in synchronization with the serial clock input at pin SCK1 After data transmission and reception are complete an overrun occurs if the serial clock continues to be input no data is transmitted or received and the SCSR1 overrun error flag bit ORER is set to 1 While transmission is stopped the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1 10 2 4 Interrupt So...

Page 224: ...a communication formats Data length seven or eight bits Stop bit length one or two bits Parity even odd or none Multiprocessor bit one or none Receive error detection parity overrun and framing errors Break detection by reading the RXD level directly when a framing error occurs Synchronous mode Serial data communication is synchronized with a clock signal SCI3 can communicate with other chips havi...

Page 225: ...ud rate generator Internal clock ø 64 ø 16 ø 4 ø Clock Transmit receive control Internal data bus Interrupt requests TEI TXI RXI ERI Legend Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter Figure 10 3 SCI3 Block Diagram ...

Page 226: ...FF H FFA9 Serial control register 3 SCR3 R W H 00 H FFAA Transmit data register TDR R W H FF H FFAB Serial status register SSR R W H 84 H FFAC Receive data register RDR R H 00 H FFAD Transmit shift register TSR Not possible Receive shift register RSR Not possible Bit rate counter BRC Not possible 10 3 2 Register Descriptions Receive Shift Register RSR 7 6 5 4 3 0 2 1 Bit Read Write The receive shi...

Page 227: ...uously RDR is exclusively for receiving data and cannot be written by the CPU RDR is initialized to H 00 upon reset or in standby mode watch mode subactive mode or subsleep mode Transmit Shift Register TSR Bit 7 6 5 4 3 2 1 0 Read Write The transmit shift register TSR is for transmitting serial data Transmit data is first transferred from the transmit data register TDR to TSR then is transmitted f...

Page 228: ...sleep mode Serial Mode Register SMR Bit 7 6 5 4 3 2 1 0 COM CHR PE PM STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W The serial mode register SMR is an 8 bit register for setting the serial data communication format and for selecting the clock source of the baud rate generator SMR can be read and written by the CPU at any time SMR is initialized to H 00 ...

Page 229: ...d or even parity as designated in bit PM Bit 4 Parity Mode PM In asynchronous mode bit 4 selects whether odd or even parity is to be added to transmitted data and checked in received data The setting here is valid only if parity adding checking is enabled in bit PE In synchronous mode or if parity adding checking is disabled in asynchronous mode bit PM is ignored Bit 4 PM Description 0 Even parity...

Page 230: ...racter Bit 2 Multiprocessor Mode MP Bit 2 enables or disables the multiprocessor communication function When the multiprocessor communication function is enabled the parity enable PE and parity mode PM settings are ignored The MP bit is valid only in asynchronous mode it should be cleared to 0 in synchronous mode See 10 3 6 for details on the multiprocessor communication function Bit 2 MP Descript...

Page 231: ...ial status register SSR is set to 1 The TXI interrupt can be cleared by clearing bit TDRE to 0 or by clearing bit TIE to 0 Bit 7 TIE Description 0 Transmit data empty interrupt request TXI disabled initial value 1 Transmit data empty interrupt request TXI enabled Bit 6 Receive Interrupt Enable RIE Bit 6 enables or disables the receive error interrupt request ERI and the receive data full interrupt...

Page 232: ... in asynchronous mode or serial clock input is detected in synchronous mode Before setting RE to 1 it is necessary to set the receive format in SMR Bit 3 Multiprocessor Interrupt Enable MPIE Bit 3 enables or disables multiprocessor interrupt requests This setting is valid only in asynchronous mode and only when the multiprocessor mode bit MP in the serial mode register SMR is set to 1 It applies o...

Page 233: ... when operation is in asynchronous mode using an internal clock CKE1 0 This bit is invalid in synchronous mode or when using an external clock CKE1 1 In synchronous mode and in external clock mode clear CKE0 to 0 After setting bits CKE1 and CKE0 the operation mode must first be set in the serial mode register SMR See table 10 10 in 10 3 3 Operation for details on clock source selection Description...

Page 234: ... Bit 2 TEND and bit 1 MPBR are read only bits and cannot be modified SSR is initialized to H 84 upon reset or in standby mode watch mode subactive mode or subsleep mode Bit 7 Transmit Data Register Empty TDRE Bit 7 is a status flag indicating that data has been transferred from TDR to TSR Bit 7 TDRE Description 0 Indicates that transmit data written to TDR has not been transferred to TSR Clearing ...

Page 235: ... if receiving of data is completed while bit RDRF remains set to 1 If this happens receive data will be lost Bit 5 Overrun Error OER Bit 5 is a status flag indicating that an overrun error has occurred during data receiving Bit 5 OER Description 0 Indicates that data receiving is in progress or has been completed 1 initial value Clearing condition After reading OER 1 cleared by writing 0 to OER 1 ...

Page 236: ...annot be continued In synchronous mode data transmission and reception cannot be performed if FER is set to 1 Bit 3 Parity Error PER Bit 3 is a status flag indicating that a parity error has occurred during asynchronous receiving Bit 3 PER Description 0 Indicates that data receiving is in progress or has been completed 1 initial value Clearing condition After reading PER 1 cleared by writing 0 to ...

Page 237: ...a received in asynchronous mode using a multiprocessor format MPBR is a read only bit and cannot be modified Bit 1 MPBR Description 0 Indicates reception of data in which the multiprocessor bit is 0 initial value 1 Indicates reception of data in which the multiprocessor bit is 1 Note If bit RE in SCR3 is cleared to 0 while a multiprocessor format is in use MPBR retains its previous state Bit 0 Mul...

Page 238: ... together with the baud rate generator clock selected by bits CKS1 and CKS0 in the serial mode register SMR sets the transmit receive bit rate BRR can be read or written by the CPU at any time BRR is initialized to H FF upon reset or in standby mode watch mode subactive mode or subsleep mode Table 10 6 gives examples of how BRR is set in asynchronous mode The values in table 10 6 are for active hi...

Page 239: ...7 0 0 12 0 16 0 13 2 48 9600 0 3 0 0 6 2 48 19200 0 1 0 31250 0 0 0 0 1 0 38400 0 0 0 Table 10 6 BRR Settings and Bit Rates in Asynchronous Mode cont OSC MHz 4 9152 6 7 3728 8 Bit Rate bits s n N Error n N Error n N Error n N Error 110 1 174 0 26 1 212 0 03 2 64 0 70 2 70 0 03 150 1 127 0 1 155 0 16 1 191 0 1 207 0 16 300 0 255 0 1 77 0 16 1 95 0 1 103 0 16 600 0 127 0 0 155 0 16 0 191 0 0 207 0 1...

Page 240: ... 0 15 1 73 19200 0 7 0 0 7 1 73 31250 0 4 1 70 0 4 0 38400 0 3 0 0 3 1 73 Notes 1 Settings should be made so that error is within 1 2 BRR setting values are derived by the following equation N 106 1 OSC 64 22n B B Bit rate bits s N BRR baud rate generator setting 0 N 255 OSC Value of øOSC MHz n Baud rate generator input clock number n 0 1 2 3 The meaning of n is shown in table 10 7 Table 10 7 Rela...

Page 241: ...selected frequencies in asynchronous mode Values in table 10 8 are for active high speed mode Table 10 8 Maximum Bit Rate at Selected Frequencies Asynchronous Mode Setting OSC MHz Maximum Bit Rate bits s n N 2 31250 0 0 2 4576 38400 0 0 4 62500 0 0 4 194304 65536 0 0 4 9152 76800 0 0 6 93750 0 0 7 3728 115200 0 0 8 125000 0 0 9 8304 153600 0 0 10 156250 0 0 Table 10 9 shows typical BRR settings in...

Page 242: ... 19 0 39 0 49 50K 0 4 0 9 0 19 0 24 100K 0 4 0 9 250K 0 0 0 1 0 3 0 4 500K 0 0 0 1 1M 0 0 2 5M Blank Cannot be set Can be set but error will result Continuous transmit receive operation is not possible at this setting Note BRR setting values are derived by the following equation N 106 1 OSC 8 22n B B Bit rate bits s N BRR baud rate generator setting 0 N 255 OSC Value of øOSC MHz n Baud rate genera...

Page 243: ...oice for the addition of a parity bit the multiprocessor bit as well as one or two stop bits these options determine the transmit receive format and the character length Framing error FER parity error PER overrun error OER and break signal can be detected when data is received Clock source Choice of internal clocks or an external clock When an internal clock is selected Operates on baud rate gener...

Page 244: ...OM Bit 6 CHR Bit 2 MP Bit 5 PE Bit 3 STOP Mode Data Length Multipro cessor Bit Parity Bit Stop Bit Length 0 0 0 0 0 Asynchronous 8 bit data None None 1 bit 1 mode 2 bits 1 0 Yes 1 bit 1 2 bits 1 0 0 7 bit data None 1 bit 1 2 bits 1 0 Yes 1 bit 1 2 bits 0 1 0 Asynchronous 8 bit data Yes None 1 bit 1 mode 2 bits 1 0 multiprocessor 7 bit data 1 bit 1 format 2 bits 1 0 Synchronous mode 8 bit data None...

Page 245: ...urce Pin SCK3 Function 0 0 0 Asynchronous Internal I O port SCK3 pin not used 1 mode Outputs clock with same frequency as bit rate 1 0 External Clock should be input with frequency 16 times the desired bit rate 1 0 0 Synchronous Internal Outputs a serial clock 1 0 mode External Inputs a serial clock 0 1 1 Reserved illegal settings 1 0 1 1 1 1 ...

Page 246: ...ions before the reception of the next serial data in RSR is completed TXI TDRE TIE When TSR empty previous transmission complete is detected and the transmit data set in TDR is transferred to TSR TDRE is set to 1 If TIE is 1 at this time TXI is enabled and an interrupt occurs See figure 10 4 b The TXI interrupt handling routine writes the next transmit data to TDR and clears TDRE to 0 Continuous d...

Page 247: ...terrupt TDR next transmit data TSR transmitting TXD pin TDRE 0 TDR TSR transmission complete next data transferred TXD pin TDRE 1 TXI requested if TIE 1 Figure 10 4 b TDRE Setting and TXI Interrupt TDR TSR transmitting TXD pin TEND 0 TDR TSR transmission complete TXD pin TEND 1 TEI requested if TEIE 1 Figure 10 4 c TEND Setting and TEI Interrupt ...

Page 248: ...ommunication The communication line in asynchronous communication mode normally stays at the high level in the mark state SCI3 monitors the communication line and begins serial data communication when it detects a space low level signal which is regarded as a start bit One character consists of a start bit low level transmit receive data in LSB first order a parity bit high or low level and finall...

Page 249: ... 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 S 8 bit data STOP 0 0 0 1 S 8 bit data STOP STOP 0 1 0 0 S 8 bit data P STOP 0 1 0 1 S 8 bit data P STOP STOP 1 0 0 0 S 7 bit data STOP 1 0 0 1 S 7 bit data STOP STOP 1 1 0 0 S 7 bit data P STOP 1 1 0 1 S 7 bit data P STOP STOP 0 1 0 S 8 bit data MPB STOP 0 1 1 S 8 bit data MPB STOP STOP 1 1 0 S 7 bit data MPB STOP 1 1 1 S 7 bit data MPB STOP STOP Legend S Start...

Page 250: ...ansmit receive data Serial data 1 character 1 frame 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Clock Figure 10 6 Phase Relation of Output Clock and Communication Data in Asynchronous Mode 8 Bit Data Parity Bit Added and 2 Stop Bits 3 Data Transmit Receive Operations SCI3 Initialization Before data is sent or received bits TE and RE in serial control register 3 SCR3 must be cleared to 0 after which initiali...

Page 251: ... when using an external clock Wait for at least a 1 bit interval then set bits RIE TIE TEIE and MPIE and set bit TE or RE in SCR3 to 1 Setting TE or RE No Yes Wait End enables SCI3 to use the TXD or RXD pin The initial states in asynchronous mode are the mark transmit state and the idle receive state waiting for a start bit 1 Set bits CKE1 and CKE0 Select the clock using serial control register 3 ...

Page 252: ...onfirming that bit TDRE 1 write transmit data in the transmit data register TDR When data is written to TDR TDRE is automatically cleared to 0 To continue transmitting data first read TDRE to confirm that it is set to 1 indicating that data writing is enabled then write the next data to TDR When data is written to TDR TDRE is automatically cleared to 0 To output a break signal when transmission en...

Page 253: ...ansmission of the next frame starts If TDRE is 1 the TEND bit in SSR is set to 1 and after the stop bit is sent the mark state is entered in which 1 is continuously output A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1 Figure 10 9 shows a typical operation in asynchronous transmission mode 0 D0 D1 D7 0 1 1 D0 D1 D7 0 1 1 0 Start bit Parity bit Stop bit Parity bit Stop b...

Page 254: ...the serial status register SSR and after confirming that bit RDRF 1 read received data from the receive data register RDR When RDR data is read RDRF is automatically cleared to 0 3 To continue receiving data read bit RDRF and finish reading RDR before the stop bit of the present frame is received When data is read from RDR RDRF is automatically cleared to 0 4 When a receive error occurs read bits ...

Page 255: ...ived data is stored in RDR At that time if bit RIE in SCR3 is set to 1 an RXI interrupt is requested If the error check detects a receive error the appropriate error flag OER PER or FER is set to 1 RDRF retains the same value as before the data was received If at this time bit RIE in SCR3 is set to 1 an ERI interrupt is requested Table 10 15 gives the receive error detection conditions and the pro...

Page 256: ... Asynchronous Mode 8 Bit Data Parity Bit Added and 1 Stop Bit 10 3 5 Operation in Synchronous Mode In synchronous mode data is sent or received in synchronization with clock pulses This mode is suited to high speed serial communication SCI3 consists of independent transmit and receive modules so full duplex communication is possible sharing the same clock between both modules Both the transmit and...

Page 257: ...nous receive mode SCI3 latches receive data in synchronization with the rising edge of the serial clock The transmit receive format is fixed at 8 bit data No parity bit or multiprocessor bit is added in this mode 2 Clock Either an internal clock from the built in baud rate generator is used or an external clock is input at pin SCK3 The choice of clock sources is designated by bit COM in SMR and bi...

Page 258: ...ster BRR Note that this setting is not required when using an external clock Wait for at least a 1 bit interval then set bits RIE TIE TEIE and MPIE and set bit TE or RE in SCR3 to 1 Setting TE or RE Note In simultaneous transmit receive operations the TE and RE bits should both be cleared to 0 or set to 1 simultaneously No Yes Wait End enables SCI3 to use the TXD or RXD pin The initial states in a...

Page 259: ...nd after confirming that bit TDRE 1 write transmit data in the transmit data register TDR When data is written to TDR TDRE is automatically cleared to 0 If clock output has been selected after data is written to TDR the clock is output and data transmission begins To continue transmitting data first read TDRE to confirm that it is set to 1 indicating that data writing is enabled then write the nex...

Page 260: ...DRE is 0 data is transferred from TDR to TSR and after the MSB bit 7 is sent transmission of the next frame starts If TDRE is 1 the TEND bit in SSR is set to 1 and after the MSB bit 7 is sent the MSB state is maintained A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1 After data transmission ends pin SCK3 is held at the high level Note Data transmission cannot take place ...

Page 261: ... the serial status register SSR to determine if an error has occurred If an overrun error has occurred overrun error processing is executed To continue receiving data read bit RDRF and read the received data in RDR before the MSB bit 7 of the present frame is received When data is read from RDR RDRF is automatically cleared to 0 When an overrun error occurs read bit OER in SSR After the necessary ...

Page 262: ...ed OER is set to 1 and RDRF remains set to 1 Then if bit RIE in SCR3 is set to 1 an ERI interrupt is requested For the overrun error detection conditions and receive data processing see table 10 15 Note Data receiving cannot be continued while a receive error flag is set Before continuing the receive operation it is necessary to clear the OER FER PER and RDRF flags to 0 Figure 10 17 shows a typica...

Page 263: ...ng and receiving serial data read bit RDRF and finish reading RDR before the MSB bit 7 of the present frame is received Also read bit When an overrun error occurs read bit OER in SSR After the necessary error processing be sure to clear OER to 0 Data transmission and reception cannot take place while bit OER is set to 1 See figure 10 16 for overrun error processing Note When switching from transmi...

Page 264: ...le that identifies the receiving processor and a data sending cycle in which communication data is sent to the specified receiving processor The multiprocessor bit is used to distinguish between the ID sending cycle and the data sending cycle The multiprocessor bit is 1 in an ID sending cycle and 0 in a data sending cycle The transmitting processor starts by sending the ID of the receiving process...

Page 265: ...ted by ID ID 01 ID 02 ID 03 ID 04 H 01 H AA MPB 1 MPB 0 MPB Multiprocessor bit Figure 10 19 Example of Interprocessor Communication Using Multiprocessor Format Data H AA Sent to Receiving Processor A Four communication formats are available Parity bit settings are ignored when a multiprocessor format is selected For details see table 10 14 For a description of the clock used in multiprocessor comm...

Page 266: ...e sure it is set to 1 indicating that data writing is enabled Then write the next data to TDR When data is written to TDR TDRE is automatically cleared to 0 To output a break signal at the end of data transmission first set the port values PCR 1 and PDR 0 then clear bit TE in SCR3 to 0 Read the serial status register SSR and after confirming that bit TDRE 1 set bit MPBT multiprocessor bit transmit...

Page 267: ...rred from TDR to TSR and after the stop bit is sent transmission of the next frame starts If TDRE is 1 the TEND bit in SSR is set to 1 and after the stop bit is sent the output remains at 1 mark state A TEI interrupt is requested in this state if bit TEIE transmit end interrupt enable in SCR3 is set to 1 Figure 10 21 shows a typical SCI3 operation in multiprocessor communication mode 0 D0 D1 D7 D0...

Page 268: ...DRF 1 then read received data from the receive data register RDR If a receive error occurs read bits OER and FER in SSR to determine which error occurred After the necessary error processing be sure to clear the error flags to 0 Data reception cannot resume while bit OER or FER is set to 1 When a framing error occurs a break can be detected by reading the RXD pin value No Yes Yes No Yes No Yes Yes...

Page 269: ...Start bit Receive data ID2 Receive data data 2 Mark idle state MPB MPB MPB MPB MPIE RDRF RDR value ID1 b Data matches own ID 1 frame 1 frame 1 frame 1 frame ID1 If not own ID set MPIE to 1 again SCI3 operation User processing RXI request MPIE cleared to 0 RDRF cleared to 0 If own ID continue receiving SCI3 operation User processing RDRF cleared to 0 Read data from RDR and set MPIE to 1 again Data ...

Page 270: ...tial value of bit TDRE is 1 Accordingly if the transmit data empty interrupt request TXI is enabled by setting bit TIE to 1 in SCR3 before placing transmit data in TDR TXI will be requested even though no transmit data has been readied Likewise the initial value of bit TEND is 1 Accordingly if the transmit end interrupt request TEI is enabled by setting bit TEIE to 1 in SCR3 before placing transmi...

Page 271: ... to TDR should be performed only once not two or more times always after confirming that bit TDRE is set to 1 Operation when Multiple Receive Errors Occur at the Same Time When two or more receive errors occur at the same time the status flags in SSR are set as shown in table 10 17 If an overrun error occurs data is not transferred from RSR to RDR and receive data is lost Table 10 17 SSR Status Fl...

Page 272: ...es an I O port outputting the value 1 To send a break signal during transmission set the PCR bit to 1 and clear the PDR bit to 0 then clear the TXD bit in PMR6 to 0 When the TXD bit in PMR6 is cleared to 0 the TXD pin becomes an I O port outputting 0 regardless of the current transmission status Receive Error Flags and Transmit Operation Sysnchronous Mode Only When a receive error flag ORER PER or...

Page 273: ...ation M 0 5 L 0 5 F 100 1 2N D 0 5 N Equation 1 M Receive margin N Ratio of clock frequency to bit rate N 16 D Clock duty cycle D 0 5 to 1 L Frame length L 9 to 12 F Absolute value of clock frequency error In equation 1 if F absolute value of clock frequency error 0 and D clock duty cycle 0 5 the receive margin is 46 875 as given by equation 2 below When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 Equat...

Page 274: ...ompleted This is illustrated in figure 10 25 Communica tion line RDRF RDR Frame 1 Frame 2 Frame 3 Data 1 Data 2 Data 3 Data 1 Data 2 RDR read RDR read At A data 1 is read At B data 2 is read A B Figure 10 25 Relationship between Data and RDR Read Timing To avoid the situation described above RDR reading should be carried out only once not two or more times after confirming that bit RDRF is set to ...

Page 275: ...ine 1 4 7 2 5 8 0 3 6 9 A B C D R1 697 Hz R2 770 Hz R3 852 Hz R4 941 Hz C1 1 209 Hz C2 1 336 Hz C3 1 477 Hz C4 1 633 Hz Figure 11 1 DTMF Frequencies 11 1 1 Features Features of the DTMF generator are as follows Generates sine waves with DTMF frequencies from the system clock input at the OSC pins fOSC The OSC clock 1 2 MHz to 10 MHz selectable in 400 kHz steps is divided to generate a 400 kHz cloc...

Page 276: ...pendent row group or column group output 11 1 2 Block Diagram Figure 11 2 shows a block diagram of the DTMF generator DTLR Clock counter 400 kHz 1 2 MHz to 10 MHz selectable in 400 kHz steps D A sine wave counter Modified programmable divider DTCR Feedback Column section Feedback TONED VTref fOSC Internal data bus Row section DTLR DTCR DTMF load register DTMF control register D A sine wave counter...

Page 277: ... power supply pin VTref Reference level voltage for DTMF output DTMF signal output pin TONED Output DTMF signal output 11 1 4 Register Configuration Table 11 2 shows the register configuration of the DTMF generator Table 11 2 Register Configuration Name Abbrev R W Initial Value Address DTMF control register DTCR R W H 40 H FFB2 DTMF load register DTLR R W H E0 H FFB3 ...

Page 278: ...operation of the DTMF generator Bit 7 DTEN Description 0 DTMF generator is halted initial value 1 DTMF generator operates Bit 6 Reserved Bit Bit 6 is reserved it is always read as 1 and cannot be modified Bit 5 Column Output Enable CLOE Bit 5 enables or disables DTMF column signal output Bit 5 CLOE Description 0 DTMF column signal output is disabled high impedance initial value 1 DTMF column signa...

Page 279: ...cy 1336 Hz C2 1 0 DTMF column signal output frequency 1447 Hz C3 1 DTMF column signal output frequency 1633 Hz C4 Bits 1 and 0 DTMF Row Signal Output Frequency 1 and 0 RWF1 RWF0 Bits 1 and 0 select the DTMF row signal frequency R1 to R4 Bit 1 RWF1 Bit 0 RWF0 Description 0 0 DTMF row signal output frequency 697 Hz R1 initial value 1 DTMF row signal output frequency 770 Hz R2 1 0 DTMF row signal out...

Page 280: ... frequency which will generate a 400 kHz clock for input to the DTMF generator The ratio is set as a counter value from 3 to 25 corresponding to OSC clock frequencies of 1 2 to 10 MHz in 400 kHz steps Description Bit 4 DTL4 Bit 3 DTL3 Bit 2 DTL2 Bit 1 DTL1 Bit 0 DTL0 Division Ratio OSC Clock Frequency 0 0 0 0 0 Illegal setting initial value 1 Illegal setting 1 0 Illegal setting 1 3 1 2 MHz 1 0 0 4...

Page 281: ...Figure 11 3 shows an equivalent circuit for the TONED output Figure 11 4 shows the output waveform of an independent row group or column group signal One cycle of the output is divided into 32 segments giving a stable output with low distortion Control Output control Row Column VT GND ref TONED Figure 11 3 Equivalent Circuit for TONED Output 1 2 3 4 5 6 7 8 9 10 11 12131415161718192021222324252627...

Page 282: ... 0 26 C2 1336 1333 33 0 20 C3 1477 1481 48 0 30 C4 1633 1639 34 0 39 11 3 2 Operation Flow The procedure for using the DTMF generator is given below 1 Set the OSC clock division ratio in DTLR to match the frequency of the connected system clock oscillator 1 2 MHz to 10 MHz in 400 kHz steps 2 Select a row R1 to R4 and or column C1 to C4 frequency with bits CLF1 CLF0 RWF1 and RWF0 in DTCR 3 Select r...

Page 283: ...Note Numbers at ends of signal lines are pin numbers of HA16808ANT Figure 11 5 Connection to HA16808 ANT 11 5 Application Notes When using the DTMF generator note the following point Be sure that the DTLR setting DTL4 to DTL0 matches the system clock frequency at the OSC pins Normal DTMF signal output frequencies will not be obtained unless the DTLR setting matches the OSC frequency ...

Page 284: ...rter and can convert up to four channels of analog input 12 1 1 Features The A D converter has the following features 8 bit resolution 4 input channels Conversion time approx 12 4 µs per channel at 5 MHz operation Built in sample and hold function Interrupt requested on completion of A D conversion A D conversion can be started by external trigger input ...

Page 285: ...ta bus AMR ADSR ADRR Control logic Com parator AN4 AN5 AN6 AN7 ADTRG AVCC AVSS Multiplexer Reference voltage IRRAD AVCC AVSS Legend AMR ADSR ADRR IRRAD A D mode register A D start register A D result register A D converter interrupt request flag Figure 12 1 Block Diagram of the A D Converter ...

Page 286: ...nalog input pin 5 AN5 Input Analog input channel 5 Analog input pin 6 AN6 Input Analog input channel 6 Analog input pin 7 AN7 Input Analog input channel 7 External trigger input pin ADTRG Input External trigger input for starting A D conversion 12 1 4 Register Configuration Table 12 2 shows the A D converter register configuration Table 12 2 Register Configuration Name Abbrev R W Initial Value Add...

Page 287: ...d by the CPU at any time but the ADRR values during A D conversion are undefined After A D conversion is complete the conversion result is stored in ADRR as 8 bit data this data is held in ADRR until the next conversion operation starts ADRR is not cleared on reset 12 2 2 A D Mode Register AMR Bit 7 6 5 4 3 2 1 0 CKS TRGE CKS1 CH3 CH2 CH1 CH0 Initial value 0 0 0 1 0 0 0 0 Read Write R W R W R W R ...

Page 288: ...nitial value 1 Enables start of A D conversion by rising or falling edge of external trigger at pin ADTRG Note The external trigger ADTRG edge is selected by bit IEG4 of the interrupt edge select register IEGR See 3 3 2 for details Bit 5 Clock Select 1 CKS1 Bits CKS and CKS1 select the A D conversion speed See bit 7 clock select CKS for details Bit 4 Reserved Bit Bit 4 is reserved it is always rea...

Page 289: ...o sets ADSF to 1 When conversion is complete the converted data is set in the A D result register ADRR and at the same time ADSF is cleared to 0 Bit 7 A D Start Flag ADSF Bit 7 controls and indicates the start and end of A D conversion Bit 7 ADSF Description 0 Read access Indicates the completion of A D conversion initial value Write access Stops A D conversion 1 Read access Indicates A D conversi...

Page 290: ...A D conversion bit ADSF should first be cleared to 0 stopping the conversion operation in order to avoid malfunction 12 3 2 Start of A D Conversion by External Trigger Input The A D converter can be made to start A D conversion by input of an external trigger signal External trigger input is enabled at pin ADTRG when bit IRQ4 in port mode register 2 for the I O port PMR2 is set to 1 and bit TRGE i...

Page 291: ...by setting bit IENAD to 1 and A D conversion is started by setting bit ADSF to 1 2 When A D conversion is complete bit IRRAD is set to 1 and the A D conversion result is stored in the A D result register ADRR At the same time ADSF is cleared to 0 and the A D converter goes to the idle state 3 Bit IENAD 1 so an A D conversion end interrupt is requested 4 The A D interrupt handling routine starts 5 ...

Page 292: ...NAD ADSF Channel 4 AN 4 operation state ADRR Set Set Set Read conversion result Read conversion result A D conversion result 1 A D conversion result 2 A D conversion starts Note indicates instruction execution by software Figure 12 3 Typical A D Converter Operation Timing ...

Page 293: ...ed and input channel Perform A D conversion End Yes No Disable A D conversion end interrupt Start A D conversion ADSF 0 No Yes Read ADSR Read ADRR data Figure 12 4 Flow Chart of Procedure for Using A D Converter 1 Polling by Software ...

Page 294: ... Read ADRR data Perform A D conversion Figure 12 5 Flow Chart of Procedure for Using A D Converter 2 Interrupts Used 12 6 Application Notes Data in the A D result register ADRR should be read only when the A D start flag ADSF in the A D start register ADSR is cleared to 0 Changing the digital input signal at an adjacent pin during A D conversion may adversely affect conversion accuracy ...

Page 295: ...nversion periods A conversion period of 32 768 ø with a minimum transition width of 2 ø or a conversion period of 16 384 ø with a minimum transition width of 1 ø can be selected Pulse division method to reduce ripple 13 1 2 Block Diagram Figure 13 1 shows a block diagram of the 14 bit PWM Internal data bus PWDRL PWDRU PWCR PWM waveform generator ø 2 ø 4 Legend PWDRL PWDRU PWCR PWM data register L ...

Page 296: ...ter Name Abbrev R W Initial Value Address PWM control register PWCR W H FE H FFA4 PWM data register U PWDRU W H C0 H FFA5 PWM data register L PWDRL W H 00 H FFA6 13 2 Register Descriptions 13 2 1 PWM Control Register PWCR Bit 7 6 5 4 3 2 1 0 PWCR0 Initial value 1 1 1 1 1 1 1 0 Read Write W PWCR is an 8 bit write only register that selects the input clock Upon reset PWCR is initialized to H FE Bits...

Page 297: ... W W Bit 7 6 5 4 3 2 1 0 PWDRL PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W PWDRU and PWDRL together comprise a 14 bit write only register with PWDRU as the upper 6 bits and PWDRL as the lower 8 bits The value written to PWDRU and PWDRL corresponds to the total high level width of one PWM waveform cycle When 14 bit data is written...

Page 298: ...consists of 64 pulses the total high level width TH during this conversion period corresponds to the data in PWDRU and PWDRL TH PWDRU PWDRL data value 64 tø 2 Here tø is the PWM input clock cycle either 2 ø when PWCR0 0 or 4 ø when PWCR0 1 Example To set a conversion period of 8 192 µs the following settings are made When PWCR0 is cleared to 0 one conversion period is 16 384 ø and therefore ø 2 MH...

Page 299: ...y voltage VTref 0 3 to VCC 0 3 V 1 Programming voltage VPP 0 3 to 13 0 V 1 Input voltage Ports other than port B Vin 0 3 to VCC 0 3 V 1 Port B AVin 0 3 to AVCC 0 3 V 1 Operating temperature Topr 20 to 75 C 1 Storage temperature Tstg 55 to 125 C 1 Note 1 Permanent damage may occur to the chip if maximum ratings are exceeded Normal operation should be under the conditions specified in Electrical Cha...

Page 300: ...aded region in the figures below Note Caution is required during development since the guaranteed operating ranges of the chip and development tools are different Power Supply Voltage vs Oscillator Frequency Range 10 0 2 7 4 0 5 5 V V CC f MHz OSC 32 768 2 7 4 0 5 5 V V CC fw kHz Active mode high and medium speeds Sleep mode All operating modes 5 0 2 0 ...

Page 301: ...gh speed Sleep mode except CPU Subactive mode Subsleep mode except CPU Watch mode except CPU Active mode medium speed 8 192 4 096 2 5 0 5 500 0 312 5 62 5 Analog Power Supply Voltage vs A D Converter Operating Range 2 7 4 0 5 5 AV V CC ø MHz 2 7 4 0 5 5 AV V CC ø kHz 625 0 312 5 Active high speed mode Sleep mode Active medium speed mode 500 0 5 0 2 5 0 5 62 5 ...

Page 302: ...dition Note Input high voltage VIH RES WKP0 to WKP7 IRQ0 to IRQ4 TMIF TMIG TMCIY SCK1 SCK3 ADTRG 0 8 VCC VCC 0 3 V SI1 RXD 0 7 VCC VCC 0 3 V OSC1 VCC 0 5 VCC 0 3 V P10 to P17 P20 to P27 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PE2 to PE3 0 7 VCC VCC 0 3 V PB4 to PB7 0 7 VCC AVCC 0 3 V Input low voltage VIL RES WKP0 to WKP7 IRQ0 to IRQ4 TMIF TMIG TMCIY SCK1 SCK3 ADTRG 0 3 0...

Page 303: ... to P87 P90 to P97 PA0 to PA3 PB4 to PB7 PE2 to PE3 0 3 0 3 VCC V Output high voltage VOH P10 to P17 P20 to P26 P50 to P57 VCC 1 0 V VCC 4 0 V to 5 5 V IOH 1 0 mA P60 to P67 P70 to P77 P80 to P87 VCC 0 5 VCC 4 0 V to 5 5 V IOH 0 5 mA P90 to P97 PA0 to PA3 PE2 to PE3 VCC 0 5 IOH 0 1 mA Output low voltage VOL P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PE2 to PE3 0 5 V IOL 0 4 ...

Page 304: ...rrent OSC1 P10 to P17 P20 to P26 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PE2 to PE3 1 µA VIN 0 5 V to VCC 0 5 V PB4 to PB7 1 VIN 0 5 V to AVCC 0 5 V Pull up MOS IP P10 to P17 P20 to P26 50 300 µA VCC 5 V VIN 0 V current P50 to P57 P60 to P67 35 VCC 2 7 V VIN 0 V Reference value Input capaci tance CIN All input pins except power supply pins 15 pF f 1 MHz VIN 0 V Ta 25 C RE...

Page 305: ... 10 35 µA VCC 2 7 V 32 kHz crystal oscillator øSUB øw 2 4 5 Watch mode current dissipation IWATCH VCC 6 µA VCC 2 7 V 32 kHz crystal oscillator 4 5 Standby mode current dissipation ISTBY VCC 5 µA 32 kHz crystal oscillator not used 4 5 RAM data retaining voltage VRAM VCC 2 V Notes 4 Pin states during current measurement are shown below Mode Other Pins Internal State Oscillator Pins Active mode high ...

Page 306: ... pin IOL Output pins except in ports 1 and 2 2 mA VCC 4 0 V to 5 5 V Ports 1 and 2 10 VCC 4 0 V to 5 5 V All output pins 0 5 Allowable output low current total ΣIOL Output pins except in ports 1 and 2 40 mA VCC 4 0 V to 5 5 V Ports 1 and 2 80 VCC 4 0 V to 5 5 V All output pins 20 Allowable output high IOH All output pins 2 mA VCC 4 0 V to 5 5 V current per pin 0 2 Allowable output high Σ IOH All o...

Page 307: ...2 32 768 kHz Watch clock cycle time øW tW X1 X2 30 5 µs Subclock øSUB cycle time tsubcyc 2 8 tW 2 Instruction cycle time 2 tcyc tsubcyc Oscillation stabiliza tion time trc OSC1 OSC2 40 ms VCC 4 0 V to 5 5 V crystal oscillator 60 Oscillation stabilization time trc X1 X2 2 s External clock high tCPH OSC1 40 ns VCC 4 0 V to 5 5 V Figure 14 1 width 80 External clock low tCPL OSC1 40 ns VCC 4 0 V to 5 ...

Page 308: ...g subactive mode unless otherwise specified Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure Input pin high width tIH IRQ0 to IRQ4 WKP0 to WKP7 ADTRG TMIF TMIG TMCIY 2 tcyc tsubcyc Figure 14 3 Input pin low width tIL IRQ0 to IRQ4 WKP0 to WKP7 ADTRG TMIF TMIG TMCIY 2 tcyc tsubcyc Figure 14 3 ...

Page 309: ...0 ns VCC 4 0 V to 5 5 V Figure 14 4 delay time 350 Serial input data tSIS SI1 200 ns VCC 4 0 V to 5 5 V Figure 14 4 setup time 400 Serial input data tSIH SI1 200 ns VCC 4 0 V to 5 5 V Figure 14 4 hold time 400 Table 14 5 Serial Interface Timing SCI3 VCC 2 7 V to 5 5 V AVCC 2 7 V to 5 5 V VSS AVSS 0 0 V Ta 20 to 75 C including subactive mode unless otherwise specified Item Symbol Min Typ Max Unit T...

Page 310: ...y current AIOPE AVCC 1 5 mA AVCC 5 0 V AISTOP1 AVCC 150 µA 2 Reference value AISTOP2 AVCC 5 µA 3 Analog input capacitance CAIN AN4 to AN7 30 pF Allowable signal source impedance RAIN 10 kΩ Resolution 8 bit Non linearity error 2 0 LSB Quantization error 0 5 LSB Absolute accuracy 2 5 LSB Conversion time 12 4 248 µs AVCC 4 5 V to 5 5 V 24 8 248 µs Notes 1 Set AVCC VCC when the A D converter is not us...

Page 311: ...on Notes Reference level supply voltage VTref VTref 2 7 VCC 0 3 V DTMF output voltage row VOR TONED 675 890 mVrms VTref GND 2 7 V RL 100 kΩ Figure 14 8 1 DTMF output voltage column VOC TONED 700 935 mVrms VTref GND 2 7 V RL 100 kΩ Figure 14 8 1 DTMF output distortion DISDT TONED 3 7 VTref GND 2 7 V RL 100 kΩ Figure 14 8 DTMF output level dBCR TONED 2 5 dB VTref GND 2 7 V RL 100 kΩ Figure 14 8 Note...

Page 312: ... 14 6 show operation timings tOSC VIH VIL tCPH tCPL tCPr OSC1 tCPf Figure 14 1 System Clock Input Timing RES VIL tREL Figure 14 2 RES Low Width Timing VIH VIL tIL IRQ to IRQ WKP to WKP ADTRG TMIF TMIG TMCIY tIH 0 4 0 7 Figure 14 3 Input Timing ...

Page 313: ... OL tSIS tSIH SCK SO SI 1 1 1 tSCKr V or V IH OH V or V IL OL Notes Output timing reference levels Output high Output low Refer to figure 14 7 for output load condition V 2 0 V V 0 8 V OH OL Figure 14 4 Serial Interface 1 Input Output Timing ...

Page 314: ... TXD transmit data 3 tScyc tTXD tRXH tRXS V or V IH OH V or V IL OL VOH VOL Notes Output timing reference levels Output high Output low Refer to figure 14 7 for output load condition V 2 0 V V 0 8 V OH OL Figure 14 6 Input Output Timing of Serial Interface 3 in Synchronous Mode ...

Page 315: ...313 14 4 Output Load Circuits Figure 14 7 shows an output load condition VCC 2 4 kΩ 12 kΩ 30 pF Output pin Figure 14 7 Output Load Condition RL 100 kΩ TONED GND Figure 14 8 TONED Load Circuit ...

Page 316: ...overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer xx 3 8 16 Immediate data 3 8 or 16 bits d 8 16 Displacement 8 or 16 bits aa 8 16 Absolute address 8 or 16 bits Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move Logical complement Condition Code Notation Symbol Modified according to the instruction result Undefined value not g...

Page 317: ... xx 16 Rd MOV W Rs Rd MOV W Rs Rd MOV W d 16 Rs Rd MOV W Rs Rd MOV W aa 16 Rd MOV W Rs Rd MOV W Rs d 16 Rd MOV W Rs Rd MOV W Rs aa 16 POP Rd xx 8 Rd8 Rs8 Rd8 Rs16 Rd8 d 16 Rs16 Rd8 Rs16 Rd8 Rs16 1 Rs16 aa 8 Rd8 aa 16 Rd8 Rs8 Rd16 Rs8 d 16 Rd16 Rd16 1 Rd16 Rs8 Rd16 Rs8 aa 8 Rs8 aa 16 xx 16 Rd Rs16 Rd16 Rs16 Rd16 d 16 Rs16 Rd16 Rs16 Rd16 Rs16 2 Rs16 aa 16 Rd16 Rs16 Rd16 Rs16 d 16 Rd16 Rd16 2 Rd16 Rs...

Page 318: ...s Rd SUBS W 1 Rd SUBS W 2 Rd DEC B Rd DAS B Rd NEG B Rd CMP B xx 8 Rd CMP B Rs Rd CMP W Rs Rd MULXU B Rs Rd SP 2 SP Rs16 SP Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 Rs16 Rd16 Rd8 xx 8 C Rd8 Rd8 Rs8 C Rd8 Rd16 1 Rd16 Rd16 2 Rd16 Rd8 1 Rd8 Rd8 decimal adjust Rd8 Rd8 Rs8 Rd8 Rd16 Rs16 Rd16 Rd8 xx 8 C Rd8 Rd8 Rs8 C Rd8 Rd16 1 Rd16 Rd16 2 Rd16 Rd8 1 Rd8 Rd8 decimal adjust Rd8 0 Rd Rd Rd8 xx 8 Rd8 Rs8 Rd16 Rs16 Rd...

Page 319: ...Rd OR B Rs Rd XOR B xx 8 Rd XOR B Rs Rd NOT B Rd SHAL B Rd SHAR B Rd SHLL B Rd SHLR B Rd ROTXL B Rd ROTXR B Rd ROTL B Rd ROTR B Rd Rd16 Rs8 Rd16 RdH remainder RdL quotient Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd Rd B B B B B B B B B B B B B B B B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 b7 b0 0 C b7 b0 0 ...

Page 320: ... aa 8 BTST xx 3 Rd BTST xx 3 Rd BTST xx 3 aa 8 BTST Rn Rd BTST Rn Rd BTST Rn aa 8 xx 3 of Rd8 1 xx 3 of Rd16 1 xx 3 of aa 8 1 Rn8 of Rd8 1 Rn8 of Rd16 1 Rn8 of aa 8 1 xx 3 of Rd8 0 xx 3 of Rd16 0 xx 3 of aa 8 0 Rn8 of Rd8 0 Rn8 of Rd16 0 Rn8 of aa 8 0 xx 3 of Rd8 xx 3 of Rd8 xx 3 of Rd16 xx 3 of Rd16 xx 3 of aa 8 xx 3 of aa 8 Rn8 of Rd8 Rn8 of Rd8 Rn8 of Rd16 Rn8 of Rd16 Rn8 of aa 8 Rn8 of aa 8 xx...

Page 321: ...Rd BIOR xx 3 Rd BIOR xx 3 aa 8 BXOR xx 3 Rd BXOR xx 3 Rd BXOR xx 3 aa 8 BIXOR xx 3 Rd xx 3 of Rd8 C xx 3 of Rd16 C xx 3 of aa 8 C xx 3 of Rd8 C xx 3 of Rd16 C xx 3 of aa 8 C C xx 3 of Rd8 C xx 3 of Rd16 C xx 3 of aa 8 C xx 3 of Rd8 C xx 3 of Rd16 C xx 3 of aa 8 C xx 3 of Rd8 C C xx 3 of Rd16 C C xx 3 of aa 8 C C xx 3 of Rd8 C C xx 3 of Rd16 C C xx 3 of aa 8 C C xx 3 of Rd8 C C xx 3 of Rd16 C C xx ...

Page 322: ...NE d 8 BEQ d 8 BVC d 8 BVS d 8 BPL d 8 BMI d 8 BGE d 8 BLT d 8 BGT d 8 BLE d 8 JMP Rn JMP aa 16 JMP aa 8 BSR d 8 JSR Rn JSR aa 16 C xx 3 of Rd16 C C xx 3 of aa 8 C PC PC d 8 PC PC 2 If condition is true then PC PC d 8 else next B B 4 2 2 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 8 6 6 8 C Z 0 C Z 1 C 0 C 1 Z 0 Z 1 V 0 V 1 N 0 N 1 N V 0 N V 1 Z N V 0 Z N V 1 ...

Page 323: ...L 0 else next B B B B B B 2 8 8 10 2 2 2 2 2 2 2 2 4 2 2 2 2 2 2 2 2 2 2 4 Notes 1 Set to 1 when there is a carry or borrow from bit 11 otherwise cleared to 0 2 If the result is zero the previous value of the flag is retained otherwise the flag is cleared to 0 3 Set to 1 if decimal adjustment produces a carry otherwise retains value prior to arithmetic operation 4 The number of states required for...

Page 324: ...323 Instruction when first bit of byte 2 bit 7 of first instruction word is 0 Instruction when first bit of byte 2 bit 7 of first instruction word is 1 ...

Page 325: ...BLS BTST ROTXR ROTR ORC OR BCC RTS XORC XOR BCS BSR BOR BIOR BXOR BIXOR BAND BIAND ANDC AND BNE RTE LDC BEQ NOT NEG BLD BILD BST BIST ADD SUB BVC BVS MOV INC DEC BPL JMP ADDS SUBS BMI EEPMOV MOV CMP BGE BLT ADDX SUBX BGT JSR DAA DAS BLE MOV ADD ADDX CMP SUBX OR XOR AND MOV MOV Note Bit manipulation instructions The PUSH and POP instructions are identical in machine language to MOV instructions ...

Page 326: ...ion status The total number of states required for the execution of an instruction can be calculated by using the following equation Execution states I SI J SJ K SK L SL M SM N SN Examples When instruction is fetched from on chip ROM and an on chip RAM is accessed 1 BSET 0 FF00 From table A 4 I L 2 J K M N 0 From table A 3 SI 2 SL 2 Number of states required for execution 2 2 2 2 8 When instructio...

Page 327: ...nstruction Cycle On Chip Memory On Chip Peripheral Module Instruction fetch SI 2 Branch address read SJ Stack operation SK Byte data access SL 2 or 3 Word data access SM Internal operation SN 1 1 Note Depends on which on chip module is accessed See 2 9 1 Notes on Data Access for details ...

Page 328: ...S ADDS W 1 Rd 1 ADDS W 2 Rd 1 ADDX ADDX B xx 8 Rd 1 ADDX B Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 Rd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS d 8 BLO d 8 2 BNE d 8 2 BEQ d 8 2 BVC d 8 2 BVS d 8 2 BPL d 8 2 BMI d 8 2 BGE d 8 2 BLT d 8 2 BGT d 8 2 BLE d 8 2 BCLR BCLR xx 3 Rd 1 BCLR xx ...

Page 329: ... 3 Rd 1 BILD xx 3 Rd 2 1 BILD xx 3 aa 8 2 1 BIOR BIOR xx 3 Rd 1 BIOR xx 3 Rd 2 1 BIOR xx 3 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 Rd 2 2 BIST xx 3 aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 Rd 2 1 BIXOR xx 3 aa 8 2 1 BLD BLD xx 3 Rd 1 BLD xx 3 Rd 2 1 BLD xx 3 aa 8 2 1 BNOT BNOT xx 3 Rd 1 BNOT xx 3 Rd 2 2 BNOT xx 3 aa 8 2 2 BNOT Rn Rd 1 BNOT Rn Rd 2 2 BNOT Rn aa 8 2 2 BOR BOR xx 3 Rd 1 BOR xx 3 Rd 2...

Page 330: ... BTST xx 3 Rd 2 1 BTST xx 3 aa 82 1 BTST Rn Rd 1 BTST Rn Rd 2 1 BTST Rn aa 8 2 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 Rd 2 1 BXOR xx 3 aa 8 2 1 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W Rs Rd 1 DAA DAA B Rd 1 DAS DAS B Rd 1 DEC DEC B Rd 1 DIVXU DIVXU B Rs Rd 1 12 EEPMOV EEPMOV 2 2n 2 1 INC INC B Rd 1 JMP JMP Rn 2 JMP aa 16 2 2 JMP aa 8 2 1 2 JSR JSR Rn 2 1 JSR aa 16 2 1 2 JSR aa 8 2 1 1 LDC LDC xx 8 CCR 1 ...

Page 331: ...B Rs Rd 1 1 2 MOV B aa 8 Rd 1 1 MOV B aa 16 Rd 2 1 MOV B Rs Rd 1 1 MOV B Rs d 16 Rd 2 1 MOV B Rs Rd 1 1 2 MOV B Rs aa 8 1 1 MOV B Rs aa 16 2 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W Rs Rd 1 1 MOV W d 16 Rs Rd 2 1 MOV W Rs Rd 1 1 2 MOV W aa 16 Rd 2 1 MOV W Rs Rd 1 1 MOV W Rs d 16 Rd 2 1 MOV W Rs Rd 1 1 2 MOV W Rs aa 16 2 1 MULXU MULXU B Rs Rd 1 12 NEG NEG B Rd 1 NOP NOP 1 NOT NOT B Rd 1 OR OR B xx 8 ...

Page 332: ...ternal Operation N ROTXL ROTXL B Rd 1 ROTXR ROTXR B Rd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL B Rd 1 SHAR SHAR B Rd 1 SHLL SHLL B Rd 1 SHLR SHLR B Rd 1 SLEEP SLEEP 1 STC STC CCR Rd 1 SUB SUB B Rs Rd 1 SUB W Rs Rd 1 SUBS SUBS W 1 Rd 1 SUBS W 2 Rd 1 POP POP Rd 1 1 2 PUSH PUSH Rs 1 1 2 SUBX SUBX B xx 8 Rd 1 SUBX B Rs Rd 1 XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XORC XORC xx 8 CCR 1 ...

Page 333: ...H 9E PUCR5 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 H 9F PUCR6 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 H A0 SCR1 SNC1 SNC0 CKS3 CKS2 CKS1 CKS0 SCI1 H A1 SCSR1 SOL ORER STF H A2 SDRU SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0 H A3 SDRL SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0 H A4 PWCR PWCR0 14 bit H A5 PWDRU PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWM H...

Page 334: ...W2 TCW1 TCW0 timer H B6 TCRF TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Timer F H B7 TCSRF OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL H B8 TCFH TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0 H B9 TCFL TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL2 TCFL1 TCFL0 H BA OCRFH OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 H BB OCRFL OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 H BC TMG OVF...

Page 335: ... O ports H D9 PDR6 P67 P66 P65 P64 P63 P62 P61 P60 H DA PDR7 P77 P76 P75 P74 P73 P72 P71 P70 H DB PDR8 P87 P86 P85 P84 P83 P82 P81 P80 H DC PDR9 P97 P96 P95 P94 P93 P92 P91 P90 H DD PDRA PA3 PA2 PA1 PA0 H DE PDRB PB7 PB6 PB5 PB4 H DF H E0 H E1 H E2 H E3 PCRE PCRE3 PCRE2 I O ports H E4 PCR1 PCR17 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 H E5 PCR2 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 H E...

Page 336: ...1 SA0 control H F2 IEGR IEG4 IEG3 IEG2 IEG1 IEG0 H F3 IENR1 IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 H F4 IENR2 IENDT IENAD IENTG IENTFH IENTFL IENTY H F5 H F6 IRR1 IRRTA IRRS1 IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 System H F7 IRR2 IRRDT IRRAD IRRTG IRRTFH IRRTFL IRRTY IRRTYC control H F8 H F9 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 System control H FA H FB H FC H FD H FE H FF ...

Page 337: ...ad and write R W R W Possible types of access Bit Initial value Read Write 7 DA0E 0 R W 6 MTEN 0 R W 5 DIR 0 R W 3 FR1 0 0 FT0 0 R W 2 FR0 0 R W 1 FT1 0 R W 4 1 Fine tuning counter clock source select FT0 0 1 0 1 Clock Division Ratio 1tOSC counter clock fOSC 2tOSC counter clock fOSC 2 4tOSC counter clock fOSC 4 8tOSC counter clock fOSC 8 FT1 0 0 1 1 Frame counter clock source select FR0 0 1 0 1 Cl...

Page 338: ...OFL pin function switch 0 Functions as P1 I O pin 1 Functions as TMOFL output pin P1 TMOFH pin function switch 0 Functions as P1 I O pin 1 Functions as TMOFH output pin P1 IRQ pin function switch P1 IRQ pin function switch 1 0 Functions as P1 I O pin 1 Functions as IRQ input pin 0 Functions as P1 I O pin 1 Functions as IRQ input pin P1 IRQ TMIF pin function switch 1 0 Functions as P1 I O pin 1 Fun...

Page 339: ... Functions as SI input pin TMIG noise canceller select 0 Noise canceller function not selected 1 Noise canceller function selected P2 SO pin PMOS control P2 IRQ ADTRG pin function switch 1 0 CMOS output 1 NMOS open drain output 0 Functions as P2 I O pin 1 Functions as IRQ ADTRG input pin 1 2 3 0 1 0 1 4 4 1 P2 SO pin function switch 1 0 Functions as P2 I O pin 1 Functions as SO output pin 3 3 1 1 ...

Page 340: ...WKP 0 R W 2 WKP 0 R W 1 WKP 0 R W 0 Functions as P5 I O pin 1 Functions as WKP input pin n n 7 6 5 4 3 2 1 0 P5 WKP pin function switch n n n 7 to 0 PUCR1 Port pull up control register 1 H 9C I O ports Bit Initial value Read Write 7 PUCR17 0 R W 6 PUCR16 0 R W 5 PUCR15 0 R W 4 PUCR14 0 R W 3 PUCR13 0 R W 0 PUCR10 0 R W 2 PUCR12 0 R W 1 PUCR11 0 R W PUCR2 Port pull up control register 2 H 9D I O po...

Page 341: ...PUCR56 0 R W 5 PUCR55 0 R W 4 PUCR54 0 R W 3 PUCR53 0 R W 0 PUCR50 0 R W 2 PUCR52 0 R W 1 PUCR51 0 R W PUCR6 Port pull up control register 6 H 9F I O ports Bit Initial value Read Write 7 PUCR67 0 R W 6 PUCR66 0 R W 5 PUCR65 0 R W 4 PUCR64 0 R W 3 PUCR63 0 R W 0 PUCR60 0 R W 2 PUCR62 0 R W 1 PUCR61 0 R W ...

Page 342: ... pin 1 Clock source is external clock and pin SCK is input pin 0 8 bit synchronous mode 16 bit synchronous mode 0 1 1 Continuous clock output mode Reserved 0 1 Clock select Bit 2 CKS2 CKS1 CKS0 Bit 1 Bit 0 0 ø 1024 ø 256 1 1 0 ø 64 ø 32 1 ø 16 1 0 0 1 ø 8 0 0 ø 4 1 0 1 ø 2 ø 5 MHz 204 8 µs 51 2 µs 12 8 µs 6 4 µs 3 2 µs 1 6 µs 0 8 µs ø 2 5 MHz 409 6 µs 102 4 µs 25 6 µs 12 8 µs 6 4 µs 3 2 µs 1 6 µs ...

Page 343: ...put level is high SO1 pin output level changes to high Note Only a write of 0 for flag clearing is possible 0 Clearing condition After reading 1 cleared by writing 0 1 Setting condition Set if a clock pulse is input after transfer is complete when an external clock is used SDRU Serial data register U H A2 SCI1 Bit Initial value Read Write 7 SDRU7 Undefined R W 6 SDRU6 Undefined R W 5 SDRU5 Undefin...

Page 344: ...er 8 bits of data PWCR PWM control register H A4 14 bit PWM Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 PWCR0 0 W 2 1 1 1 Clock select 1 0 Input clock ø 2 tø 2 ø 1 conversion cycle 16 384ø minimum transition width 1 ø 1 Input clock ø 4 tø 4 ø 1 conversion cycle 32 768ø minimum transition width 2 ø Note tø PWM input clock cycle PWDRU PWM data register U H A5 14 bit PWM Bit Initial value Read...

Page 345: ... PM 0 R W 3 STOP 0 R W 0 CKS0 0 R W 2 MP 0 R W 1 CKS1 0 R W Parity enable 0 Parity bit adding and checking disabled 1 Parity bit adding and checking enabled Clock select 0 1 0 0 1 1 0 1 ø clock ø 4 clock ø 16 clock ø 64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 ...

Page 346: ...345 BRR Bit rate register H A9 SCI3 Bit Initial value Read Write 7 BRR7 1 R W 6 BRR6 1 R W 5 BRR5 1 R W 4 BRR4 1 R W 3 BRR3 1 R W 0 BRR0 1 R W 2 BRR2 1 R W 1 BRR1 1 R W ...

Page 347: ...ock I O port Synchronous Internal clock Serial clock output 1 Asynchronous Internal clock Clock output Synchronous Reserved 1 0 Asynchronous External clock Clock output Synchronous External clock Serial clock input 1 Asynchronous Reserved Synchronous Reserved Clearing condition Multiprocessor bit receives a data value of 1 Transmit enable 0 Transmit operation disabled TXD is the transmit data pin ...

Page 348: ...47 TDR Transmit data register H AB SCI3 Bit Initial value Read Write 7 TDR7 1 R W 6 TDR6 1 R W 5 TDR5 1 R W 4 TDR4 1 R W 3 TDR3 1 R W 0 TDR0 1 R W 2 TDR2 1 R W 1 TDR1 1 R W Data to be transferred to TSR ...

Page 349: ... setting in the serial mode register SMR 0 Indicates that data receiving is in progress or has been completed Framing error Clearing conditions After reading FER 1 cleared by writing 0 1 Indicates that a framing error occurred in data receiving Setting conditions The stop bit at the end of receive data is checked and found to be 0 0 Indicates that data receiving is in progress or has been complete...

Page 350: ...0 0 R W 2 TMA2 0 R W 1 TMA1 0 R W Internal clock select TMA3 TMA2 0 PSS PSS PSS PSS 0 4 1 Clock output select 0 ø 32 ø 16 TMA1 0 1 TMA0 0 0 1 1 PSS PSS PSS PSS 1 0 1 0 0 1 1 1 PSW PSW PSW PSW 0 0 1 0 0 1 1 PSW and TCA are reset 1 0 1 0 0 1 1 Prescaler and Divider Ratio or Overflow Period ø 8192 ø 4096 ø 2048 ø 512 ø 256 ø 128 ø 32 ø 8 1 s 0 5 s 0 25 s 0 03125 s Interval timer Time base Function 0 ...

Page 351: ...350 TCA Timer counter A H B1 Timer A Bit Initial value Read Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 0 TCA0 0 R 2 TCA2 0 R 1 TCA1 0 R Count value ...

Page 352: ... Hz R2 852 Hz R3 941 Hz R4 Row output enable 0 1 DTMF row signal output is disabled high impedance DTMF row signal output is enabled RWF1 0 1 DTMF column signal output frequency 1 and 0 CLF0 0 1 0 1 DTMF column signal output frequency 1209 Hz C1 1336 Hz C2 1447 Hz C3 1633 Hz C4 CLF1 0 1 Column output enable 0 1 DTMF column signal output is disabled high impedance DTMF column signal output is enabl...

Page 353: ... DTL2 0 R W 1 DTL1 0 R W OSC clock division ratio 4 to 0 DTL3 0 0 0 0 0 1 1 1 Division Ratio Illegal setting Illegal setting Illegal setting 3 4 25 Illegal setting Illegal setting DTL4 0 0 0 0 0 1 1 1 DTL2 0 0 0 0 1 0 0 1 DTL1 0 0 1 1 0 0 1 DTL0 0 1 0 1 0 1 OSC Clock Frequency 1 2 MHz 1 6 MHz 10 MHz initial value Note Don t care ...

Page 354: ...o bit 0 enabled 1 Writing to bit 0 disabled Watchdog timer on 1 0 Watchdog timer operation disabled 1 Watchdog timer operation enabled Bit 2 write disable 1 0 Writing to bit 2 enabled 1 Writing to bit 2 disabled Timer control status register W write enable 1 0 Writing to bit 2 and bit 0 disabled 1 Writing to bit 2 and bit 0 enabled Bit 4 write disable 1 0 Writing to bit 4 enabled 1 Writing to bit ...

Page 355: ...H1 0 W 3 TOLL 0 W 0 CKSL0 0 W 2 CKSL2 0 W 1 CKSL1 0 W 4 CKSH0 0 W Toggle output level H Clock select L 0 1 0 0 1 1 0 1 Internal clock Internal clock Internal clock Internal clock ø 32 ø 16 ø 4 Note Don t care External event TMIF Rising or falling edge ø 2 Toggle output level L 0 Low level 1 High level Clock select H 0 1 0 0 1 1 0 1 Internal clock Internal clock Internal clock Internal clock ø 32 ø...

Page 356: ...o CMFH 1 Setting condition When the TCFH value matches the OCRFH value 0 TCFH overflow interrupt disabled 1 TCFH overflow interrupt enabled Counter clear H 0 16 bit mode 8 bit mode 1 TCF clearing by compare match disabled TCFH clearing by compare match disabled 16 bit mode 8 bit mode TCF clearing by compare match enabled TCFH clearing by compare match enabled Timer overflow flag L 0 Clearing condi...

Page 357: ...0 R W 5 TCFL5 0 R W 4 TCFL4 0 R W 3 TCFL3 0 R W 0 TCFL0 0 R W 2 TCFL2 0 R W 1 TCFL1 0 R W Count value OCRFH Output compare register FH H BA Timer F Bit Initial value Read Write 7 OCRFH7 1 R W 6 OCRFH6 1 R W 5 OCRFH5 1 R W 4 OCRFH4 1 R W 3 OCRFH3 1 R W 0 OCRFH0 1 R W 2 OCRFH2 1 R W 1 OCRFH1 1 R W OCRFL Output compare register FL H BB Timer F Bit Initial value Read Write 7 OCRFL7 1 R W 6 OCRFL6 1 R ...

Page 358: ...FL 1 cleared by writing 0 to OVFL 1 Setting condition When the value of TCG overflows from H FF to H 00 0 TCG overflow interrupt disabled 1 TCG overflow interrupt enabled Input capture interrupt edge select 0 Interrupts are requested at the rising edge of the input capture signal 1 Interrupts are requested at the falling edge of the input capture signal Clock select 0 Internal clock Internal clock...

Page 359: ... ICRGF7 0 R 6 ICRGF6 0 R 5 ICRGF5 0 R 4 ICRGF4 0 R 3 ICRGF3 0 R 0 ICRGF0 0 R 2 ICRGF2 0 R 1 ICRGF1 0 R ICRGR Input capture register GR H BE Timer G Bit Initial value Read Write 7 ICRGR7 0 R 6 ICRGR6 0 R 5 ICRGR5 0 R 4 ICRGR4 0 R 3 ICRGR3 0 R 0 ICRGR0 0 R 2 ICRGR2 0 R 1 ICRGR1 0 R ...

Page 360: ...ernal trigger at pin ADTRG 5 CKS1 0 R W 4 AN5 AN6 AN7 Reserved 1 Reserved Clock select Reserved Bit 5 0 Conversion Period CKS1 124 ø 1 ø 2 MHz 62 µs ø 5 MHz 24 8 µs Conversion Time Note Operation is not guaranteed if the conversion time is less than 12 4 µs Set bits 5 and 7 for a value of at least 12 4 µs Don t care Bit 7 0 CKS 0 62 ø 0 31 µs 12 4 µs 1 31 ø 1 15 5 µs 1 ADRR A D result register H C...

Page 361: ... Timer mode register Y H CD Timer Y Bit Initial value Read Write 7 TMY7 0 R W 6 1 5 1 4 1 3 1 0 TMY0 0 R W 2 TMY2 0 R W 1 TMY1 0 R W Count select 1 0 Internal clock ø 8192 1 Internal clock ø 2048 0 0 0 0 0 Internal clock ø 512 1 0 1 Internal clock ø 256 1 0 0 Internal clock ø 64 0 1 1 Internal clock ø 16 0 1 0 Internal clock ø 4 1 1 1 External event TMCIY count on rising edge falling edge 1 1 Auto...

Page 362: ...TLYH6 0 W 5 TLYH5 0 W 4 TLYH4 0 W 3 TLYH3 0 W 0 TLYH0 0 W 2 TLYH2 0 W 1 TLYH1 0 W Reload value setting TCYL Timer counter YL H CF Timer Y Bit Initial value Read Write 7 TLYL7 0 R 6 TLYL6 0 R 5 TLYL5 0 R 4 TLYL4 0 R 3 TLYL3 0 R 0 TLYL0 0 R 2 TLYL2 0 R 1 TLYL1 0 R Count value TLYL Timer load register YL H CF Timer Y Bit Initial value Read Write 7 TLYL7 0 W 6 TLYL6 0 W 5 TLYL5 0 W 4 TLYL4 0 W 3 TLYL3...

Page 363: ...ata register 2 H D5 I O ports Bit Initial value Read Write 7 P2 0 R W 6 P2 0 R W 5 P2 0 R W 4 P2 0 R W 3 P2 0 R W 0 P2 0 R W 2 P2 0 R W 1 P2 0 R W 7 6 5 4 3 0 2 1 PDR5 Port data register 5 H D8 I O ports Bit Initial value Read Write 7 P5 0 R W 6 P5 0 R W 5 P5 0 R W 4 P5 0 R W 3 P5 0 R W 0 P5 0 R W 2 P5 0 R W 1 P5 0 R W 3 0 2 1 4 5 6 7 PDR6 Port data register 6 H D9 I O ports Bit Initial value Read...

Page 364: ...R W 3 P8 0 R W 0 P8 0 R W 2 P8 0 R W 1 P8 0 R W 3 0 2 1 4 5 6 7 PDR9 Port data register 9 H DC I O ports Bit Initial value Read Write 7 P9 0 R W 6 P9 0 R W 5 P9 0 R W 4 P9 0 R W 3 P9 0 R W 0 P9 0 R W 2 P9 0 R W 1 P9 0 R W 3 0 2 1 4 5 6 7 PDRA Port data register A H DD I O ports Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 PA 0 R W 0 PA 0 R W 2 PA 0 R W 1 PA 0 R W 3 0 2 1 PDRB Port data register ...

Page 365: ...6 PCR1 0 W 5 PCR1 0 W 4 PCR1 0 W 3 PCR1 0 W 0 PCR1 0 W 2 PCR1 0 W 1 PCR1 0 W Port 1 input output select 0 Input pin 1 Output pin 7 6 5 4 3 0 2 1 PCR2 Port control register 2 H E5 I O ports Bit Initial value Read Write Note As P27 is an input only pin it becomes a high impedance output when PCR27 is set to 1 7 PCR2 0 W 6 PCR2 0 W 5 PCR2 0 W 4 PCR2 0 W 3 PCR2 0 W 0 PCR2 0 W 2 PCR2 0 W 1 PCR2 0 W Por...

Page 366: ...ontrol register 6 H E9 I O ports Bit Initial value Read Write 7 PCR6 0 W 6 PCR6 0 W 5 PCR6 0 W 4 PCR6 0 W 3 PCR6 0 W 0 PCR6 0 W 2 PCR6 0 W 1 PCR6 0 W Port 6 input output select 0 Input pin 1 Output pin 7 6 5 4 3 0 2 1 PCR7 Port control register 7 H EA I O ports Bit Initial value Read Write 7 PCR7 0 W 6 PCR7 0 W 5 PCR7 0 W 4 PCR7 0 W 3 PCR7 0 W 0 PCR7 0 W 2 PCR7 0 W 1 PCR7 0 W Port 7 input output s...

Page 367: ... 0 2 1 PCR9 Port control register 9 H EC I O ports Bit Initial value Read Write 7 PCR9 0 W 6 PCR9 0 W 5 PCR9 0 W 4 PCR9 0 W 3 PCR9 0 W 0 PCR9 0 W 2 PCR9 0 W 1 PCR9 0 W Port 9 input output select 0 Input pin 1 Output pin 7 6 5 4 3 0 2 1 PCRA Port control register A H ED I O ports Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 PCRA 0 W 0 PCRA 0 W 2 PCRA 0 W 1 PCRA 0 W 3 0 2 1 Port A input output sel...

Page 368: ...states Wait time 16 384 states 0 0 1 Wait time 32 768 states Wait time 65 536 states 1 0 1 1 Wait time 131 072 states Low speed on flag 0 The CPU operates on the system clock ø 1 The CPU operates on the subclock ø SUB When a SLEEP instruction is executed in subactive mode a transition is made to subsleep mode When a SLEEP instruction is executed in active mode a transition is made to standby mode ...

Page 369: ...0 MSON 1 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 Subactive mode clock select 0 ø 8 ø 4 0 1 1 ø 2 W W W Noise elimination sampling frequency select 0 Sampling rate is ø 16 1 Sampling rate is ø 4 OSC OSC When a SLEEP instruction is executed in active medium speed mode a direct transition is made to active high speed mode if SSBY 0 MSON 0 and LSON 0 or to subactive mode if SSBY 1 ...

Page 370: ... 0 0 0 IRQ edge select 0 Falling edge of IRQ pin input is detected 1 Rising edge of IRQ pin input is detected 1 1 1 IRQ edge select 0 Falling edge of IRQ pin input is detected 1 Rising edge of IRQ pin input is detected 2 2 2 IRQ edge select 0 Falling edge of IRQ TMIF pin input is detected 1 Rising edge of IRQ TMIF pin input is detected 3 3 3 IRQ edge select 0 Falling edge of IRQ ADTRG pin input is...

Page 371: ...RQ interrupt enable 0 Disables interrupt requests from IRQ to IRQ 1 4 4 0 0 Enables interrupt requests from IRQ to IRQ 4 0 Wakeup interrupt enable 0 Disables interrupt requests from WKP to WKP 1 7 0 Enables interrupt requests from WKP to WKP 7 0 SCI1 interrupt enable 0 Disables SCI1 interrupts 1 Enables SCI1 interrupts Timer A interrupt enable 0 Disables timer A interrupts 1 Enables timer A interr...

Page 372: ...upt enable 0 Disables timer FL interrupts 1 Enables timer FL interrupts Timer G interrupt enable 0 Disables timer G interrupts 1 Enables timer G interrupts A D converter interrupt enable 1 0 1 0 Disables A D converter interrupt requests 1 Enables A D converter interrupt requests Direct transfer interrupt enable 1 0 Disables direct transfer interrupt requests 1 Enables direct transfer interrupt req...

Page 373: ...tting condition When the timer A counter overflows from H FF to H 00 Note Only a write of 0 for flag clearing is possible SCI1 interrupt request flag 0 Clearing condition When IRRS1 1 it is cleared by writing 0 1 Setting condition When an SCI1 transfer is completed IRQ to IRQ interrupt request flag 0 Clearing condition When IRRIn 1 it is cleared by writing 0 to IRRIn 1 Setting condition When pin I...

Page 374: ...0000 Timer G interrupt request flag 0 Clearing condition When IRRTG 1 it is cleared by writing 0 1 Setting condition When pin TMIG is set to TMIG input and the designated signal edge is detected Timer FH interrupt request flag 0 Clearing condition When IRRTFH 1 it is cleared by writing 0 1 Setting condition When counter FH matches output compare register FH in 8 bit mode or when 16 bit counter F T...

Page 375: ...5 0 R W 4 IWPF4 0 R W 3 IWPF3 0 R W 0 IWPF0 0 R W 2 IWPF2 0 R W 1 IWPF1 0 R W Note Only a write of 0 for flag clearing is possible Wakeup interrupt request flag 0 Clearing condition When IWPFn 1 it is cleared by writing 0 1 Setting condition When pin WKPn is set to interrupt input and a falling signal edge is detected n 7 to 0 ...

Page 376: ...l during reset and in standby mode PUCR17 PMR17 PDR17 PCR17 Internal data bus PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 VCC VCC IRQ3 Timer F module TMIF VSS P17 Figure C 1 a Port 1 Block Diagram Pin P17 ...

Page 377: ...ode PUCR16 PMR16 PDR16 PCR16 Internal data bus PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 VCC VCC IRQ2 Timer Y module TMCIY VSS P16 Figure C 1 b Port 1 Block Diagram Pin P16 ...

Page 378: ... standby mode PUCR15 PMR15 PDR15 PCR15 Internal data bus PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 VCC VCC IRQ1 VSS P15 Figure C 1 c Port 1 Block Diagram Pin P15 ...

Page 379: ... PDR14 PCR14 Internal data bus PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 VCC VCC VSS P14 PWM module PWM Figure C 1 d Port 1 Block Diagram Pin P14 ...

Page 380: ...R13 PCR13 Internal data bus PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 TMIG Timer G module P13 VCC VCC VSS Figure C 1 e Port 1 Block Diagram Pin P13 ...

Page 381: ...nal data bus TMOFH P12 TMOFL P11 PDR1 PCR1 PMR1 PUCR1 n 2 1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 Timer F module VCC P1n VCC VSS Figure C 1 f Port 1 Block Diagram Pins P12 and P11 ...

Page 382: ...R10 PCR10 Internal data bus TMOW PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 Timer A module VCC P10 VCC VSS Figure C 1 g Port 1 Block Diagram Pin P10 ...

Page 383: ... Diagrams PUCR27 PMR27 PDR27 PCR27 Internal data bus PDR2 PCR2 PMR2 PUCR2 Port data register 2 Port control register 2 Port mode register 2 Port pull up control register 2 IRQ0 P27 Figure C 2 a Port 2 Block Diagram Pin P27 ...

Page 384: ...PDR26 PCR26 Internal data bus TXD PDR2 PCR2 PMR6 PUCR2 Port data register 2 Port control register 2 Port mode register 6 Port pull up control register 2 SCI3 module VCC P26 VCC VSS Figure C 2 b Port 2 Block Diagram Pin P26 ...

Page 385: ...Y PUCR25 PDR25 PCR25 RE RXD PDR2 PCR2 PUCR2 Port data register 2 Port control register 2 Port pull up control register 2 SCI3 module VCC P25 VCC VSS Internal data bus Figure C 2 c Port 2 Block Diagram Pin P25 ...

Page 386: ...PCR24 SCKIE SCKOE SCKO SCKI PDR2 PCR2 PUCR2 Port data register 2 Port control register 2 Port pull up control register 2 SCI3 module P24 VCC VSS Internal data bus VCC PUCR24 Figure C 2 d Port 2 Block Diagram Pin P24 ...

Page 387: ...23 PCR23 Internal data bus SO PDR2 PCR2 PMR2 PUCR2 Port data register 2 Port control register 2 Port mode register 2 Port pull up control register 2 SCI1 module VCC P23 VCC VSS 1 PMR23 Figure C 2 e Port 2 Block Diagram Pin P23 ...

Page 388: ... PDR22 PCR22 Internal data bus PDR2 PCR2 PMR2 PUCR2 Port data register 2 Port control register 2 Port mode register 2 Port pull up control register 2 SI SCI module P22 VCC VCC VSS Figure C 2 f Port 2 Block Diagram Pin P22 ...

Page 389: ... PCR21 EXCK SCKO SCKI PDR2 PCR2 PMR2 PUCR2 Port data register 2 Port control register 2 Port mode register 2 Port pull up control register 2 SCI module VCC P21 VCC VSS Internal data bus Figure C 2 g Port 2 Block Diagram Pin P21 ...

Page 390: ...20 PCR20 Internal data bus PDR2 PCR2 PMR2 PUCR2 Port data register 2 Port control register 2 Port mode register 2 Port pull up control register 2 IRQ4 P20 VCC VSS VCC A D module ADTRG Figure C 2 h Port 2 Block Diagram Pin P20 ...

Page 391: ...m SBY PUCR5n PMR5n PDR5n PCR5n Internal data bus PDR5 PCR5 PMR5 PUCR5 n 0 to 7 Port data register 5 Port control register 5 Port mode register 5 Port pull up control register 5 WKPn VCC P5n VCC VSS Figure C 3 Port 5 Block Diagram ...

Page 392: ...ort 6 Block Diagram SBY PUCR6n PDR6n PCR6n Internal data bus PDR6 PCR6 PUCR6 n 0 to 7 Port data register 6 Port control register 6 Port pull up control register 6 VCC P6n VCC VSS Figure C 4 Port 6 Block Diagram ...

Page 393: ...392 C 5 Port 7 Block Diagram SBY PDR7n PCR7n Internal data bus PDR7 PCR7 n 0 to 7 Port data register 7 Port control register 7 P7n VCC VSS Figure C 5 Port 7 Block Diagram ...

Page 394: ...393 C 6 Port 8 Block Diagram SBY PDR8n PCR8n Internal data bus PDR8 PCR8 n 0 to 7 Port data register 8 Port control register 8 P8n VCC VSS Figure C 6 Port 8 Block Diagram ...

Page 395: ...394 C 7 Port 9 Block Diagram SBY PDR9n PCR9n Internal data bus PDR9 PCR9 n 0 to 7 Port data register 9 Port control register 9 P9n VCC VSS Figure C 7 Port 9 Block Diagram ...

Page 396: ...Internal data bus PDRA PCRA n 0 to 3 Port data register A Port control register A PAn VCC VSS Figure C 8 Port A Block Diagram C 9 Port B Block Diagram DEC Internal data bus AMR0 to AMR3 V A D module IN PBn n 4 to 7 Figure C 9 Port B Block Diagram ...

Page 397: ...396 C 10 Port E Block Diagram SBY PDREn PCREn Internal data bus PDRE PCRE n 3 2 Port data register E Port control register E PEn VCC VSS Figure C 10 Port E Block Diagram ...

Page 398: ...gh impedance Retained Functional Functional P77 to P70 High impedance Retained Retained High impedance Retained Functional Functional P87 to P80 High impedance Retained Retained High impedance Retained Functional Functional P97 to P90 High impedance Retained Retained High impedance Retained Functional Functional PA3 to PA0 High impedance Retained Retained High impedance Retained Functional Functio...

Page 399: ...80 pin QFP FP 80B version products HD6433637X HD6433637 X 80 pin TQFP TFP 80F HD6433637W HD6433637 W 80 pin TQFP TFP 80C H8 3636 Mask ROM Standard HD6433636F HD6433636 F 80 pin QFP FP 80B version products HD6433636X HD6433636 X 80 pin TQFP TFP 80F HD6433636W HD6433636 W 80 pin TQFP TFP 80C H8 3635 Mask ROM Standard HD6433635F HD6433635 F 80 pin QFP FP 80B version products HD6433635X HD6433635 X 80...

Page 400: ... Max 1 2 0 2 24 8 0 4 20 64 41 40 25 24 1 80 65 18 8 0 4 14 0 15 0 8 2 70 2 4 0 20 0 10 0 20 0 8 1 0 0 35 0 06 0 15 0 04 Unit mm Dimension including the plating thickness Base material dimension Figure F 1 FP 80B Package Dimensions Note In case of inconsistencies arising within figures dimensional drawings listed in the Hitachi Semiconductor Packages Manual take precedence and are considered corre...

Page 401: ...0 65 0 5 0 1 16 0 0 2 60 41 80 1 21 40 20 0 8 14 61 1 0 0 32 0 08 0 10 0 10 0 10 1 20 Max 1 00 0 83 0 30 0 06 0 15 0 04 Unit mm Dimension including the plating thickness Base material dimension Figure F 2 TFP 80F Package Dimensions ...

Page 402: ... 20 Max 14 0 0 2 0 5 12 14 0 0 2 60 41 1 20 80 61 21 40 0 17 0 05 1 0 0 22 0 05 0 10 0 10 1 00 1 25 0 20 0 04 0 15 0 04 Unit mm Dimension including the plating thickness Base material dimension Figure F 3 TFP 80C Package Dimensions ...

Page 403: ...Manual Publication Date 1st Edition August 1998 Published by Electronic Devices Business Group Hitachi Ltd Edited by Technical Documentation Group UL Media Co Ltd Copyright Hitachi Ltd 1998 All rights reserved Printed in Japan ...

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