Hioki RM3542-50, Instruction Manual

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9.5 Communication Methods
124
 Standard Event Status Enable Register (SESER)
Setting any bit of the Standard Event Status Enable Register to 1 enables access to the cor-
responding bit of the Standard Event Status Register.
Standard Event Status Register (SESR) and Standard Event Status Enable Register (SESER)
 Device-Specific Event Status Registers (ESR0 and ESR1)
This instrument provides two event status registers for controlling events.
Each event register is an 8-bit register.
When any bit in one of these event status registers enabled by its corresponding event status
enable register is set to 1, the following happens:
• In case of Event Status Register 0:
Status Byte Register (STB) bit 0 (ESB0) is "1".
• In case of Event Status Register 1:
Status Byte Register (STB) bit 1 (ESB1) is "1".
Event Status Registers 0 and 1 are cleared in the following situations:
• When a "
∗
CLS
" command is executed.
• When an Event Status Register query is executed.
(
:ESR0?
,
:ESR1?
)
• When the instrument is powered on.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PON URQ CME EXE DDE QYE RQC OPC
& & & & & & & &
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PON URQ CME EXE DDE QYE RQC OPC
Standard Event Status Register (SESR)
Standard Event Status Enable Register (SESER)
bit 6 bit 5 bit 4
SRQ
MSS
ESB MAV
Logical sum