Hioki RM3542-50, Instruction Manual

Page: 128 / 234

9.5 Communication Methods
122
 Status Byte Register (STB)
During serial polling, the contents of the 8-bit Status Byte Register are sent from the instru-
ment to the controller.
When any Status Byte Register bit enabled by the Service Request Enable Register has
switched from 0 to 1, the MSS bit becomes 1. Consequently, the SRQ bit is set to 1, and a
service request is dispatched.
The SRQ bit is always synchronous with service requests, and is read and simultaneously
cleared during serial polling. Although the MSS bit is only read by an
∗
STB?
query, it is not
cleared until a clear event is initiated by the ∗
CLS
command.
 Service Request Enable Register (SRER)
This register masks the Status Byte Register. Setting a bit of this register to 1 enables the cor-
responding bit of the Status Byte Register to be used.
Bit 7 unused
Bit 6
SRQ Set to 1 when a service request is dispatched.
MSS This is the logical sum of the other bits of the Status Byte Register.
Bit 5 ESB
Standard Event Status (logical sum) bit
This is the logical sum of the Standard Event Status Register.
Bit 4 MAV
Message available
Indicates that a message is present in the output queue.
Bit 3 unused
Bit 2 unused
Bit 1 ESB1
Event Summary (logical sum) bit 1
This is the logical sum of Event Status Register 1.
Bit 0 ESB0
Event Summary (logical sum) bit 0
This is the logical sum of Event Status Register 0.