HIMax System
5 Programming
HI 801 001 E Rev. 4.01
Page 69 of 122
First CPU Cycle Considered
Second CPU Cycle Considered
Input Processing in the First CPU Cycle
First UP 1 Cycle Considered
First Portion of the Considered UP 2
Cycle
Output Processing in the First CPU Cy-
cle
Input Processing in the Second CPU
Cycle
Second UP 1 Cycle Considered
Second Portion of the Considered UP 2
Cycle
Output Processing in the Second CPU
Cycle
Figure 12:
CPU Cycle Sequence with Multitasking
Each UP 1 cycle is completely processed during each CPU cycle. UP 1 processes an input
change registered by the system at the beginning of the CPU cycle
and delivers a
reaction at the end of the cycle.
One UP2 cycle requires two CPU cycles to be processed. UP 2 needs CPU cycle
to
process an input change registered by the system at the beginning of CPU cycle
. For
this reason, the reaction to this input change is only available at the end of CPU cycle
.
The reaction time of UP 2 is two times longer than that of UP 1.
Upon completion of the first part
of the UP 2 cycle under consideration, UP 2
processing is
completely
aborted and only resumed when
starts. During its cycle, UP 2
processes the data provided by the system during
. The results of UP 2 are available to
the system during
(e.g., for process output). The data that the system exchanges with
the user program are always consistent.
The program processing sequence can be controlled by assigning a priority, which
indicates how important the corresponding user program is compared to the others (see
multitasking mode 2).
To specify the user program execution order, use the following parameters in the resources
and programs or in the Multitasking Editor:
Summary of Contents for HIMax
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