hilscher NXHX 4000-JTAG+, Device Description

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Schematic diagrams 47/70
5.2 Debugging
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Q
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Q
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2
[2
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G
N
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G
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+
3
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3
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3
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3
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3
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M
M
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0
2
_
G
P
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0
_
2
[1
6
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M
M
IO
0
3
_
G
P
IO
0
_
3
[1
6
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M
M
IO
0
4
_
G
P
IO
0
_
4
[1
6
]
M
M
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0
5
_
G
P
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0
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5
[1
6
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M
M
IO
0
6
_
G
P
IO
0
_
6
[1
6
]
M
M
IO
0
7
_
G
P
IO
0
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7
[1
6
]
M
M
IO
0
8
_
G
P
IO
0
_
8
[1
6
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M
M
IO
0
9
_
G
P
IO
0
_
9
[1
6
]
+
3
V
3
G
N
D
G
N
D
Figure 8: “Debugging” schematic diagram
NXHX 4000-JTAG+ | Device description
DOC170703HW02EN | Revision 2 | English | 2018-10 | Released | Public © Hilscher 2018