Schematic diagrams
46/70
5.1
JTAG_RESET_RDY_RUN
JT
_
S
E
L
1
J
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S
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L
0
F
un
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C
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a
nd
n
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rm
a
l o
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(
no
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J
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Z
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)
1
0
B
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4
0
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1
1
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C
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12
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3
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2
2
S
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3
F
2
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C
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#
K
4
0
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2
2
6
0
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0
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tX
4
0
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R
2
1
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4
7
0
0
4
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2
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1
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4
7
0
0
4
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2
1
2
R
2
1
6
1
0
k
04
02
1
2
R
2
1
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1
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k
04
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na
G
N
D
G
N
D
JT
_
T
D
I
JT
_
T
D
O
JT
_
T
M
S
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W
D
+
JT
_
T
C
L
K
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W
C
L
K
JT
_
#
T
R
S
T
JT
_
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E
L
0
JT
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L
1
JT
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+
6
V
9
G
N
D
S
E
N
S
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_
#
P
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[1
0
,1
1
,1
2
,1
5
,2
1
]
G
N
D
G
N
D
JT
_
#
R
E
S
E
T
_
IN
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
S
E
N
S
E
_
#
P
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R
S
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#
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D
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L
A
Y
E
D
G
N
D
JT
_
#
R
E
S
E
T
_
IN
[3
,2
1
]
S
Y
S
_
#
R
D
Y
[3
,1
5
]
S
Y
S
_
#
R
U
N
[3
]
S
P
K
R
_
S
E
T
[1
6
]
+
5
V
G
N
D
G
N
D
S
P
K
R
_
D
S
P
K
R
_
P
IE
Z
O
JT
_
+
6
V
9
[3
]
JT
_
S
E
L
1
[3
]
JT
_
#
T
R
S
T
[3
,2
1
]
JT
_
T
C
L
K
/S
W
C
L
K
[3
]
JT
_
T
M
S
/S
W
D
+
[3
]
JT
_
T
D
O
[3
]
JT
_
T
D
I
[3
]
U
S
B
1
1
_
D
N
E
G
[3
]
U
S
B
1
1
_
D
P
O
S
[3
]
G
N
D
G
N
D
O
S
C
4
0
M
_
X
T
2
+
1
V
1
6
2
5
G
N
D
Q
S
P
I_
#
C
S
Q
S
P
I_
M
IS
O
_
S
IO
1
Q
S
P
I_
M
O
S
I_
S
IO
0
Q
S
P
I_
C
L
K
Q
S
P
I_
S
IO
3
Q
S
P
I_
S
IO
2
Q
S
P
I_
M
IS
O
_
S
IO
1
[3
]
Q
S
P
I_
M
O
S
I_
S
IO
0
[3
]
Q
S
P
I_
C
L
K
[3
]
Q
S
P
I_
S
IO
2
[3
]
S
Y
S
_
#
R
S
T
_
O
U
T
[1
5
,1
6
]
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
_
N
E
T
X
[2
,8
,9
,1
2
,1
4
]•[1
5
,1
6
,1
7
,1
8
,1
9
]•[2
1
,2
2
]
+
3
V
3
_
N
E
T
X
[2
,8
,9
,1
2
,1
4
]•[1
5
,1
6
,1
7
,1
8
,1
9
]•[2
1
,2
2
]
+
3
V
3
_
N
E
T
X
[2
,8
,9
,1
2
,1
4
]•[1
5
,1
6
,1
7
,1
8
,1
9
]•[2
1
,2
2
]
+
3
V
3
Figure 7: "JTAG_RESET_RDY_RUN" schematic diagram
NXHX 4000-JTAG+ | Device description
DOC170703HW02EN | Revision 2 | English | 2018-10 | Released | Public
© Hilscher 2018