HSBT3031-08 module_datasheet
Version2.0– Jun. 15
th
HANSONG ( NANJING) TECHNOLOGY CO.,LTD
14
Transaction bridge debug access is lockable. When locked, this interface only becomes active
after the correct unlock key sequence is provided.
7.4 RESET# reset
The HSBT3031-08 digital reset pin (RESET#) is an active low reset signal. PIO[1] defaults to
RESET# upon boot.
The pin is active low and on-chip glitch filtering avoids the need to filter out any spurious noise
that may cause unintended resets. The RESET# pin has a fixed strong pull-up to
VDD_PADS_1, and therefore can be left unconnected. The input is asynchronous, and is
pulse extended within HSBT3031-08 to ensure a full reset.
HSBT3031-08 contains internal Reset Protection functionality to automatically keep the power
rails enabled and enable the system to restart after unintended reset (such as a severe ESD
event). Assertion of RESET# beyond the Reset Protection timeout (typically greater than ~1.8
s) causes the device to power down if VCHG is not present and SYS_CTRL is low.
HSBT3031-08 then requires a SYS_CTRL assertion or VCHG attach to restart.
NOTE
HSBT3031-08 is always powered if VCHG is present. It does not power down if
RESET# is asserted while VCHG remains present.
QTIL recommends that HSBT3031-08 is powered down via software-controlled
methods rather than external assertion of RESET#.
Holding RESET# low continuously is not the lowest HSBT3031-08 power state,
because pull downs are enabled on VCHG and VDD_BYP in this state.
RESET# is guaranteed to work if held low for 120us.
After boot, PIO[1] is configurable as a digital PIO.
7.5 SYS_CTRL
SYS_CTRL is an input pin that acts as a power on signal for the internal regulators. It can also
be used as an input (appears to software as virtual PIO[0]) or as a multifunction button.
From the OFF state, SYS_CTRL must be asserted for >20 ms to start power up.
SYS_CTRL is VBAT tolerant (4.8 V max), and typically connected via a button to VBAT.
