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GENERAL DESCRIPTION.

The TD-2 is an advanced DTMF

tone decoder and multichannel con-
troller providing 5 latching outputs

and up to 12 momentary outputs.
Latching outputs are handy to control

autopatches, repeaters, sub-audible
tone decoders, and various other

on/off functions. A toll call restrictor
is included in the autopatch control

circuitry at no extra cost. The heart of
the TD-2 is a central office grade, 16-

digit, crystal controlled DTMF decoder
chip with built-in filters to prevent

falsing on noise or voice signals. Reli-
able operation is maintained for any

audio input level from 100mV to 2V p-
p. Low power consumption is made

possible by the exclusive use of CMOS
ic's. The unit can operate on 10-

15Vdc at only 15mA. Control codes
are easily programmable and allow

flexibility in code types. See our cata-
log for a full list of features.

THEORY OF OPERATION.

Refer to schematic diagram.

The

input to tone decoder chip U1 is proc-
essed through a dial tone filter and a
bandsplit filter using switched capaci-
tor technology. The signal is then
analyzed by two zero-crossing detec-
tors and a digital detection algorithm
to determine if and which tones are
present. Then, the resulting logic sig-
nals are processed in a code converter
and latch circuit to provide four bi-
nary outputs (called Q1-Q4) with en-
coded information about dtmf digits
which may have been received.

A valid digit strobe (StD) signal in-

dicates when any valid digit tones are
received. This valid digit signal is
used to gate U2 and to provide a mut-
ing signal to the autopatch board
when tones are received. It also oper-
ates the toll call restrictor, which is
discussed later. The whole circuit is
run on a clock controlled by color
burst crystal Y1. The audio input
signal is filtered by L1/C1 to remove
any rf which may be picked up on the
wiring. The ratio of R2-R3 sets the
gain of the op-amp input circuit. C3-
R4 sets the length of time necessary
for presence of valid tones and the in-
terval between tones to prevent erratic
operation. U2 decodes the hexadeci-
mal information from U1 to provide 16
CMOS output lines corresponding to
the digits on a DTMF pad. Program-
ming for the various functions is done
by soldering jumper wires from pro-
gram pads at the output of U2 to ad-

jacent function program pads.

The 4013 latches may be operated

synchronously or directly. The Q out-
put will assume a hi whenever the set
input is triggered by a hi or a lo when-
ever the reset input is triggered by a
hi. The not-Q output is just the in-
verse. The latch also may be operated
synchronously, with its Q output as-
suming the whatever state the data
input has applied when the clock in-
put receives a hi. If the clock input is
lo, the latch ignores the data input.
But if the clock goes hi at any time,
the latch will follow the data input
when the clock is hi.

U5A/B and U6B are D-type flip-

flops operating as a "key" latch in con-
junction with program inputs K1-K3.
The output of U6B is high only upon
proper receipt of a three digit code,
which provides a security "key" to
unlock the rest of the logic gates.
R8/C11/CR2 in the reset circuit of
U5A provides a five-second time delay.
When the first digit of the key is re-
ceived, the not-Q output of U5A re-
leases the reset inputs of the other
two flip-flops for about five seconds. If
the full three digit code is not com-
pleted within that time period, all
three flip-flops are reset.

There are 12 momentary functions,

each using a 4081 ANDgate. Nor-
mally, one input of each AND-gate is
tied to the so-called "key" bus coming
from U6B and the other input is tied
to a programming pad bearing the
name of the output line from the AND-
gate. To actuate a function, it is nec-
essary to send the three-digit key plus
a fourth digit indicating the desired
function. During the interval when
the key is active (about five seconds),
if any other function is selected, it
may be activated with just its one digit
function code. If the key period ex-
pires, then the key must be re-sent to
start another command. It is also
possible to eliminate the key alto-
gether, if the security is not needed,
allowing one digit commands at any
time. This is done by disconnecting
the input of the AND-gate normally
connected to the key bus and recon-
necting it to the +5V bus instead. You
can even use the key for some func-
tions and not others; using only a "#",
for instance, to turn off the autopatch,
but requiring the full four digits to
turn it on.

When a particular AND-gate re-

ceives both a key input and a function
input, it applies a hi signal to its out-
put line. In the case of five pairs of

AND-gates, the outputs also are tied
to the "set" and "reset" inputs of
latches. The latches, in turn, drive
output transistors and led's. The
open-collector transistor switches may
be used to drive external circuits.
Thus, the momentary outputs, which
are CMOS hi's in the active state, may
be used or the latch outputs may be
used or any combination of latch and
momentary outputs may be used as
desired.

The names of the lines were se-

lected based on two parameters.

First, the letter indicates the function
usually associated with the line. The
"R" function normally is used to en-
able or disable a repeater. The "A"
function normally controls an auto-
patch in a repeater. Of course, the
circuits can be used for any other
function, but it was thought best to
select names based on uses most
owners will have for them. The other
functions are not dedicated to any
particular function; so they were
named B, C, D, and E. (E is the pair
of momentary functions which has no
latch. We loaded the pc board with all
the functions we could fit on the
board, and we had two AND-gates left
to provide the extra momentary func-
tions. There is no other significance.
If you need a momentary function or
two, you can use the E functions
without feeling you are wasting an as-
sociated latch.) The number, 1 or 0,
indicates which line turns the latched
output on or off.

It is a little confusing looking at

the latch circuits until you realize that
the repeater latch circuit is different
from the others, which turn on a cir-
cuit by the collector of the transistor
conducting to ground. The R latch
mutes a repeater by grounding the
COS line from the receiver or auto-
patch to the COR board input. Thus,
the repeater is off when the transistor
is active instead of being on when the
transistor conducts like the other cir-
cuits. The autopatch latch is differ-
ent, too, because of extra toll call
restriction circuits. There also is a
difference in the way that the latches
are preset at power up. The repeater
wants to be enabled after a power
failure, not disabled. So its latch is
wired to default with the repeater en-
abled. The other latches default in
the off condition. Default status is
set by the C/R networks on the clock
or reset inputs of the latches. When
power is first applied, a positive pulse
is applied by the capacitor to reset the