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4 Reference Design 

4.1 Project Code 

 

IPUG546-1.1E 

16(17) 

 

4

  Reference  Design 

4.1

 

Project Code 

The key files in the AE250 embedded project template are as follows: 

1. 

src/bsp/ae250/ae250.h: This file contains the system clock definition, 
peripheral register definition, peripheral register address mapping 
definition, and interrupts source number definition. The clock definition 
must be consistent with the AE250 parameters configuration. 

2. 

src/bsp/ae250/ae250.c: The reset_handler function is the entry to start 
the embedded program. In the entry, UART initialization is performed 
before the main function is executed. The required UART port is 
selected and the required baud rate is configured according to the 
parameter configuration of AE250. 

3. 

src/bsp/ae250/interrupt.c: This file is the definition of interrupt handler 
functions of AE250 

4. 

src/bsp/config/config.h: This file contains the macro definition that 
control compilation method. #define BUILD_MODE can be defined as 
BUILD_LOAD or BUILD_BURN. BUILD_LOAD means that the 
program is loaded directly into ILM, and it is generally used when 
debugging. BUILD_BURN means the program is downloaded to SPI 
Flash, and the program is read from SPI Flash to ILM first after power 
on, and then run, which is applicable to release version program. 

5. 

Start.S: The starter file written in assembly language. 

6. 

src/bsp/loader.c: bootloader file, which is used to start from SPI Flash. 

7. 

ae250.sag: Sag is the scattering-and-Gathering format script. It's used 
to generate linker script. It should be noted that the memory map 
parameters in ae250.sag need to be consistent with those in AE250. 

8. 

src/bsp/driver: This directory contains two folders, ae250 is AE250 

Summary of Contents for RISCV

Page 1: ...Gowin FPGA Development Board RISCV Programming Quick Start Guide IPUG546 1 1E 11 11 2022 ...

Page 2: ...l photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale Al...

Page 3: ...rsion Description 04 29 2019 1 0E Initial version published 11 11 2022 1 1E AndeSight RDS v311 software updated Reference design updated The description of downloading embedded project compilation results via SPI Flash updated ...

Page 4: ... Developing and Debugging Steps 3 2 Debug Cable Connection Instructions 4 3 Use Instructions for RDS 6 3 1 RDS Installation 6 3 2 Create a New Project 6 3 3 Import and Export a Project 8 3 4 Download Programs to Flash 9 3 5 On chip Debug 12 3 6 RDS Built in Serial Terminal Usage 14 4 Reference Design 16 4 1 Project Code 16 4 2 Reference Design 17 ...

Page 5: ...Figure 3 2 Import Export a Project 8 Figure 3 3 Import a Project 8 Figure 3 4 Export a Project 9 Figure 3 5 System Reset Vector Default 10 Figure 3 6 SPI1 Configuration 10 Figure 3 7 Set MSPI Interface to Regular IO 11 Figure 3 8 ae250 sag bootloader Parameters Setting 12 Figure 3 9 Debug Configurations 13 Figure 3 10 Debug Introduction 14 Figure 3 11 Assembly Instruction Code Window 14 Figure 3 1...

Page 6: ...List of Tables IPUG546 1 1E iii List of Tables Table 2 1 AICE MINI Debug Cable Pin Definition 5 Table 3 1 SPI1 Interface Physical Constraints 11 ...

Page 7: ... Introduction 1 1 AE250 Introduction AE250 is a 32 bit RISC V MCU system its structure is shown in Figure 1 1 Figure 1 1 AE250 Structure Diagram Based on Gowin FPGA development board the RISC V AE250 MCU development and debugging system is shown in Figure 1 2 ...

Page 8: ...d program development and debugging with AndeSight RDS v311 software 1 2 Preparations Before using Gowin FPGA and AE250 for development and debugging the following tools need to be prepared 1 Gowin GW2A series of FPGA development board 2 Gowin Software installation package for configuring and downloading the FPGA chip 3 AndeSight RDS v311 installation package for developing and debugging the embed...

Page 9: ...the Debug Cable used for AE250 debugging download the project compilation result to the instruction memory ILM in AE250 and start debugging on the chip 4 During debugging you can use UART to USB cable to connect the UART interface of AE250 to PC use the built in serial terminal in RDS to operate the input and output operations You can use GPIO to connect to LED indicators keys or external pins for...

Page 10: ...ld be noted that pin 1 is blank in the figure When the cable is correctly connected and RDS is opened the red LED light marked with yellow box in the figure will go out Figure 2 1 AICE MINI Debug Cable and its Pins The pin definition of AICE MINI debug cable is as shown in Table 2 1 It should be noted that Pin 1 is defined as No Connection NC corresponding to the blank one VREF needs to connect a ...

Page 11: ...le Connection Instructions IPUG546 1 1E 5 17 Table 2 1 AICE MINI Debug Cable Pin Definition Pin Number AICE MINI Debug Cable Pin 1 NC 2 TSRST_N 3 GND 4 TTMS 5 GND 6 TCK 7 VREF 8 NC 9 NC 10 TTRST_N 11 TTDO 12 TTDI ...

Page 12: ...pdf which can be found in the installation package 1 When setting the installation path and workspace path do not include Chinese characters or space or it will get a runtime error 2 The current version of RDS supports AICE MINI Cable by default 3 GOWIN Programmer may be unable to connect to the development board after installing RDS which can be fixed by reinstall Gowin Programmer driver 4 For se...

Page 13: ...debug cable If the emulator is used as a test platform please select SID 4 For Chip Profile select ADP AE250 N25 GOWIN which is optimized according to Gowin FPGA 5 Project Type includes an Empty Project and a Hello World ANSI C Project 6 For Toolchains nds32le elf mculib v5m is the default After creating a new project right click on the project name in the Project Explorer select Build Project fro...

Page 14: ...wn in Figure 3 2 Figure 3 2 Import Export a Project Click Import General Existing Project into workspace to import a project and the interface is as shown in Figure 3 3 When selecting Select root directory import the project in folder when selecting Select archive fil import the project in zip Figure 3 3 Import a Project Select Export Archive File to open the export project interface as ...

Page 15: ...dded program is executed The recommended method is to reuse SPI Flash that saves FPGA Bitstream use the first half of Flash to save the FPGA Bitstream and the remaining to save the binary files of embedded programs 1 Open the IP core generator in Gowin Software and call AE250 RTL parameters Double click the SMU to open the SMU interface and set System Reset Vector Default to 0x80400000 as shown in...

Page 16: ...e 3 5 System Reset Vector Default 2 2 Double click SPI1 to open the SPI1 interface check SPI1 Support and set SPI1 Memory Map Space Base Address to 0x80400000 as shown in Figure 3 6 Figure 3 6 SPI1 Configuration 3 In the physical constraints of RTL design the SPI1 interface should be ...

Page 17: ...MCLK MISO MSO MOSI MSI 4 Reuse MSPI interface as regular IO In the Process window of Gowin Software right click Place Route select Configuration in the pop up menu select Dual Purpose Pin tab and check Use MSPI as regular IO and click OK to finish placement and routing Figure 3 7 Set MSPI Interface to Regular IO 5 Modify embedded program parameter settings First modify the parameters of bootloader...

Page 18: ...to generate binary files of the embedded project and download the files to SPI Flash 0x400000 address using Gowin Programmer external Flash C Bin mode Synthesize and place route the modified RTL design again and download it to SPI Flash 0x000000 address using Gowin Programmer external Flash mode 3 5 On chip Debug After compilation the compilation results of the embedded project can be downloaded t...

Page 19: ...a breakpoint at the beginning of the main function Check Resume and it will start the continuous operation directly after entering on chip debug When entering on chip debug it automatically goes to the debug view and an area will be displayed as shown in Figure 3 10 This area is the operation area for on chip debug Some shortcut buttons for debug are shown in the red box From left to right they me...

Page 20: ...roduction Figure 3 11 is an assembly statements window that displays the contents of assembly instructions running in real time in ILM Figure 3 11 Assembly Instruction Code Window 3 6 RDS Built in Serial Terminal Usage Figure 3 12 shows the UART Terminal built in RDS interface If you need to use click Window Show View Terminal in the top menu to open Terminal window and then click open a terminal ...

Page 21: ... Built in Serial Terminal Usage IPUG546 1 1E 15 17 Figure 3 12 RDS Built in Serial Terminal For the details see the document AndeSight_RDS_v3 1_User_Manual_UM170_V1 0 pdf which can be found in the doc path of the installation directory ...

Page 22: ...rc bsp ae250 interrupt c This file is the definition of interrupt handler functions of AE250 4 src bsp config config h This file contains the macro definition that control compilation method define BUILD_MODE can be defined as BUILD_LOAD or BUILD_BURN BUILD_LOAD means that the program is loaded directly into ILM and it is generally used when debugging BUILD_BURN means the program is downloaded to ...

Page 23: ...directory or in the reference design zip at the website the reference design can be loaded into RDS for trial debugging and redeveloping by the way of importing The reference designs are shown as follows 1 ae250_demo Demonstrates UART input output and GPIO output of the AE250 2 ae250_plic Demonstrates the response of the interrupt controller to interrupts and provides demonstrations of the machine...

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