6 Configuration Mode Introduction
6.2 JTAG Configuration
UG290-2.5.2E
27(98)
Figure 6-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode
FPGA
TCK
TMS
TDI
TDO
FPGA
TCK
TMS
TDI
TDO
FPGA
TCK
TMS
TDI
TDO
JTAG PORT
TCK
TMS
TDI
TDO
R
E
A
D
Y
R
E
C
O
N
F
IG
_
N
D
O
N
E
R
E
A
D
Y
R
E
C
O
N
F
IG
_
N
D
O
N
E
R
E
A
D
Y
R
E
C
O
N
F
IG
_
N
D
O
N
E
Note!
DONE, RECONFIG_N, and READY can be connected or not as appropriate.
6.2.3
JTAG Configuration Timing
See Figure 6-6 for the timing of JTAG mode.
Figure 6-6 JTAG Configuration timing
See Table 6-4 for the description of timing parameters.
Table 6-4 JTAG Configuration Timing Parameters
Name
Description
Min.
Max.
T
tckftco
Time from TCK falling edge to output
-
10ns
T
tckftcx
Time from SCLK falling edge to high impedance
-
10ns
T
tckp
TCK clock period
40ns
-
T
tckh
TCK clock high time
20ns
-
T
tckl
TCK clock low time
20ns
-
T
jps
JTAG PORT setup time
10ns
-
T
jph
JTAG PORT hold time
8ns
-
