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5 Configuration Mode Introduction

5.9 I2C Mode

UG290-2.3E

68(87)

Figure 5-52 Connection Diagram for I

2

C Mode

FPGA

SCLK

DIN

Host

CLK

DOUT

Note!

The figure above shows the minimum system diagram of the I

2

C MODE. The MODE value

is set to "100". The connection for the other fixed pins is shown in Figure 5-1.

Figure 5-53 I

2

C Mode Timing

I

2

C is a serial transmission bus, which transmits data according to the

protocol shown in the figure above. Under normal status, both SDA and
SCL are at high level.

Table 5-21 I

2

C Configuration Timing Parameters

Prameter

Description

S

Start condition

SCL is high level and SDA switches from high to low level.

P

Stop condition

SCL is high level and SDA jumps from low to high level.

ADDRESS

Address frame

A unique 7-bit or 10-bit sequence for each slave device
that identifies the slave device when the master device is
about to communicate with it.

R/W

Read/Write bit

Determines whether the master sends data to the slave (0)
or reads data from the slave (1).

ACK

ACK/NACK

位

Each frame in the message is followed by an ACK/NACK
bit, and Gowin FPGA returns 0 if correct.

DATA

Data

A data has 8bits, and the most significant bit is sent first.

All DATA on the I2C bus is transmitted in 8-bit bytes. Each byte sent by the

transmitter, it releases the DATA line during the clock pulse 9, and the receiver sends
back an answer signal.The response signal is a valid response bit (ACK bit) if it is low,
indicating that the receiver has successfully received the byte. The response signal is
a non-acknowledgement bit (NACK) if it is high, which generally indicates that the
receiver did not succeed in receiving the byte. The requirement for the ACK feedback
is that the receiver pulls the SDA line low during the low level prior to the 9th clock
pulse and ensures a stable low level during the high level of the clock.If the receiver is
the master, after it receives the last byte, it sends a NACK signal to notify the
controlled sender to end the data transmission and releases the SDA line for the
master receiver to send a stop signal.

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Summary of Contents for GW2AR-18

Page 1: ...Gowin FPGA Products Programming and Configuration Guide UG290 2 3E 02 07 2021 ...

Page 2: ... identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms...

Page 3: ...reuse description updated The programming features of B version devices updated Configuration notes and the timing for different configuration modes added 1 8 2019 1 05E The configuration timing and parameters for SERIAL mode added The description of power supply requirements deleted 8 16 2019 1 06E Power up description and configuration flow added The description of File Size Configuration modifi...

Page 4: ...Configuration Pin Multiplexing 9 4 2 Configuration Pin Function and Application 11 5 Configuration Mode Introduction 16 5 1 Configuration Notes 16 5 2 JTAG Configuration 19 5 2 1 JTAG Configuration Mode Pins 20 5 2 2 Connection Diagram for the JTAG Configuration Mode 21 5 2 3 JTAG Configuration Timing 22 5 2 4 JTAG Configuration Process 23 5 3 AUTO BOOT Configuration Supported by LittleBee Family ...

Page 5: ...m File Configuration 70 6 1 Configuration Options 70 6 2 Configuration Data Encryption Supported by Arora Family only 71 6 2 1 Definition 71 6 2 2 Enter Encryption KEY 72 6 2 3 Enter the Decrypt Key 72 6 2 4 Programming Operation 73 6 2 5 Programming Flow 75 6 3 Configuration File Size 78 6 4 Configuration File Loading Time 79 7 Safety Precautions 83 8 Boundary Scan 85 9 SPI Flash Selection 87 ...

Page 6: ...5 14 Process of reading SRAM 30 Figure 5 15 The Embedded Flash Erasing process of T Technology 32 Figure 5 16 The Embedded Flash Erasing process of S Technology 34 Figure 5 17 Process of Programming Internal Flash View 36 Figure 5 18 X page Programming 37 Figure 5 19 Y page Programming 38 Figure 5 20 Process of Reading Internal Flash 39 Figure 5 21 Process of Reading a Y page 40 Figure 5 22 GW1N 4...

Page 7: ... Address for the External Flash 60 Figure 5 44 Connection Diagram for Configuring Multiple FPGAs via Single Flash 61 Figure 5 45 MSPI Download Timing 61 Figure 5 46 Multiple FPGA Connection Diagram in MSPI Configuration Mode 62 Figure 5 47 Dual Boot Flow Chart 63 Figure 5 48 Connection Diagram for CPU Mode 65 Figure5 49 CPU Mode Configuration Timing 65 Figure 5 50 Connection Diagram for SERIAL Mod...

Page 8: ...ddress and Length of One Address 29 Table 5 8 TCK Frequency Requirements for JTAG 31 Table 5 9 Readback pattern Autoboot pattern 35 Table 5 10 Pin State 44 Table 5 11 Status Register Definition 46 Table 5 12 SSPI Mode Pins 49 Table 5 13 SSPI Configuration Timing Parameters 50 Table 5 14 Configuration Instruction 51 Table 5 15 Pin Description in JTAG Configuration Mode 57 Table 5 16 MSPI Configurat...

Page 9: ...List of Tables UG290 2 3E vi Table 9 1 SPI Flash Operation Instruction 87 ...

Page 10: ...1NR series of FPGA Products Data Sheet DS226 GW2AR series of FPGA Products Data Sheet DS961 GW2ANR series of FPGA Products Data Sheet DS821 GW1NS series of FPGA Products Data Sheet DS841 GW1NZ series of FPGA Products Data Sheet DS861 GW1NSR series of FPGA Products Data Sheet DS871 GW1NSE series of FPGA Products Data Sheet DS881 GW1NSER series of FPGA Products Data Sheet DS891 GW1NRF series of FPGA...

Page 11: ...a Configuration Mode Configuration Mode EFlash EmbFlash Embedded Flash Internal Flash Internal Flash Programming Programming Edit Mode Edit Mode User Mode User Mode Background Programming Embedded Flash Background Programming LSB Least Significant Bit MSB Most Significant Bit TAP Test Access Port Security Bit Security Bit Bscan Boundary Scan I2C I2 C IIC Inter Integrated Circuits SCL Serial Clock ...

Page 12: ...onfiguration modes each device supports depend on the device model and package MODE 2 0 A representation of the three MODE pin values associated with GowinCONFIG AUTO BOOT Configuration FPGA loads bitstream data into the SRAM from an embedded Flash Only non volatile devices support this mode DUAL BOOT Configuration Two bitstream files are stored in embedded Flash and external Flash separately Swit...

Page 13: ...can only be transmitted between adjacent devices User Mode Hands over control to users when the FPGA configuration has been completed Only in user mode configuration pins can be reused as GPIOs Gowin Programmable I O Edit Mode FPGA can be programmed and configured in this mode All configuration pins cannot be reused as GPIOs The output of all GPIOs is high impedance state except transparent transm...

Page 14: ...t is commonly used in the industry the LittleBee Family of FPGA products also support GOWINSEMI s own configuration mode GowinCONFIG GowinCONFIG configuration modes that are available and supported for each device depend on the device model and package All non volatile devices support JTAG and AUTO BOOT modes Up to six configuration modes are supported as shown in Table 3 1 ...

Page 15: ...is independent of MODE value 3 The SPI interfaces of the SSPI and MSPI modes are independent of each other 4 Currently GW1N R 4 GW1N R 4B do not support DUAL BOOT 5 The CPU configuration mode and SERIAL configuration mode share SCLK WE_N and CLKHOLD_N The data bus pins for the CPU configuration mode share pins with MSPI and SSPI configuration modes 6 I 2 C is only supported in some devices Note Fo...

Page 16: ...t configures Arora Family of FPGA products via DIN interface CPU4 111 External Host configures Arora Family of FPGA products via DBUS interface Note 1 The unbound mode pins are grounded by default 2 The JTAG configuration mode is independent of MODE value 3 The SPI interfaces of the SSPI and MSPI modes are independent of each other 4 The CPU configuration mode and SERIAL configuration mode share S...

Page 17: ...and also can be reused as GPIO Users can configure the pins as required Users also can configure them according to their configuration functions to meet specific requirements 4 1 Configuration Pin List and Reuse Options 4 1 1 Configuration Pin List Table 4 1 contains a list of all the configuration pins of Gowin FPGA products together with the details of the pins used in each configuration mode an...

Page 18: ... To maximize the utilization of I O Gowin FPGA products support setting the configuration pins as GPIO pins Before any configuration operation is performed on all series of Gowin FPGA products after power up all related configuration pins are used as configuration pins by default After successful configuration the device enters into user mode and reassigns the pin functions according to the multip...

Page 19: ...Dedicated configuration pins Set as GPIO Used as GPIO after configuration DONE Default Status Dedicated configuration pins Set as GPIO Used as GPIO after configuration Note 1 For the devices with JTAGSEL_N unbound when debugging JTAG pin reuse it s suggested to set MODE value to non auto configuration mode being neither auto boot dual boot nor MSPI before power up to avoid the other bit stream dat...

Page 20: ... function for the FPGA programming configuration FPGA can t be configured if RECONFIG_N is set to low Keep high level during FPGA powering up until the powering up is stable for 1ms As a configuration pin a low level signal with pulse width no less than 25ns is required for GowinCONFIG to reload bitstream data according to the MODE setting value You can also write logic to control the pin to trigg...

Page 21: ...g Otherwise the FPGA will fail to enter the user mode after being configured MODE GowinCONFIG modes selection pin As the selection pin of GowinCONFIG modes MODE is an input pin that has internal weak pull up The maximum bit width is 3 bits When FPGA powers up or a low level pulse triggers RECONFIG_N the device enters the corresponding GowinCONFIG mode in accordance with the MODE value The same MOD...

Page 22: ...pe TDO As a configuration pin it is an output pin It is a serial data output pin in JTAG configuration mode As a GPIO it can be used as an input or output type SCLK As a configuration pin it is an input pin It is a clock input pin in SSPI SERIAL and CPU configuration modes As a GPIO it can be used as an input or output type CLKHOLD_N As a configuration pin it is an input pin with internal weak pul...

Page 23: ... Setting MCS_N As a configuration pin it is an output pin It is a chip selection signal in MSPI configuration mode active low As a GPIO it can be used as an input or output type MI As a configuration pin it is an input pin It is a serial data input pin in MSPI configuration mode As a GPIO it can be used as an input or output type MO As a configuration pin it is an output pin Serial data output pin...

Page 24: ...ll up It is a serial data input pin in the SERIAL configuration mode As a GPIO it can be used as an input or output type DOUT As a configuration pin it is an output pin It is a serial data output pin in the SERIAL configuration mode which is only used as the input to the latter device when the FPGA is cascading As a GPIO it can be used as an input or output type SCL As a configuration pin it is an...

Page 25: ...T or DUAL BOOT configuration The mode value for each configuration is different 5 1 Configuration Notes GOWINSEMI FPGA products include LittleBee family and Arora family Whether the name of the device contains R does not affect the configuration feature the main difference is that SDRAM PSRAM is integrated in all FPGA products that have a serial number that includes the letter R Except DUALBOOT co...

Page 26: ...an only be programmed via the JTAG interface and the clock rate is no less than 1MHz Please refer to Table 5 7 for the clock rate Note During configuring SRAM devices via built in Flash AUTOBOOT configuration and DUALBOOT configuration and programming built in Flash the FPGA needs to remain powered up and the RECONFIG_N cannot be triggered at low level otherwise it may cause irreparable damages to...

Page 27: ...e 5 1 Recommended Pin Connection FPGA MODE 0 MODE 1 MODE 2 RECONFIG_N READY DONE 4 7K LED DC3 3V 4 7K DC3 3V LED 4 7K DC3 3V 1K 1K KEY 1K Note Add the dial switch to change the MODE value Some MODE pins of devices are not all bonded out and the unbonded MODE pins are grounded by default The values of READY and DONE signals have no meaningful reference in JTAG configuration The unbonded RECONFIG_N ...

Page 28: ...e power up waiting time is 50 μs Timing parameters of the Arora Family of FPGA Products are as shown in Table 5 2 Table 5 2 Timing Parameters for Power on again and RECONFIG_N Triggering Arora Family Name Description Min Max Tportready Time from application of VCC VCCX and VCCO to the rising edge of READY 23ms Trecfglw RECONFIG_N low pulse width 25ns Trecfgtrdyn Time from RECONFIG_N falling edge t...

Page 29: ...k input TMS2 I internal weak pull up JTAG serial mode input TDI I internal weak pull up JTAG serial data input TDO O JTAG serial data output Note 1 The JTAGSEL_N works only when the JTAG pin is set as a GPIO and the device starts to work For the LittleBee Family of FPGA products when MODE 2 0 001 the JTAGSEL_N pin and the four JTAG pins TCK TMS TDI TDO can be set as GPIOs simultaneously but the JT...

Page 30: ...and JTAG pin will be used as a GPIO The clock frequency for JTAG configuration mode is no higher than 40MHz In addition to using JTAG to configure SRAM the built in Flash of Gowin non volatile FPGA devices LittleBee Family and the external SPI Flash of all other FPGA series programming can also be configured through the JTAG pin The connection for programming the built in Flash of the non volatile...

Page 31: ... be connected or not as appropriate 5 2 3 JTAG Configuration Timing See Figure 5 6 for the timing of JTAG mode Figure 5 6 JTAG Configuration timing See Table 5 4 for the description of timing parameters Table 5 4 JTAG Configuration Timing Parameters Name Description Min Max Ttckftco Time from TCK falling edge to output 10ns Ttckftcx Time from SCLK falling edge to high impedance 10ns Ttckp TCK cloc...

Page 32: ... logic 1 and at least 5 strobes are input higher and then low at the TCK terminal the TAP logic is reset the TAP state machine in other states is converted into the state of test logic reset and the JTAG port and the test logic are reset Note The CPU and peripherals are not reset in this state Note The data on the TDO is valid from the falling edge of TCK in the Shift_DR or Shift_IR state The data...

Page 33: ...hine returns to Run Test Idle as shown in Figure 5 8 During the data register scanning operation the data or instructions are sent to the DR in the Shift_DR state as shown in Figure 5 9 The data is sent in LSB way or MSB way depending on specific operations Figure 5 8 Instruction Register Access Timing Figure 5 9 Data Register Access Timing Note The total length of the instruction register is 8 bi...

Page 34: ...9C h11005 h1100481B GW2A R 18 18C h00000 h0000081B GW2A 55 55C h00002 h0000281B The instruction for reading FPGA is 0x11 Take the GW1N 4B ID Code as an example to illustrate the working mode of JTAG please refer to the following steps 1 TAP reset TMS is set to high level and at least 5 clock cycles are continuously transmitted 2 Move the state machine from Test Logic Reset to Run Test Idle 3 Move ...

Page 35: ... When the 32 clock cycles are completed jump from Shift DR to Exit1 DR During this period sending 32 clocks can read 32 bits data that is 0x0100381B as shown in Figure 5 12 6 Move the state machine back to Run Test Idle Figure 5 10 Read Machine Flow Chart in ID Code State Start Move TAP to Shift IR Transfer Read ID Code 0x11 instruction LSB Move TAP to Exit1 IR End Move TAP to Update IR Move TAP t...

Page 36: ... link and reset TAP 2 Read the device ID CODE and check if it matches 3 Erase the SRAM if it has been configured Please refer to SRAM Erasure Process 4 Send the 0x15 instruction of ConfigEnable 5 Send the 0x12 instruction of Address Initialize 6 Send the 0x17 instruction of Transfer Configuration Data 7 Move the state machine to Shift DR Data Register Send Configuration Data from the MSB bit by bi...

Page 37: ...Read Flow Transfer Config Enable Instruction 0x15 Transfer Address Init Instruction 0x12 N Y SRAM Erase Option Process of Reading SRAM Warning SRAM data is not allowed to be read back by default Read the SRAM data from the SRAM area of the FPGA First ensure that the security bit is not configured when the data are written to the SRAM The security bit is used to protect the runtime data and ensure ...

Page 38: ...s is described in detail below as shown in Figure 5 14 1 Send the 0x15 instruction of ConfigEnable 2 Send the 0x12 instruction of Address Initialize 3 Send the 0x 03 instruction of SRAM Read 4 Move the state machine to Shift DR data register and send as many clocks as the value of the address length see Table 5 7 When the last clock is sent pull up TMS at the same time The state machine jumps to E...

Page 39: ...pute the checksum 16bit Transfer Config Disable Instruction 0x3A Transfer Config Enable Instruction 0x15 SRAM Erasure Process When reconfiguring SRAM the existing SRAM needs to be erased The flow is as follows 1 Send the 0x15 instruction of ConfigEnable 2 Send the 0x05 instruction of SRAM Erase 3 Send the 0x02 instruction of Noop 4 Delay or Run Test 2 10ms 5 Send the 0x09 instruction of SRAM Erase...

Page 40: ...ice TCK Frequency Range Process Code GW1N 1 GW1N 1S 1 4MHz 5MHz H GW1N RF 4B GW1N SER 4C GW1N R 9 C GW1NZ 1 1MHz 5MHz T GW1NS E 2 C 1MHz 5MHz S FPGA erasure process of T Technology The following describes the erase flow of T Technology for GW1NZ 1 in detail as shown in Figure 5 15 1 Establish a JTAG link and reset the TAP 2 Read the device ID CODE and check if it matches 3 Erase SRAM first if it h...

Page 41: ...Test 120 ms Transfer Config Disable Instruction 0x3A Transfer Read ID Code Instruction 0x11 Transfer Repogram Instruction 0x3C Transfer Noop Instruction 0x02 Note Ignore the shading area operation during Background Programming FPGA erasure process of H Technology FPGA erasure process of H Technology 1 Send the 0x15 instruction of ConfigEnable 2 Send the 0x75 instruction of EFlash Erase 3 Move the ...

Page 42: ...all 5 The clock Run Test is continuously generated in Run Test Idle for 120ms Please refer to Table 5 8 for the frequency requirements 6 Send the 0x3A instruction of ConfigDisabled 7 Send the 0x03 instruction of Reprogram to check if the erasing is successful 8 Send the 0x02 instruction of Noop to end the erasure process ...

Page 43: ...nsfer SRAM Erase Instruction 0x05 Transfer SRAM Erase Done Instruction 0x09 Transfer EFlash Erase Instruction 0x75 Run Test 96 ms Transfer Config Disable Instruction 0x3A Transfer Noop Instruction 0x02 Run Test 1ms GW1NS E 2 C Erasure Process of S Technology GW1NS E 2 C offers two built in Flash Note the different Flash when programming Refer to the process below 1 Check if the device ID is matche...

Page 44: ...ith the feature of background programming just need to use Autoboot pattern Autoboot pattern data must be inserted in the header of bitstream file in the case of no requirements of reading back data If an X page is less than 256Bytes you can use 0xFF or 0x00 to complement it The requirements for JTAG programming frequency are different according to the different processes of the embedded Flash in ...

Page 45: ...ify See Read EFlash Flow End Y N Transfer Noop Instruction 0x02 See ReadIDCode Same as FS file Y N Erase Flash Verify Y Program the first X page with readable pattem Erase Flash Transfer Reprogram Instruction 0 x 3C N Program Bitstream to pages one page have 64 X pages one X page have 4Y pages Process of Programming an X page The process of programming an X page is as shown in Figure 5 18 1 Send t...

Page 46: ... 0x13 the written in address is 00000000000000000000010011000000 The address data is written in LSB way Jump out of Shift DR at the last bit Figure 5 18 X page Programming Start End Delay 16000ns Program 1 X Page Transfer Config Enable Instuction 0x15 Transfer EF Program Instuction 0x71 Address index 0 Y Delay 16000ns in Run Test Idle Transfer address data LSB N Delay 6μS GW1N Z 2 4 6 9 Or 2400μS ...

Page 47: ...IFT DR Transfer 4 Bytes LSB Move Tap to Exit DR Update DR Run Test Idle Process of Reading internal Flash This chapter introduces the process of reading internal Flash briefly no rate requirements for the TCK of JTAG as shown in Figure 5 20 Reading the internal Flash can be regarded as the reverse process of programming Flash But firstly you should make sure that the written in Readable pattern ha...

Page 48: ... end the process Figure 5 20 Process of Reading Internal Flash Start Check ID Code See ReadIDCode Transfer Config Enable Instruction 0x15 Y N Y Transfer EF Read Instruction 0x73 Transfer address 0x0 data LSB Transfer Config Disable Instruction 0x3A End Read pages N Process of Reading a Page Y page Flash Reading a Y page is similar to writing a Y page but there is no waiting time for writing in Fla...

Page 49: ...uction 5 2 JTAG Configuration UG290 2 3E 40 87 Figure 5 21 Process of Reading a Y page Start Move TAP to SHIFT DR Transfer 4 Bytes all 0x0 and get Y page data from TDO data is LSB End Move TAP to Exit1 DR Update DR Run Test Idle ...

Page 50: ...ons And it can maintain the I O state when adding a new data stream file The following is the flow of GW1N4 that upgrades the internal Flash data using the Background Programming Figure 5 22 GW1N 4 Background Programming Flow Start Flash Erase Flash Program Verify Flash Readback Toggle reconfig_N pin Transfer JTAG Instructions Sample 0x01 Extest 0x04 End N NG Y Y Transfer JTAG Instructions NOOP 0x...

Page 51: ...hift IR Transfer Sample Instruction 0x01 Update IR Select DR Scan Exit1 DR Update DR Select DR Scan Shift IR Transfer Extest Instruction 0x04 Run TEST IDLE Update IR Capture DR End Note 1 Jump directly from Update IR to Select DR Scan ExFlash Programming Gowin FPGA can load bitstream files from external Flash and program external Flash through JTAG directly ...

Page 52: ... of programming external Flash via JTAG Program External Flash via JTAG SPI In this mode the external Flash can be programed via JTAG The principle of this mode is to convert JTAG protocol to SPI protocol and then program external Flash Users program SPI Flash by simulating Master SPI timing through JTAG Figure 5 25 Process View of Programming SPI Flash SPI Start Check ID Code See RaadIDCode Progr...

Page 53: ...ple of this mode is changing the state of the pins connected to SPI by using Boundary Scan method to implement SSPI timing and then to program the internal Flash The length of the Boundary Scan Chain used in this mode is 8 bits Every two bits combination corresponds to the pin state as shown in Table 5 10 One SCLK drive is completed every two times of sending Boundary Scan Chain Table 5 10 Pin Sta...

Page 54: ...means input data 0 means low 1 means high Figure 5 28 Process of Use Boundary Scan Mode To Program SPI Flash Start Check ID Code See RaadIDCode Transfer BSCAN_2_SPI Instruction 0x3D Program or read SPI through JTAG End Y N Transfer Config Disable Instruction 0x3A Transfer Config Enable Instruction 0x15 ...

Page 55: ...its the read instruction is 0x41 and the timing is the same as that of Read ID Code The meaning of the Status Register is shown in Table 5 11 Table 5 11 Status Register Definition Device Status Register 31 0 GW1N R 1 2 4 GW1NS 2 GW1NS R 2C GW1N R 6 9 GW1NZ 1 GW2A 18 55 0 CRC Error 1 Bad Command Error 2 ID Verify Failed Error 3 Timeout Error 4 0 5 6 7 8 9 0 10 11 12 Gowin VLD 1 0 13 Done Final 14 S...

Page 56: ...Diagram of Daisy Chain Figure 5 29 Connection Diagram of Daisy Chain Routine File For the routine file please contact GOWINSEMI technical support or the local office 5 3 AUTO BOOT Configuration Supported by LittleBee Family Only The AUTO BOOT mode is a configuration mode for momentary connection feature of non volatile LittleBee family of FPGA Products The Arora Family of FPGA products do not supp...

Page 57: ... the SRAM to complete AUTO BOOT after the built in Flash is programmed using Gowin programmer The momentary connection feature of the built in Flash saves download time and improves productivity GW1N R 9 and GW1NS series support two retries of AUTO BOOT configuration i e the devices can be automatically reconfigured twice if the first configuration fails after power up The other devices of LittleB...

Page 58: ...d and configured Low level Programming configuration for FPGA is prohibited DONE I O High level pulse Successfully programmed and configured Low level pulse Programming and configuration uncompleted or failed MODE 2 0 I Internal weak pull up Configuration mode selection READY rising edge sampling SCLK I Input clock CLKHOLD_N I Internal weak pull up High level SPI operation corresponding to SCLK is...

Page 59: ...dge to high impedance 10ns Tcsnhw CSN high time 25ns Treadytcsl Time from READY rising edge to CSN low TBD Treadytsclk Time from READY rising edge to first SCLK edge TBD Other than the power requirements the following conditions need to be met to use the SSPI configuration mode SSPI port enable RECONFIG_N is not set as a GPIO during the first configuration after power up or the previous programmin...

Page 60: ...Code 0x41000000 Reconfig Reprogram 0x3C00 Write Enable 0x1500 Write Disable 0x3A00 Write Data 0x3B Program SPI Flash 0x1600 Init Address 0x1200 Erase SRAM 0x0500 Read ID Code The length of FPGA ID Code is 32bits The instruction to read ID is four bytes that is 0x11000000 Before sending instructions keep CS at a high level and generate multiple clocks more than two to let FPGA get CS state After CS...

Page 61: ...ming mode using Write Enable 0x15 instruction to receive the Write Data 0x3B instructions Figure 5 32 Write Enable 0x15 Timing Note At CS high level more than two clocks should be given to SCLK to drive FPGA to identify CS signal This rule also applies to other instructions Write Disable 0x3A00 After finishing sending data exit programming mode using Write Disable After exiting the device can be a...

Page 62: ...eprogram 0x1500 Write Enable 0x3A000 Write Disable 0x1600 Program SPI Flash 0x1200 Init Address 0x0500 Erase SRAM In addition SSPI is driven by an external clock so if CS is at high before and after these instructions more than two clocks are needed to enable FPGA to collect the state of CS Write Data 0x3B The fs file is sent directly to the FPGA device using the Write Data 0x3B instruction Note t...

Page 63: ...in programmer The connection diagram for programming an external Flash via SSPI is shown in Figure 5 36 Figure 5 36 Connection Diagram of Programming External Flash via SSPI FPGA CLKHOLD_N SCLK MCLK SSPI_CS_N MCS_N SI MI SO MO Host CTRL CLK CS_N DOUT DIN Flash CLK CS_N DOUT DIN Note All Arora family devices support programming external Flash via SSPI For the LittleBee family devices currently only...

Page 64: ...nfiguration Mode Introduction 5 4 SSPI UG290 2 3E 55 87 Figure 5 37 The Flow of Programming External Flash via SSPI Start Transfer Program SPI Flash Instruction 0x1600 Program Flash following SPI timing End ...

Page 65: ... Master and reads bitstream data from the external Flash via SPI port to complete configuration MSPI Configuration Process Set the MODE pin to MSPI status power on again or trigger RECONFIG_N at one low level pulse and the device will read bitstream data from the external Flash and complete configuration automatically According to the MSPI configuration features remote upgrade requirements can be ...

Page 66: ... DONE I O High level pulse Successfully programmed and configured Low level pulse Programming and configuration uncompleted or failed MODE 2 0 I Internal weak pull up MODE select signal READY rising edge sample MCLK O FPGA output clock MCS_N O Chip selection signal active low MO O FPGA outputs data to Slave MI I Input data to FPGA through Slave FASTRD_N I READY signal rising edge sampling High lev...

Page 67: ...ncy is less than 30 MHz The connection diagram for programming data to external Flash is shown in Figure 5 41 The connection diagram for programming external Flash via the SSPI interface is shown in Figure 5 36 Figure 5 41 Connection Diagram of JTAG Programming External Flash FPGA TDI MCLK TCK MCS_N TMS MI TDO MO JTAG PORT Flash CLK CS_N DOUT DIN 4 7K Note The figure above shows the minimum system...

Page 68: ...dresses in one same external Flash Currently the Gowin Programmer software supports the ability to program multiple bitstream data to external Flash without erasure and the initial programming address is 0 The loading address of the latter bitstream data is written in previous bitstream data and the configuration is completed by triggering RECONFIG_N to switch the data stream file under the condit...

Page 69: ...urations to ensure that the start address is not covered by the previous bitstream data The lower 12 bits of an SPI Flash start address is invalid and the address space of ADDR 23 12 can be set by users In addition to the introduction of configuring one FPGA via one Flash Gowin FPGA products also support configuring multiple FPGAs with one Flash The FPGA directly connected to the SPI Flash adopts ...

Page 70: ...ntroduction 5 5 MSPI UG290 2 3E 61 87 Figure 5 44 Connection Diagram for Configuring Multiple FPGAs via Single Flash MSPI Configuration Timing MSPI Download Timing is as shown in Figure 5 45 Figure 5 45 MSPI Download Timing ...

Page 71: ...mclk Time from READY rising edge to first MCLK edge 2 8μs 4 4μs Other than the power requirements the following conditions need to be met to use the MSPI configuration mode MSPI port enable RECONFIG_N is not set as a GPIO during the first configuration after power up or the previous programming Initiate new configuration Power on again or trigger RECONFIG_N at one low pulse Figure 5 46 Multiple FP...

Page 72: ...o built in Flash in Dual BOOT mode The Dual Boot mode configuration flow is shown in Figure 5 47 Figure 5 47 Dual Boot Flow Chart start ready emFlash fail exFlash fail Y N Y end N fail success Y N Note When the MODE value is set to 110 the FPGA first attempts to configure from the external Flash GW1N R 9 and GW1NS series products support four times configuration in all DUAL BOOT modes Start from t...

Page 73: ... shown in Table 5 17 Table 5 17 CPU Mode Pins Pin Name I O Description RECONFIG_N I internal weak pull up Low level pulse Start GowinCONFIG READY I O High level pulse The device can be programmed and configured Low level Programming configuration for device is prohibited DONE I O High level Successfully programmed and configured Low level Programming and configuration uncompleted or failed MODE 2 ...

Page 74: ...er up or the previous programming Initiate new configuration Power on again or trigger RECONFIG_N at one low pulse 5 7 1 Configuration Timing Before configuration make sure that MODE 2 0 111 and DONE will be pulled up after configuration If DONE or READY is pulled down the configuration fails In the configuration process data bus D 7 0 is the MSB mode and the FPGA reads the data at the SCLK rising...

Page 75: ... configuration uncompleted or failed MODE 2 0 I internal weak pull up Configuration mode selection READY rising edge sampling SCLK I Input clock DIN I internal weak pull up Input data DOUT O Output data only used in SERIAL configuration mode when FPGA cascading The connection diagram for the SERIAL mode is shown in Figure 5 50 Figure 5 50 Connection Diagram for SERIAL Mode FPGA SCLK DIN Host CLK D...

Page 76: ...figuration modes that use the least number of pins The I2 C mode can only write bitstream data to FPGA and cannot readback data from FPGA devices as such the I2 C mode cannot read information on the ID CODE USER CODE status register and read back check A definition of the pins employed in the I2 C mode is provided in Table 5 20 Table 5 20 Pin Definition in SERIAL Configuration Mode Pin Name I O De...

Page 77: ...aster sends data to the slave 0 or reads data from the slave 1 ACK ACK NACK 位 Each frame in the message is followed by an ACK NACK bit and Gowin FPGA returns 0 if correct DATA Data A data has 8bits and the most significant bit is sent first All DATA on the I2C bus is transmitted in 8 bit bytes Each byte sent by the transmitter it releases the DATA line during the clock pulse 9 and the receiver sen...

Page 78: ...low The list of I2 C mode supported by Gowin FPGA devices is as shown in the table below Mode Device Frequency Address SRAM GW1N 2 IDCode 0x0120681B 100Khz 1 33Mhz 7 b1010_000 Embedded Flash GW1N 2 IDCode 0x0120681B 1 33Mhz 1 7 b1011_000 External Flash Note If you use I 2 C to write Flash the bitstream file needs to be conveted into specific bitstream file first The conversion tool is included in ...

Page 79: ... the FPGA bitstream file and the security bit is set During the process of data configuration input data is checked in real time The wrong data cannot wake up the device and the DONE signal is pulled down After the configuration of the bitstream with security bit is complete data readback cannot be performed 6 1 Configuration Options Please refer to Figure 6 1 for the related configuration data se...

Page 80: ... FPGA products support bitstream data encryption using the 128 AES encryption algorithm Please refer to the following steps for the data encryption configuration 1 Enter the encryption KEY KEY in Gowin software interface to generate the bitstream data 2 Enter the decryption key in Gowin Programmer 3 After encrypted bitstream data is loaded into the device FPGA compares the data that has been loade...

Page 81: ...ption KEY Refer to the steps below to write the encryption keys in Gowin software 1 Open the corresponding project in Gowin software 2 Select Project Configuration Dual Purpose Pin from the available menu options 3 Click BitStream check Enable Encryption only support GW2A and input the key value as shown in Figure 6 2 Figure 6 2 Encryption Key Setting Method After setting the encryption key succes...

Page 82: ...rformed this action any read and write key operations will be invalid the key value cannot be modified and all read bits are all 1 After the decryption key is set the encrypted bitstream data will only work when the data matches the decryption key The key does not affect the non encrypted bitstream data Note The initial value of the Gowin FPGA keys is 0 If a key value is changed to 1 it cannot be ...

Page 83: ... Write 1 Write the user defined Key to the text box in the figure above 2 Click Write button 3 Return the validation result after running Read Click Read button to validate the written AES encryption key again The Key that is read from the tool will be displayed in the text box in the figure above Lock Click Lock to lock the read and write permission of Key If it is locked the Key cannot be read o...

Page 84: ...ocol Check ID CODE Check the device ID to determine whether the JTAG protocol works properly and whether the programing object is correct to avoid misoperation Figure 6 5 Prepare Start Check ID Transmit Read ID Command 0x11 Read 32 Bits ID match Stop Yes No Yes No The sign can be A To read AES key flow B To program AES key flow C To lock AES key or Set Key2 selected flow ...

Page 85: ...am File Configuration UG290 2 3E 76 87 Read AES Key Figure6 6 Read AES Key Flow Transmit Read Key Command 0x25 Read 128 Bits Delay 100 ms Stop A Transmit ISC Enable Command 0x15 Transmit ISC Disable Command 0x3A ...

Page 86: ...rogram AES Key Figure 6 7 Program AES Key Flow Transmit Program EFuse Command 0x24 Transmit Program Key Command 0x29 Transmit 128bits Delay 800 ms Transmit Read ID Command 0x11 Stop Transmit ISC Enable Command 0x15 Transmit ISC Disable Command 0x3A B ...

Page 87: ...m data The file with a bin suffix is a binary format file with no annotations This binary format file is commonly used for embedded programming Users can configure the bitstream file format in Gowin software 1 Open the Gowin software Transmit Program EFuse Command 0x24 note Start the 2 5 V circuit to get the voltage ready before program efuse Transmit Security Command 0x23 Transmit 128 bits of dat...

Page 88: ...Size 1 152 84 KBytes 4 608 217 KBytes 8 640 435 KBytes 20 736 887 KBytes 54 720 2269 KBytes Note The data in the table is the file size in binary format and the configuration file is not compressed If SPI Flash is used to store bitstream file memory margin is required 6 4 Configuration File Loading Time Gowin FPGA can be used as Master to read bitstream files from Flash and configure SRAM includin...

Page 89: ... Fast Read SPI 0x0B is used The LittleBee family devices support not only MSPI mode but also Autoboot mode The loading frequency is 2 5 MHz by default and Autoboot mode loads one byte 8 bits per clock The loading time varies depending on the configuration file size load frequency and per clock loading width Due to the different process of the embedded Flash the maximum Autoboot loading frequency f...

Page 90: ...tion UG290 2 3E 81 87 Device Max Loading Frequency of Autoboot Max Loading Frequency of MSPI GW1N 2B GW1NSER 4C GW1NS 4 GW1NSR 4 GW1NS 4C GW1NSR 4C GW1N 4B GW1NR 4B GW1NRF 4B GW1N 4 GW1NR 4 GW1N 6 GW1N 9 GW1N 9C GW1NR 9 GW1NR 9C ...

Page 91: ...ation File Loading Time ms when frequency 2 5 MHz default frequency Loading Time ms when Frequency 25 MHz Loading Time ms when Frequency 31 25 MHz 1 152 84 KBytes 34 4 3 4 608 217 KBytes 88 9 7 8 640 435 KBytes 178 17 14 What is listed above is the reference of loading time From power on to configuration completion of the device in addition to the configuration time there are also the power on tim...

Page 92: ...used to configure Gowin FPGA by following the steps outlined below 1 Connect the device that needs to be configured 2 Start Gowin programmer to start scanning and the connected FPGA devices can be identified automatically 3 Select the bitstream and configuration mode to configure the device During the process outlined above Gowin programmer will read the connected device ID first and then compare ...

Page 93: ...interface After Configuration After configuration the device bitstream will be loaded to the SRAM or on chip Flash according to the configuration mode selected On chip Flash is supported by the LittleBee Family of FPGA products only If the data is loaded to the SRAM Gowin software will set the security bit automatically in the process of bitstream generation and no user can read SRAMs If the data ...

Page 94: ... file for device testing The short chain is mainly used to erase and read and write the external Flash on the FPGA chain To perform a boundary scan follow the steps outlined below 1 Connect the FPGA development board to the PC and then power up 2 Open Gowin programmer and scan the connected devices 3 Double click in the Operation field and select External Flash Mode and the related bscan operation...

Page 95: ...matic Diagram The boundary scan operation can only be performed on the external Flash of FPGA and cannot be used to program the embedded Flash or SRAM This operation is irrelevant with the FPGA MODE value but it is slower than that of the external Flash programming via JTAG ...

Page 96: ...are as shown in Table 9 1 Gowin FPGA can read data from this Flash Table 9 1 SPI Flash Operation Instruction Operation Instruction Read 0x03 Fast_Read 0x0B Note The Flash read instructions supported by Gowin FPGA must have at least one 03 or 0B Use the regular reading instruction if the clock frequency is no higher than 30 MHz Use the fast reading instruction if the clock frequency is higher than ...

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