3 FPGA Circuits
3.4 Clock, Reset
DBUG398-1.1E
13(25)
3.4
Clock, Reset
3.4.1
Overview
A 50MHz crystal oscillator is provided in the development board that
connects to the PLL input pin. This can be employed as the input clock for
the PLL in FPGA, and the output clock as needed via multiplication and
division of the PLL frequency.
To facilitate testing, a SMA socket is reserved on the development
board as the clock input interface. The clock signal is connected to the
FPGA global clock pin.
3.4.2
Clock, Reset
Figure 3-3 Clock, Reset
6
56
92
KEY5
50MHz
ADM811
JC3.660.046
3.3V
FPGA_RST_N
F_CLK_SMA
FPGA_CLK
U6
U7
J7
X2
3.4.3
Pinout
Table 3-3 FPGA Clock and Reset Pinout
Signal Name
Pin No.
BANK
Description
I/O
FPGA_CLK
6
3
50MHz crystal oscillator
Input
3.3V, 2.5V, 1.2V
F_CLK_SMA
56
2
External clock input
3.3V, 2.5V, 1.2V
FPGA_RST_N
92
1
Reset signal, active low
3.3V, 2.5V
Note!
The VCCO1 of GW1N-9 can only be supplied with 3.3V.
3.5
LED
3.5.1
Overview
Four green LEDs are incorporated into the development board and are
used to display the required status. In addition, two LEDs are reserved to
