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GOWIN DK_START_GW2AR-LV18EQ144PC8I7, User Manual

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3 Development Board Circuit 

3.10 Ethernet 

 

DBUG405-1.0E 

21(25) 

 

Signal Name 

Pin No. 

Socket Pin No. 

BANK 

Description 

I/O 

F_LVDS_B2_N  116 

6 

1 

B Channel 2– 

3.3V 

GND 

- 

7 

- 

- 

- 

GND 

- 

8 

- 

- 

- 

F_LVDS_B3_P  115 

9 

1 

B Channel 3+ 

3.3V 

F_LVDS_B3_N  114 

10 

1 

B Channel 3– 

3.3V 

GND 

- 

11 

- 

- 

- 

GND 

- 

12 

- 

- 

- 

F_LVDS_B4_P  113 

13 

1 

B Channel 4+ 

3.3V 

F_LVDS_B4_N  112 

14 

1 

B Channel 4– 

3.3V 

GND 

- 

15 

- 

- 

- 

GND 

- 

16 

- 

- 

- 

F_LVDS_B5_P  110 

17 

1 

B Channel 5+ 

3.3V 

F_LVDS_B5_N  110 

18 

1 

B Channel 5– 

3.3V 

GND 

- 

19 

- 

- 

- 

GND 

- 

20 

- 

- 

- 

3.10

 

Ethernet 

3.10.1

 

Overview 

Two Ethernet interfaces are reserved for FPGA to communicate with 

PC or the other external devices. 

3.10.2

 

Ethernet Circuit 

Figure 3-9 Ethernet Download Connection 

PHY1_TXD3

Ethernet  PHY 

65

66

U9

J7

RJ45

PHY1_TXEN

67

PHY1_RXC

U5

PHY1_RXD0

PHY1_RXD1

PHY1_RXD2

PHY1_RXD3

PHY1_TXD1

PHY1_TXD2

PHY1_GTCLK

PHY1_TXD0

PHY1_RXDV

PHY_MDC

PHY_MDIO

62

63

64

46

61

45

68

69

70

71

72

GW2AR-

LV18EQ144PC8I7

 

Summary of Contents for DK_START_GW2AR-LV18EQ144PC8I7

Page 1: ...DK_START_GW2AR LV18EQ144PC8I7_V1 1 User Guide DBUG405 1 0E 09 06 2021...

Page 2: ...are trademarks of GOWINSEMI and are registered in China the U S Patent and Trademark Office and other countries All other words and logos identified as trademarks or service marks are the property of...

Page 3: ...Revision History Date Version Description 09 06 2021 1 0E Initial version published...

Page 4: ...scription 3 2 1 Overview 3 2 2 A Development Board Suite 4 2 3 PCB Components 5 2 4 System Architecture 5 2 5 Features 6 2 6 Development Board Specification 7 3 Development Board Circuit 9 3 1 FPGA Mo...

Page 5: ...rview 14 3 6 2 Switch Circuit 14 3 6 3 Pinout 14 3 7 Key 15 3 7 1 Overview 15 3 7 2 Key Circuit 15 3 7 3 Pinout 15 3 8 GPIO 15 3 8 1 Overview 15 3 8 2 GPIO Circuit 16 3 8 3 Pinout 17 3 9 LVDS 19 3 9 1...

Page 6: ...e 2 3 PCB Components 5 Figure 2 4 System Architecture 5 Figure 3 1 Connection Diagram for FPGA USB Downloading 10 Figure 3 2 Power System Distribution 11 Figure 3 3 Clock Reset 13 Figure 3 4 LED Circu...

Page 7: ...2 FPGA Power Pinout 12 Table 3 3 FPGA Clock and Reset Pinout 13 Table 3 4 LED Pinout 14 Table 3 5 Clock Circuit Pinout 14 Table 3 6 Key Pinout 15 Table 3 7 J5 GPIO Pinout 17 Table 3 8 J14 GPIO Pinout...

Page 8: ...of the development board Introduction to the use of the software 1 2 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi...

Page 9: ...nput Look up Table LUT7 7 input Look up Table LUT8 8 input Look up Table REG Register ALU Arithmetic Logic Unit IOB Input Output Block SSRAM Shadow Static Random Access Memory BSRAM Block Static Rando...

Page 10: ...orm of SIP chip The main difference between the GW2A series and the GW2AR series is that the GW2AR series integrates abundant memories The GW2AR series also provides high performance DSP resources a h...

Page 11: ...G405 1 0E 4 25 2 2 A Development Board Suite A development board suite includes the following items DK_START_GW2AR LV18EQ144PC8I7_V1 1 development board USB cable Figure 2 2 A Development Board Kit 1...

Page 12: ...LED Switches Reset Mode Control FPGA Download 5V IN FLASH FPGA GPIO LVDS Power on off Ethernet 1 8V 2 4 System Architecture Figure 2 4 System Architecture 4 LED 2 SWITCH OSC 50MHz MINI USB 5Pairs LVDS...

Page 13: ...nfiguration Mode JTAG MSPI Multi BOOT 3 Clock resource 50MHz Clock Crystal Oscillator 4 Key switch and slide switch One reset button Two key switches Two slide switches 5 LED One power indicator green...

Page 14: ...Slide Switches Available for testing 2 5 Key Switches Available for testing 2 6 Reset button Reset for FPGA 1 7 LED Test indicator DONE indicator Power indicator Four Test indicators green One DONE in...

Page 15: ...6 Development Board Specification DBUG405 1 0E 8 25 No Item Functions Technical Conditions Note outlet 2A self recovery fuses are connected at power inlet 14 Voltage Input Voltage 5V 15 Humidity 95 16...

Page 16: ...mation please refer to UG229 GW2AR series of FPGA Products Package and Pinout 3 2 Download 3 2 1 Overview The development board provides an USB download interface The data stream file can be downloade...

Page 17: ...J26 on the development board Set J13 to 0 and set J9 and J10 to 1 Power on Open the Programmer select External Flash mode and then select the bitstream file you required Turn off the power after down...

Page 18: ...d to step down voltage from 5V to 3 3V 1 8V and 1 0V which can meet the power demand of the development board 3 3 2 Power System Distribution Figure 3 2 Power System Distribution DC5V TPS7A7001 LDO 1...

Page 19: ...VCCPLLR0 104 PLLR0 power 1 0V VCCPLLR1 81 PLLR1 power 1 0V VCCPLL1 36 PLLL1 power be internal short circuited 1 0V VCCX 31 55 Auxiliary voltage The auxiliary voltage and VCCO4 VCCO6 are internal shor...

Page 20: ...T_N 135 0 Reset signal active low 1 8V 3 5 LED 3 5 1 Overview Four green LEDs are incorporated into the development board and are used to display the required status In addition two LEDs are reserved...

Page 21: ...8 0 JESD 4 3 3V 3 6 Switches 3 6 1 Overview Two Slide switches are incorporated into the development board These are used to input the 0 1 signal during testing 3 6 2 Switch Circuit Figure 3 5 Switch...

Page 22: ...0 Input 1 when the key is up 3 7 2 Key Circuit Figure 3 6 Key Circuit 129 130 KEY1 KEY2 U9 F_KEY1 F_KEY2 VCC3P3 GW2AR LV18EQ144PC8I7 3 7 3 Pinout Table 3 6 Key Pinout Signal Name Pin No BANK Descript...

Page 23: ...1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 VCC5P0 H_A_IO7 H_A_IO9 H_A_IO11 H_A_IO13 H_A_IO15 H_A_IO8 H_A_IO10 H_A_IO12 H_A_IO14 H_A_IO16 J14 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20...

Page 24: ...9 6 General I O 3 3V H_A_IO5 10 10 7 General I O 1 8V Table 3 8 J14 GPIO Pinout Signal Name Pin No Socket Pin No BANK Description I O GND 1 GND VCC5P0 2 5V Output 5V GND 3 0 GND VCC5P0 4 0 5V Output 5...

Page 25: ...General I O 3 3V H_A_IO26 44 25 5 General I O 3 3V H_A_IO25 42 26 5 General I O 3 3V Table 3 9 J2 GPIO Pinout Signal Name Pin No Socket Pin No BANK Description I O GND 1 GND GND 2 GND H_B_IO0 105 3 2...

Page 26: ...O 3 3V H_B_IO20 78 17 3 General I O 3 3V H_B_IO19 82 18 3 General I O 3 3V H_B_IO22 76 19 3 General I O 3 3V H_B_IO21 79 20 3 General I O 3 3V 3 9 LVDS 3 9 1 Overview Two 2 0 mm DC3 20P sockets are re...

Page 27: ...annel 2 3 3V GND 7 GND 8 F_LVDS_A3_P 134 9 0 A Channel 3 3 3V F_LVDS_A3_N 133 10 0 A Channel 3 3 3V GND 11 GND 12 F_LVDS_A4_P 132 13 0 A Channel 4 3 3V F_LVDS_A4_N 131 14 0 A Channel 4 3 3V GND 15 GND...

Page 28: ...3V GND 15 GND 16 F_LVDS_B5_P 110 17 1 B Channel 5 3 3V F_LVDS_B5_N 110 18 1 B Channel 5 3 3V GND 19 GND 20 3 10 Ethernet 3 10 1 Overview Two Ethernet interfaces are reserved for FPGA to communicate wi...

Page 29: ...V PHY1_TXD1 63 4 RGMII MII transmitter data 3 3V PHY1_TXD2 64 4 RGMII MII transmitter data 3 3V PHY1_TXD3 65 4 RGMII MII transmitter data 3 3V PHY1_TXEN 66 4 RGMII MII transmitting enable 3 3V PHY1_RX...

Page 30: ..._TXD3 51 5 RGMII MII transmitter data 3 3V PHY2_TXEN 52 5 RGMII MII transmitting enable 3 3V PHY2_RXC 54 5 RGMII MII receive clock 3 3V PHY2_RXD0 56 4 RGMII MII receive data 3 3V PHY2_RXD1 57 4 RGMII...

Page 31: ...dle with care and pay attention to electrostatic protection 2 When you program the external FLASH please refer to the MODE value in UG290 Gowin FPGA Products Programming and Configuration User Guide 3...

Page 32: ...5 Gowin Software DBUG405 1 0E 25 25 5 Gowin Software For the details you can see SUG100 Gowin Software User Guide...

Page 33: ......

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