3 Development Board Circuit
3.4 Clock, Reset
DBUG385-1.1E
11(23)
3.4
Clock, Reset
3.4.1
Introduction
The development board offers a 50MHz oscillator, connecting to the
global clock pins. It also offers a female SMA seat for users to input the
external clock for multiple tests.
The reset circuit adopts keys and dedicated reset chips. After powered
on the device, the reset chip automatically generates a reset signal to reset
the FPGA and Ethernet PHY chip. The 3.3V voltage is monitored in real
time. The reset signal will be generated once an exception occurs. The
reset signal can also be generated via the reset key.
Figure 3-3 Connection Diagram of Clock and Reset
H11
T15
T10
KEY1
50MHz
ADM811
EXT CLK
3.3V
RST_N
CLK_SMA
CLK_G
3.4.2
Pinout
Table 3-2 Clock and Reset Pinout
Signal Name
FPGA Pin No. BANK
I/O
Description
CLK_G
H11
0
2.5V
50MHz crystal oscillator Input
CLK_SMA
T15
2
3.3V
External clock input
RST_N
T10
3
3.3V
Reset signal, active low
3.5
DDR3
3.5.1
Introduction
The development board includes a DDR3 chip with 2Gbit storage
space, 16 bits data bus width, and the highest data speed of 1600MT/s.
