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GOWIN DK_START_GW1NSR-LX2CQN48PC5I4_V 2.1, User Manual

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GOWIN DK_START_GW1NSR-LX2CQN48PC5I4_V 2.1 User Manual Download Page 20

3 Development Board Circuit 

3.4 Clock, Reset 

 

DBUG401-1.0E 

13(22) 

 

3.3.1

 

Pinout 

Table 3-2 FPGA Power Pinout     

Signal Name 

Pin No. 

BANK 

Description 

I/O 

VCCO0 

1 

0 

I/O Bank Power 

1.8V/3.3V 

VCCO1 

25 

1 

I/O Bank Power 

2.5V 

VCCO2 

13 

2 

I/O Bank Power 

1.2V/2.5V 

VCCO3 

1 

3 

I/O Bank Power 

1.8V/3.3V 

VCCX 

8, 36 

- 

Auxiliary voltage 

1.8/3.3V 

VCC 

12, 37 

- 

Core voltage 

1.2V 

VSS 

2, 26 

- 

GND 

- 

3.4

 

Clock, Reset 

3.4.1

 

Overview 

A 50MHz crystal oscillator is provided in the development board that 

connects to the PLL input pin. This can be employed as the input clock for 
the PLL in FPGA, and the output clock as needed via multiplication and 
division of the PLL frequency. 

3.4.2

 

Clock, Reset 

Figure 3-3 Clock, Reset 

35

14

KEY3

50MHz

ADM811

3.3V

FPGA_RST_N

FPGA_CLK

U1

U2

X2

GW1NSR-

LX2CQN48PC5I4_V2.1

 

3.4.3

 

Pinout 

Table 3-3 FPGA Clock and Reset Pinout 

Signal Name 

Pin No. 

BANK 

Description 

I/O 

FPGA_CLK 

35 

1 

50MHz crystal oscillator Input 

2.5V 

FPGA_RST_N 

34 

1 

Reset signal, active low 

2.5V 

Summary of Contents for DK_START_GW1NSR-LX2CQN48PC5I4_V 2.1

Page 1: ...DK_START_GW1NSR LX2CQN48PC5I4_V 2 1 User Guide DBUG401 1 0E 08 19 2021 ...

Page 2: ...s are trademarks of GOWINSEMI and are registered in China the U S Patent and Trademark Office and other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your ...

Page 3: ...Revision History Date Version Description 08 19 2021 1 0E Initial version published ...

Page 4: ... Description 4 2 1 Overview 4 2 2 A Development Board Suite 5 2 3 PCB Components 6 2 4 System Architecture 6 2 5 Features 7 2 6 Development Board Specification 8 3 Development Board Circuit 10 3 1 FPGA Module 10 Overview 10 I O BANK Introduction 10 3 2 Download 10 3 2 1 Overview 10 3 2 2 USB Download Circuit 11 3 2 3 Download Flow 11 3 2 4 Pinout 11 3 3 Power Supply 11 3 3 1 Overview 11 3 3 2 Powe...

Page 5: ...cuit 14 3 5 3 Pinout 14 3 6 Key 14 3 6 1 Overview 14 3 6 2 Key Circuit 15 3 6 3 Pinout 15 3 7 GPIO 15 3 7 1 Overview 15 3 7 2 GPIO Circuit 15 3 7 3 Pinout 16 3 8 MIPI LVDS 16 3 8 1 Overview 16 3 8 2 MIPI LVDS Circuit 16 3 8 3 Pinout 17 3 9 ADC 18 3 9 1 Overview 18 3 9 2 ADC Circuit 19 3 9 3 Pinout 19 4 Considerations 20 5 Gowin Software 21 6 Quick Start 22 ...

Page 6: ...t Board Suite 5 Figure 2 3 PCB Components 6 Figure 2 4 System Architecture 6 Figure 3 1 Connection Diagram for FPGA USB Downloading 11 Figure 3 2 Power System Distribution 12 Figure 3 3 Clock Reset 13 Figure 3 4 LED Circuit 14 Figure 3 5 Key Circuit Diagram 15 Figure 3 6 GPIO Circuit 15 Figure 3 7 LVDS Circuit 16 Figure 3 8 ADC Circuit 19 ...

Page 7: ...elopment Board Specification 8 Table 3 1 FPGA Download and Pinout 11 Table 3 2 FPGA Power Pinout 13 Table 3 3 FPGA Clock and Reset Pinout 13 Table 3 4 LED Pinout 14 Table 3 5 Key Pinout 15 Table 3 6 J14 GPIO Pinout 16 Table 3 7 J15 FPGA Pinout 17 Table 3 8 J16 FPGA Pinout 17 Table 3 9 J15 ADC Pinout 19 ...

Page 8: ...development board Introduction to the use of the FPGA development software 1 2 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS861 GW1NSR series of FPGA Products Data Sheet 2 UG863 GW1NSR series of FPGA Products Package and Pinout 3 UG862 GW1NSR 2 2C Pinout 4 UG290 Gowin FPGA Products Programming and Config...

Page 9: ...ation Trace Module TUIP Trace Port Interface Unit USB Universal Serial Bus PHY Physical Layer ADC Analog to Digital Converter SAR Successive Approximation Register SFDR Spurious free Dynamic Range SINAD Signal to Noise And Distortion LSB Least Significant Bit INL Integral Nonlinearity DNL Differential Nonlinearity CFU Configurable Function Unit CLS Configurable Logic Slice CRU Configurable Routing...

Page 10: ...Quadrant Clock Enable DCS Dynamic Clock Selector PLL Phase locked Loop DLL Delay locked Loop LQ144 LQFP144 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly using the information provided below Website www gowinsemi com E mail support gowinsemi com ...

Page 11: ...sor is employed as the core the needs of the Min memory can be met FPGA logic resources and other embedded resources can flexibly facilitate the peripheral control functions which provide excellent calculation functions and exceptional system response interrupts They also offer high performance low power consumption flexible usage instant start up affordability nonvolatile high security and abunda...

Page 12: ...G401 1 0E 5 22 2 2 A Development Board Suite A development board suite includes the following items DK_START_GW1NSR LX2CQN48PC5I4_V2 1 development board USB cable Figure 2 2 A Development Board Suite 1 2 DK_START_GW1NSR LX2CQN48PC5I4_V2 1 development board USB Cable ...

Page 13: ... FPGA Download 5V IN FPGA 1 8V LVDS LVDS 2 5V Select FPGA ARM Download 2 4 System Architecture Figure 2 4 System Architecture 2 LED Share I Os with BUTTON OSC 50MHz 5Pairs LVDS MIPI INPUT 2 BUTTON 5Pairs LVDS MIPI OUTPUT 20PIN GPIO JTAG Interface ARM JTAG FPGA JTAG 10PIN GPIO 8 CH ADC INPUT Share I Os with differential input GW1NSR LX2CQN48PC5I4_V2 1 ...

Page 14: ...des and capacities of B SRAM 2 FPGA Configuration Mode JTAG AUTO BOOT 3 Clock resource 50MHz Clock Crystal Oscillator 4 Key switch and slide switch One reset button One key switches 5 LED One power indicator green One DONE indicator green 2 LEDs green 6 Memory 1Mbit built in Flash 32Mbit built in PSRAM 7 MIPI LVDS 5 pairs of MIPI LVDS differential input 4 pairs of MIPI LVDS differential output 8 G...

Page 15: ... circuit and other circuits via 5V 3 3 V circuit Provide power for FPGA via the 5V to 2 5V circuit Provide power for FPGA via the 5V to 1 8V circuit Provide power to FPGA core via 5 V 1 2 V circuit 4 Key Switches Available for testing 1 5 Reset button Reset for FPGA 1 6 LED Test indicator DONE indicator Power indicator Two green test indicators share I O resources with keys One DONE indicator gree...

Page 16: ...output 11 Protection USB interface ESD protection Power interface Inverse current and over current protection USB interface ESD protection 15kV non contact discharge 8kV contact discharge Schottky diode is connected between positive and negative anodes of power outlet 2A self recovery fuses are connected at power inlet 12 Voltage Input Voltage 5V 13 Humidity 95 14 Temperature Operating range 20 70...

Page 17: ...W1NSR series of FPGA products please refer to UG863 GW1NSR series of FPGA Products Package and Pinout 3 2 Download 3 2 1 Overview The development board provides an USB download interface The data stream file can be downloaded to the internal SRAM or internal flash as needed Note When downloaded to SRAM the data stream file will be lost if the device is power down and it will need to be downloaded ...

Page 18: ...the J Link ARM emulator to the ARM JTAG interface J8 Note Before debugging switch the SW3 SW4 SW5 and SW6 on the development board to the ARM Download side 3 2 4 Pinout Table 3 1 FPGA Download and Pinout Signal Name Pin No BANK Description I O TMS 4 3 JTAG Signal 3 3V ADC LVDS 1 8V MIPI PSRAM TCK 5 3 JTAG Signal 3 3V ADC LVDS TDI 6 3 JTAG Signal 1 8V MIPI PSRAM TDO 7 3 JTAG Signal 3 3V ADC LVDS MO...

Page 19: ... 3 2 Power System Distribution USB Interface DC5V Input TPS7A7001 LDO 1 2V TPS7A7001 LDO 3 3V TPS7A7001 LDO 2 5V USB JTAG FT2232 FPGA VCCO0 VCCO3 ADC LVDS MIPI FPGA VCCX UX FPGA Key LED Reset FPGA VCCO2 LVDS FPGA VCCO1 FPGA VCC FPGA VCCO2 MIPI TPS7A7001 LDO 1 8V FPGA VCCO0 VCCO3 PSRAM FPGA VCCX LX FPGA ...

Page 20: ...set 3 4 1 Overview A 50MHz crystal oscillator is provided in the development board that connects to the PLL input pin This can be employed as the input clock for the PLL in FPGA and the output clock as needed via multiplication and division of the PLL frequency 3 4 2 Clock Reset Figure 3 3 Clock Reset 35 14 KEY3 50MHz ADM811 3 3V FPGA_RST_N FPGA_CLK U1 U2 X2 GW1NSR LX2CQN48PC5I4_V2 1 3 4 3 Pinout ...

Page 21: ... in the following ways If the output signal of related pins is logic low LED is on If the logic is high LED is off 3 5 2 LED Circuit Figure 3 4 LED Circuit LED1 3 LED2 11 VCC3P3 F_KEY1 F_KEY2 U1 GW1NSR LX2CQN48PC5I4_V2 1 3 5 3 Pinout Table 3 4 LED Pinout Signal Name Pin No BANK Description I O F_LED1 17 2 LED1 1 2V 2 5V F_LED2 18 2 LED2 1 2V 2 5V 3 6 Key 3 6 1 Overview One key switch is embedded i...

Page 22: ... 3 Pinout Table 3 5 Key Pinout Signal Name Pin No BANK Description I O F_KEY1 14 2 KEY1 1 2V 2 5V 3 7 GPIO 3 7 1 Overview One 2 54mm DC3 10P sockets are reserved on the development board for user function extension and testing purposes 3 7 2 GPIO Circuit Figure 3 6 GPIO Circuit 1 3 5 7 9 2 4 6 8 10 H_A_IO1 H_A_IO3 H_A_IO5 H_A_IO7 H_A_IO2 H_A_IO4 H_A_IO6 H_A_IO8 J14 H_A_IO9 ...

Page 23: ... GND 8 GND GND 9 GND GND 10 GND 3 8 MIPI LVDS 3 8 1 Overview Two 2 mm DC3 20P sockets are reserved on the development board for MIPI LVDS input output testing and data communication 3 8 2 MIPI LVDS Circuit Figure 3 7 LVDS Circuit 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_A1_P F_LVDS_A2_P F_LVDS_A3_P F_LVDS_A4_P F_LVDS_A5_P F_LVDS_A1_N F_LVDS_A2_N F_LVDS_A3_N F_LVDS_A4_N F_LVDS_A5_N...

Page 24: ...2 Differential output channel 2 2 5V LVDS 1 2V MIPI GND 7 GND 8 F_LVDS_A3_P 21 9 2 Differential output channel 3 2 5V LVDS 1 2V MIPI F_LVDS_A3_N 22 10 2 Differential output channel 3 2 5V LVDS 1 2V MIPI GND 11 GND 12 F_LVDS_A4_P 23 13 2 Differential output channel 4 2 5V LVDS 1 2V MIPI F_LVDS_A4_N 24 14 2 Differential output channel 4 2 5V LVDS 1 2V MIPI GND 15 GND 16 GND 15 GND GND 16 GND GND 19 ...

Page 25: ...MIPI F_LVDS_B3_N 42 10 0 Differential input channel 3 3 3V LVDS 1 8V MIPI GND 11 GND 12 F_LVDS_B4_P 41 13 0 Differential input channel 4 3 3V LVDS 1 8V MIPI F_LVDS_B4_N 40 14 0 Differential input channel 4 3 3V LVDS 1 8V MIPI GND 15 GND 16 F_LVDS_B5_P 39 17 0 Differential input channel 5 3 3V LVDS 1 8V MIPI F_LVDS_B5_N 38 18 0 Differential input channel 5 3 3V LVDS 1 8V MIPI GND 19 GND 20 3 9 ADC ...

Page 26: ...1 13 15 17 19 12 14 16 18 20 F_LVDS_B1_P F_LVDS_B2_P F_LVDS_B3_P F_LVDS_B4_P F_LVDS_B5_P F_LVDS_B1_N F_LVDS_B2_N F_LVDS_B3_N F_LVDS_B4_N F_LVDS_B5_N J16 3 9 3 Pinout Table 3 9 J15 ADC Pinout Signal Name Pin No Socket Pin No BANK Description I O ADC_CH0 47 1 0 ADC_CH0 3 3V ADC ADC_CH1 46 2 0 ADC_CH1 3 3V ADC GND 3 0 GND ...

Page 27: ... to be set as 3 3V If the development board adopts the LX device VCCX needs to be set as 1 8V VCCO2 Bank voltage needs to be set as 2 5V when the Bank2 output differential pairs serve as LVDS output VCCO2 Bank voltage needs to be set as 1 2V when the Bank2 output differential pairs serve as MIPI output VCCO0 VCCO3 Bank voltage needs to be set as 1 8V when the internal PSRAM is employed VCCO0 VCCO3...

Page 28: ...5 Gowin Software DBUG401 1 0E 21 22 5 Gowin Software Please refer to SUG100 Gowin Software User Guide for details ...

Page 29: ...6 Quick Start DBUG401 1 0E 22 22 6 Quick Start See TN432 DK START GW1NSR2_V2 1 Development Board Quick Start User Guide for details ...

Page 30: ......

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