GOWIN DK_GoAI_GW1NSR-LV4CQN48PC7I6 User Manual Download Page 22

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3 Development Board Circuit

3.6 Switches

DBUG391-1.0E

15(20)

3.6

Switches

3.6.1

Overview

There is a dip switch SW3 on the development board, which can be

used to select JTAG interface or USB interface for FPGA download and
debugging.

3.7

HDMI TX

3.7.1

Overview

HDMI3 interface is connected to the FPGA pin directly. The HDMI

signal is received via FPGA IP.

3.7.2

HDMI TX Circuit

Figure 3-5 HDMI TX Interface Connection Circuit

GW1NSR4

HDMI_TXA2P

HDMI_TXA2N

HDMI_TXA1P

HDMI_TXA1N

HDMI_TXA0P

HDMI_TXA0N

HDMI_TXACP

HDMI_TXACN

HDMI_TXA2P

HDMI_TXA2N

HDMI_TXA1P

HDMI_TXA1N

HDMI_TXA0P

HDMI_TXA0N

HDMI_TXACP

HDMI_TXACN

HDMI_VCC3P3

HDMI

3.7.3

Pinout

Table 3-5 HDMI TX Pinout

Name

Pin No.

BANK

I/O Level

Description

HDMI_TXA2P

2.5V

HDMI differential data

HDMI_TXA2N

2.5V

HDMI differential data

Summary of Contents for DK_GoAI_GW1NSR-LV4CQN48PC7I6

Page 1: ...DK_GoAI_GW1NSR LV4CQN48PC7I6_V2 2 User Guide DBUG391 1 0E 03 03 2021 ...

Page 2: ... identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms...

Page 3: ...Revision History Date Version Description 03 03 2021 1 0E Initial version published ...

Page 4: ... 2 2 Introduction 3 2 1 Overview 3 2 2 System Block Diagram 4 2 3 Development Kit 5 2 4 PCB Components 6 2 5 Features 6 2 6 Development Board Description 8 3 Development Board Circuit 10 3 1 FPGA Module 10 3 2 Download Debug 10 3 2 1 Overview 10 3 2 2 USB 11 3 2 3 JTAG 11 3 2 4 Flow 11 3 2 5 Pinout 12 3 3 Power Supply 12 3 3 1 Overview 12 3 3 2 Power System Distribution 13 3 3 3 Pins Distribution ...

Page 5: ...inout 14 3 5 LED 14 3 6 Switches 15 3 6 1 Overview 15 3 7 HDMI TX 15 3 7 1 Overview 15 3 7 2 HDMI TX Circuit 15 3 7 3 Pinout 15 3 8 Camera 16 3 8 1 Overview 16 3 8 2 FPC Interface 16 3 8 3 Pinout 17 3 9 SPI FLASH 17 3 10 Mic 18 3 11 Accelerometer 18 4 Notes 19 5 Gowin Software 20 ...

Page 6: ...em Block Diagram 4 Figure 2 3 PCB Components 6 Figure 3 1 Connection Diagram of USB 11 Figure 3 2 J LINK Connection Diagram 11 Figure 3 3 Power System Distribution 13 Figure 3 4 Clock 14 Figure 3 5 HDMI TX Interface Connection Circuit 15 Figure 3 6 FPC Interface Connection Circuit 16 Figure 3 7 Accelerometer Connection Circuit 18 ...

Page 7: ...pment Board Description 8 Table 3 1 FPGA Download Pinout 12 Table 3 2 FPGA Power Pins Distribution 13 Table 3 3 FPGA Clock and Reset Pinout 14 Table 3 4 LED Pinout 14 Table 3 5 HDMI TX Pinout 15 Table 3 6 FPC Pinout 17 Table 3 7 SPI FLASH Pinout 17 Table 3 8 Mic Pinout 18 Table 3 9 Accelerometer Pinout 18 ...

Page 8: ...ftware 1 2 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS861 GW1NSR series FPGA Products Data Sheet 2 UG864 GW1NSR 4 Pinout 3 UG290 Gowin FPGA Products Programming and Configuration Guide 4 SUG100 Gowin Software User Guide 1 3 Terminology and Abbreviations The terminology and abbreviations used in this ma...

Page 9: ...ndom Access Memory RS232 Recommend Standard 232 ARM Advanced RISC Machine BSRAM Block Static Random Access Memory SPI Serial Peripheral Interface PLL Phase locked Loop QN48 QFN48 Package 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly by the following ways ...

Page 10: ...he core the needs of the min memory can be met FPGA logic resources and other embedded resources can flexibly perform the peripheral control functions which provide excellent calculation and exceptional system response interrupts They also offer high performance low power consumption flexibility instant on low cost non volatile high security and abundant package types etc The development board off...

Page 11: ... System Block Diagram Figure 2 2 System Block Diagram 4 LED OSC 50MHz 2 Mic 1 Camera FPC connector 1 LED OSC 27MHZ 1 HDMI TX JTAG Power 1 2V 1 8V 2 5V 2 8V 3 3V GW1NSR LV4QN48P MINI USB 1 64Mbit SPI Flash FT232HL DC POWER JACK SWITCH 5V 5V SWITCH 1 Accelerometer ...

Page 12: ...2 3 Development Kit The development board kit includes the following items DK_GoAI_GW1NSR LV4CQN48PC7I6_V2 2 Development Board USB Data Line Quick Start Guide 3 1 2 Gowin DK_GoAI_GW1NSR LV4CQN48PC7I6_V2 2 Development Board USB Data Line Quick Start Guide ...

Page 13: ... 5 Features The features of the development board are as follows 1 FPGA EQFP144 package Up to 38 user I O Embedded flash data not easily lost if power down Abundant LUT4 resources Multiple modes and capacities of B SRAM 2 FPGA Configuration Modes JTAG AUTO BOOT 3 Power External USB 5V 4 Clock resource 27MHz Clock Crystal Oscillator 5 LED One power indicator green 1 LEDs green ...

Page 14: ...ed Flash 64Mbits external SPI FLASH 7 HDMI TX Interface 4 pairs of HDMI output one pair of clock and three pairs of data 8 Camera 24pin FPC connector with 0 5mm pitch is used 9 Mic 2 Mic 10 2 Accelerometer 1 Accelerometer 11 DC DC Power 3 3 V 2 8V 2 5V 1 8V 1 2V supported ...

Page 15: ...tor via 5V to 2 5V circuit Provide power for FPGA via 5V to 1 8V circuit Provide power for FPGA and FPC connector via 5 V to 1 2 V circuit 4 Dip switch Select JTAG or USB interface 1 5 6 LED Test indicator Power indicator Two test indicators green One power indicator green 7 Crystal Oscillator Provide 27MHz clock for FPGA Package2520 8 Memory FLASH 256K embedded Flash 64Mbit external SPI FLASH 9 H...

Page 16: ...n Technical Condition Power interface Inverse current and over current protection Schottky diode is connected between positive and negative anodes of power interface 2A self recovery fuses are connected at power input 14 Voltage Input Voltage 5V 15 Humidity 95 16 Temperature Operating range 20 70 ...

Page 17: ...n see UG864 GW1NSR Series of FPGA Products Package and Pinout User Guide for more details 3 2 Download Debug 3 2 1 Overview The development board provides JTAG interface and USB interface The fs file can be downloaded to the internal SRAM or external FLASH as needed Note When downloaded to SRAM the bitstream file will be lost if the device is powered down and it will need to be downloaded again af...

Page 18: ...DO 7 6 3 4 U1 J3 GW1NSR4 3 2 4 Flow 1 Enable USB interface FPGA and MCU download When downloading plug the USB cable to USB interface J2 of the development board and switch SW3 to ON 2 Enable JTAG interface FPGA and MCU Download When downloading plug the USB cable to JTAG interface J3 of the development board and switch SW1 to OFF MCU Debugging When debugging connect J Link emulator to JTAG interf...

Page 19: ... 3 V TDI 3 0 JTAG Signal 3 3 V TDO 4 0 JTAG Signal 3 3 V MODE0 10 0 Mode Selection Pin 3 3 V JTAGSEL_N 8 0 JTAGSEL_N 3 3 V DONE 9 0 One DONE Indicator 3 3 V 3 3 Power Supply 3 3 1 Overview The power supply is input from DC5V or USB interface The DC DC power supply chip is used to step down voltage from 5V to 3 3V 2 8V 2 5V 1 8V and 1 2V which can meet the power demands of the development board ...

Page 20: ...CO0 VCCO1 27Mhz Clock FPGA Reset FPGA VCCO3 PSRAM FPGA VCCX HDMI FPGA VCCO2 PAM2306AYPA DC DC 2 8V FPC PAM2306AYPA DC DC 1 2V FPGA VCC 3 3 3 Pins Distribution Table 3 2 FPGA Power Pins Distribution Name Pin No BANK Description I O Level VCCO0 5 0 I O Bank Voltage 3 3V VCCO1 38 1 I O Bank Voltage 3 3V VCCO2 36 2 I O Bank Voltage 2 5V VCCO3 12 24 3 I O Bank Voltage 1 8V VCCX 25 Auxiliary voltage 2 5...

Page 21: ...Table 3 3 FPGA Clock and Reset Pinout Name Pin No BANK Description I O Level F_CLK 45 1 27MHz crystal oscillator input 3 3V 3 5 LED There is one green LED in the development board and users can display the required status through the LED At the same time in order to facilitate the observation of the power supply situation a power indicator LED is left You can test the LEDs in the following ways Wh...

Page 22: ...ectly The HDMI signal is received via FPGA IP 3 7 2 HDMI TX Circuit Figure 3 5 HDMI TX Interface Connection Circuit U1 GW1NSR4 HDMI_TXA2P HDMI_TXA2N HDMI_TXA1P HDMI_TXA1N HDMI_TXA0P HDMI_TXA0N HDMI_TXACP HDMI_TXACN HDMI_TXA2P HDMI_TXA2N HDMI_TXA1P HDMI_TXA1N HDMI_TXA0P HDMI_TXA0N HDMI_TXACP HDMI_TXACN HDMI_VCC3P3 HDMI 35 34 32 31 30 29 28 27 3 7 3 Pinout Table 3 5 HDMI TX Pinout Name Pin No BANK I...

Page 23: ...k HDMI_TXACN 27 2 2 5V HDMI differential clock 3 8 Camera 3 8 1 Overview The camera interface is connected directly to the 24pin FPGA pin FPC connector with 0 5mm pitch and the signal is received transmitted through the internal IP of FPGA 3 8 2 FPC Interface Figure 3 6 FPC Interface Connection Circuit FH12_24S_0 5SH U1 J5 GW2AR LV18QN88P PIXDATA3 PIXDATA4 PIXDATA5 PIXDATA6 PIXDATA7 PIXDATA8 PIXDA...

Page 24: ...nel 2 1 8V PIXDATA1 21 3 Video output channel 1 1 8V PIXDATA0 22 2 Video output channel 0 1 8V XCLK 33 2 System clock input 2 5V HREF 42 1 Horizontal reference output 3 3V VSYNC 43 1 Vertical Sync output 3 3V SDA 46 1 I2C serial interface data 3 3V SCL 44 1 I2C serial interface clock 3 3V 3 9 SPI FLASH There is a 64Mbit FLASH on the board If downloaded to flash the bitstream file will not be lost ...

Page 25: ...SD 13 3 Write protection input 1 8V MIC_SCK 14 3 Data output 1 8V MIC_WS 15 3 Chip select signal 1 8V 3 11 Accelerometer There is one Accelerometer left on the development board for acceleration data acquisition Figure 3 7 Accelerometer Connection Circuit Table 3 9 Accelerometer Pinout Name Pin No BANK Description I O Level SDA 46 1 I2C serial interface data 3 3V SCL 44 1 I2C serial interface cloc...

Page 26: ...4 Notes DBUG391 1 0E 19 20 4 Notes Notes for the Use of the Development Board Handle with care and pay attention to electrostatic protection ...

Page 27: ...5 Gowin Software DBUG391 1 0E 20 20 5 Gowin Software See SUG100 Gowin Software User Guide for details ...

Page 28: ......

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