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3Development Board Circuit

3.7LVDS interfaces

DBUG354-1.0E

20

(

30

)

Signal Name

FPGA Pin No.

BANK

I/O

Description

PHY1_TXD2

P13

2

3.3V

PHY1 sending data channel 2

PHY1_TXD3

T11

2

3.3V

PHY1 sending data channel 3

PHY1_TX_EN

R11

2

3.3V

PHY1 sending data enable

PHY1_RXC

T12

2

3.3V

PHY1 Clock receive

PHY1_RXD0

R12

2

3.3V

PHY1 receive data channel 0

PHY1_RXD1

T13

2

3.3V

PHY1 receive data channel 1

PHY1_RXD2

R13

2

3.3V

PHY1 receive data channel 2

PHY1_RXD3

T14

2

3.3V

PHY1 receive data channel 3

PHY1_RX_DV

R14

2

3.3V

PHY1 receive data enable

PHY2_GTCLK

T7

3

3.3V

PHY2 Transmitter Clock

PHY2_TXD0

M6

3

3.3V

PHY2 sending data channel 0

PHY2_TXD1

N6

3

3.3V

PHY2 sending data channel 1

PHY2_TXD2

P6

3

3.3V

PHY2 sending data channel

2

PHY2_TXD3

M7

3

3.3V

PHY2 sending data channel 3

PHY2_TX_EN

P8

3

3.3V

PHY2 sending data enable

PHY2_RXC

N7

3

3.3V

PHY2 Clock receive

PHY2_RXD0

P7

3

3.3V

PHY2 receive data channel 0

PHY2_RXD1

R7

3

3.3V

PHY2 receive data channel 1

PHY2_RXD2

R8

3

3.3V

PHY2 receive data channel 2

PHY2_RXD3

T8

3

3.3V

PHY2 receive data channel 3

PHY2_RX_DV

T9

3

3.3V

PHY2 receive data enable

3.7

LVDS interfaces

3.7.1

Introduction

The LVDS interfaces are the two 20 contact pins with the pitch of

2.00mm. One defaults to the transmitting interface. The other one defaults
to the receiving interface. Each interface includes five pairs of differential
signals. The terminating resistor can be changed to modify the transmitting
and receiving attributes, as shown in the figure below.

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Summary of Contents for DK-START-GW2A18

Page 1: ...DK START GW2A18 User Guide DBUG354 1 0E 08 28 2018 ...

Page 2: ... identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms...

Page 3: ...Revision History Date Version Description 08 28 2018 1 0E Initial version published ...

Page 4: ...rd Description 3 2 1 Overview 3 2 2 A Development Board Suite 4 2 3 PCB Components 5 2 4 System Architecture 6 2 5 Features 6 3 Development Board Circuit 9 3 1 FPGA Module 9 3 1 1 Introduction 9 3 1 2 I O Distribution 10 3 2 Download Module 12 3 2 1 Introduction 12 3 2 2 Pins Distribution 13 3 3 Power Supply 13 3 3 1 Introduction 13 3 3 2 Power System Distribution 15 3 4 Clock Reset 16 3 4 1 Intro...

Page 5: ...rfaces 20 3 7 1 Introduction 20 3 7 2 Pins Distribution 22 3 8 SD Card 22 3 8 1 Introduction 22 3 8 2 Pins Distribution 24 3 9 GPIO 24 3 9 1 Introduction 24 3 9 2 Pins Distribution 25 3 10 LED 26 3 10 1 Introduction 27 3 10 2 Pins Distribution 27 3 11 Key 27 3 11 1 Introduction 27 3 11 2 Pins Distribution 28 3 12 Switch 28 3 12 1 Introduction 28 3 12 2 Pins Distribution 29 4 Gowin YunYuan Software...

Page 6: ...iguration 13 Figure 3 4 Power System Distribution 15 Figure 3 5 Connection Diagram for Clock and Reset 16 Figure 3 6 Connection Diagram of FPGA and DDR3 17 Figure 3 7 Connection Diagram of FPGA and Ethernet 19 Figure 3 8 LVDS TX Interface 21 Figure 3 9 LVDS RX Interface 21 Figure 3 10 Connection Diagram of SD Card 23 Figure 3 11 20pin Interface 24 Figure 3 12 30pin Interface 25 Figure 3 13 LED Con...

Page 7: ...le 3 4 Clock and Reset Pins Distribution 16 Table 3 5 DDR3 Pins Distribution 17 Table 3 6 Ethernet Pins Distribution 19 Table 3 7 LVDS TX Interface Pins Distribution 22 Table 3 8 LVDS RX Interface Pins Distribution 22 Table 3 9 20pin Interface Pins Distribution 25 Table 3 10 30pin Interface Pins Distribution 26 Table 3 11 LED Pins Distribution 27 Table 3 12 Key Pins Distribution 28 Table 3 13 Pins...

Page 8: ...dware circuit functions circuits and pins distribution 4 An introduction to the use of the Gowin YunYuan software 1 2 Supported Products The information presented in this guide applies to the following Gowin FPGA products GW2A LV18PG256 1 3 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 GW2A series of FPGA P...

Page 9: ...eld Programmable Gate Array GPIO General Purpose Input Output LDO Low Dropout Regulator LUT4 4 input Look up Tables LVDS Low Voltage Differential Signaling S SRAM Shadow SRAM 1 5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly using the information provided bel...

Page 10: ...ed communication test FPGA functions evaluation the verification of hardware reliability software learning and debugging etc The development board uses the GW2A LV18PG256 FPGA device which is the first generation products of Gowin Arora family The GW2A series of FPGA products offer a range of comprehensive features and rich internal resources like high performance DSP resources a high speed ...

Page 11: ...nd the highest data speed of 1600MT s Its two Gigabit Ethernet interfaces support 10M 100M 1000M Ethernet communication It has abundant peripheral interfaces including LVDS interfaces a SD card slot and GPIO interfaces Besides that it also offers an external Flash slide switches key switches external clocks etc 2 2 A Development Board Suite A development board suite includes the following items 1 ...

Page 12: ...1 0E 5 30 2 3 PCB Components Figure 2 1 PCB Components 1 2V电源 2 5V电源以太网接口芯片 2 1 0V电源 DDR3 1 5V电源 3 3V电源备用电源电源插座电源开关 20PIN GPIO 插针 30PIN GPIO 插针 MODE BANK7 电压选择 LED 4 USB MINI B 开关 4 USB转 JTAG芯片 LVDS RX LVDS TX FPGA 按键 4 外部时钟复位按键配置 FLASH 以太网接口 2 SD卡座 ...

Page 13: ...PIO Header 配置 FLASH X16 X24 SD卡 X31 X4 X10 X10 X29 X7 X1 X4 X4 X4 X4 按键 LVDS TX LVDS RX 2 5 Features The key features of DK START GW2A is as follows 1 The FPGA device GW2A LV18PG256C8 I7 Max user I O 207 2 Download and Boot Integrates the download module can be downloaded with the USB Mini B cable External Flash boot The blue DONE light is on after loading 3 Power External 5V 2A Power supply ...

Page 14: ...erface for sending including five pairs of differential signals The receiving sending functions can be modified by changing the resistance Note For the V2 0 development board J13 needs to be set as 2 5V when LVDS is used 8 SD card slot Eight contacts push push type Card detection 9 Extension interface 20PIN double row pins including 16 GPIO one I O Bank voltage can be adjusted as 3 3V 2 5V 1 2V on...

Page 15: ...2Development Board Description 2 5Features DBUG354 1 0E 8 30 Four blue LEDs ...

Page 16: ... out in Table 3 1 Table 3 1GW2A LV18PG256 FPGA Resources List Device GW2A LV18PG256 LUT4 20 736 Flip Flop FF 15 552 Shadow SRAM S SRAM bits 41 472 Block SRAM B SRAM bits 828K B SRAM quantity B SRAM 46 18 x 18 Multiplier 48 PLLs DLLs 4 4 Total number of I O banks 8 Max User I O 207 Core voltage 1 0V Note See GW2A series of FPGA Products Data Sheet for further details ...

Page 17: ... series FPGA products includes eight I O Bank The I O Bank Distribution is as shown in Figure 3 1 Figure 3 1 GW2A I O Bank Distribution IO Bank 6 GW2A IO Bank 7 IO Bank 3 IO Bank 2 IO Bank 0 IO Bank 1 IO Bank 4 IO Bank 5 The view of GW2A 18 PG256 pins distribution is as shown in Figure 3 2 ...

Page 18: ...able 3 2 FPGA I O Bank Voltage and Functions I O BANK No Supply voltage Functions BANK0 2 5V LVDS_RX Interface 30PIN GPIO Interface 50MHz crystal oscillator Input LED BANK1 2 5V LVDS_TX Interface 30PIN GPIO Interface BANK2 3 3V Ethernet interface1 Ethernet interface2 JTAG Download SD card slot External Clock BANK3 3 3V Ethernet interface2 FLASH Configuration SD card slot Reset MODE ...

Page 19: ...USB download interface You can set the MODE value to download the programs to the on chip SRAM or external Flash When downloaded to SRAM the data stream file will be lost if the device is power down When downloaded to Flash the data stream file will not be lost The MODE value configuration 1 In any modes you can download the data stream file to the on chip SRAM and run it immediately 2 Set MODE as...

Page 20: ...AG Signal JTAG_TDO C6 2 3 3V JTAG Signal JTAG_TDI A6 2 3 3V JTAG Signal JTAG_TMS B8 2 3 3V JTAG Signal FLASH_SPI_MISO P10 3 3 3V FLASH signals configuration FLASH_SPI_MOSI R10 3 3 3V FLASH signals configuration FLASH_SPI_CS_N M9 3 3 3V FLASH signals configuration FLASH_SPI_CLK L10 3 3 3V FLASH signals configuration 3 3 Power Supply 3 3 1 Introduction 5V power Input 100 240V 50 60MHz 0 5A output DC...

Page 21: ...velopment Board Circuit 3 3Power Supply DBUG354 1 0E 14 30 is 2A When the redundant power is used to replace the main power you need to take off the main power s magnetic beads to avoid the power conflicts ...

Page 22: ...3170 开关电源 1 5V 3A TPS7A7001 LDO 2 5V 2A TPS7A7001 LDO 1 2V 2A TPS7A7001 备用LDO 3 3V 1 5V 1 0V 2A TPS51200 DDR终端调节器 0 75V VDDQ VDD DDR3 VREFDQ VREFCA DDR3 信号线上拉电源 DDR3 VCC VCCPLLL VCCPLLR FPGA VCCO0 VCCO1 VCCO7 FPGA VCCO2 VCCO3 VCCO7 VCCX FPGA VCCO4 VCCO5 VCCO6 FPGA VCCO7 FPGA 30PIN GPIO 插针 20PIN GPIO 插针以太网接口芯片1 B50610KML 以太网接口芯片2 B50610KML USB转JTAG FT2232 配置FLASH W25Q64 SD卡座按键开关 LED 4 ...

Page 23: ...r powered on the device the reset chip automatically generates a reset signal to reset the FPGA and Ethernet PHY chip The 3 3V voltage is monitored in real time The reset signal will be generated once an exception occurs The reset signal can also be generated via the reset key Figure 3 5 Connection Diagram for Clock and Reset H11 T15 T10 KEY1 50MHz ADM811 EXT CLK 3 3V RST_N CLK_SMA CLK_G 3 4 2 Pin...

Page 24: ...p DDR3_UDM DDR3_LDM DDR3_CASn DDR3_RASn DDR3_WEn DDR3_ODT DDR3_CK_EN DDR3_CSn DDR3_RSTn DDR3_CKn DDR3_CKp 3 5 2 Pins Distribution Table 3 5 DDR3 Pins Distribution Signal Name FPGA Pin No BANK I O Description DDR3_A0 F7 6 1 5V Address DDR3_A1 A4 5 1 5V Address DDR3_A2 D6 5 1 5V Address DDR3_A3 F8 6 1 5V Address DDR3_A4 C4 6 1 5V Address DDR3_A5 E6 6 1 5V Address DDR3_A6 B1 5 1 5V Address DDR3_A7 D8...

Page 25: ...1 5V Data DDR3_DQ1 F5 5 1 5V Data DDR3_DQ2 F4 5 1 5V Data DDR3_DQ3 F3 5 1 5V Data DDR3_DQ4 E2 5 1 5V Data DDR3_DQ5 C1 5 1 5V Data DDR3_DQ6 E1 5 1 5V Data DDR3_DQ7 B3 5 1 5V Data DDR3_DQ8 M3 4 1 5V Data DDR3_DQ9 K4 4 1 5V Data DDR3_DQ10 N2 4 1 5V Data DDR3_DQ11 L1 4 1 5V Data DDR3_DQ12 P4 4 1 5V Data DDR3_DQ13 H3 4 1 5V Data DDR3_DQ14 R1 4 1 5V Data DDR3_DQ15 M2 4 1 5V Data DDR3_LDM G1 5 1 5V Data ...

Page 26: ...o other devices is RJ45 with the built in transformer The connection diagram is as follows Figure 3 7 Connection Diagram of FPGA and Ethernet PHY1 PHY1_GTXCLK PHY1_RXC PHY1_TX_EN PHY1_RX_DV PHY1_TDX 3 0 PHY1_RDX 3 0 CLK_PHY1 PHY2 RST_N PHY_MDC PHY_MDIO PHY2_GTXCLK PHY2_RXC PHY2_TX_EN PHY2_RX_DV PHY2_TDX 3 0 PHY2_RDX 3 0 CLK_PHY2 3 6 2 Pins Distribution Table 3 6 Ethernet Pins Distribution Signal N...

Page 27: ...N6 3 3 3V PHY2 sending data channel 1 PHY2_TXD2 P6 3 3 3V PHY2 sending data channel 2 PHY2_TXD3 M7 3 3 3V PHY2 sending data channel 3 PHY2_TX_EN P8 3 3 3V PHY2 sending data enable PHY2_RXC N7 3 3 3V PHY2 Clock receive PHY2_RXD0 P7 3 3 3V PHY2 receive data channel 0 PHY2_RXD1 R7 3 3 3V PHY2 receive data channel 1 PHY2_RXD2 R8 3 3 3V PHY2 receive data channel 2 PHY2_RXD3 T8 3 3 3V PHY2 receive data ...

Page 28: ...LVDS_B3_P LVDS_B4_P LVDS_B5_P LVDS_B1_N LVDS_B2_N LVDS_B3_N LVDS_B4_N LVDS_B5_N J10 Figure 3 9 LVDS RX Interface 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 LVDS_A1_P LVDS_A2_P LVDS_A3_P LVDS_A4_P LVDS_A5_P LVDS_A1_N LVDS_A2_N LVDS_A3_N LVDS_A4_N LVDS_A5_N J11 LVDS_A1_P LVDS_A2_P LVDS_A3_P LVDS_A4_P LVDS_A5_P LVDS_A1_N LVDS_A2_N LVDS_A3_N LVDS_A4_N LVDS_A5_N ...

Page 29: ...rential Channel 5 For the V2 0 development board J13 needs to be set as 2 5V when LVDS is used Table 3 8 LVDS RX Interface Pins Distribution Pins Number Signal Name FPGA Pin No BANK I O Description 1 LVDS_A1_P D16 0 2 5V Differential Channel 1 2 LVDS_A1_N E14 0 2 5V Differential Channel 1 5 LVDS_A2_P E16 0 2 5V Differential Channel 2 6 LVDS_A2_N F15 0 2 5V Differential Channel 2 9 LVDS_A3_P G16 0 ...

Page 30: ...t 3 8SD Card DBUG354 1 0E 23 30 contacts It offers the detection of the card insertion The connection diagram is shown as follows Figure 3 10 Connection Diagram of SD Card SD卡座 SD_D0 SD_CD D3 SD_D1 SD_CMD SD_D2 SD_CLK SD_SWITCH ...

Page 31: ..._SWITCH M11 2 3 3V Insertion Detection 3 9 GPIO 3 9 1 Introduction Two double row pins with the pitch of 2 54mm are reserved on the development board The 20 pin interface connects to Bank7 and the I O voltage can be adjusted as 3 3V 2 5V and 1 2V The I O voltage of the 30 pin can be set as 2 5V as shown in the figure below Figure 3 11 20pin Interface 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18...

Page 32: ... Distribution Table 3 9 20pin Interface Pins Distribution Pins Number Signal Name FPGA Pin No BANK I O Description 3 H_A_IO1 A15 7 3 3V 2 5V 1 2V General I O 4 H_A_IO2 A14 7 3 3V 2 5V 1 2V General I O 5 H_A_IO3 B14 7 3 3V 2 5V 1 2V General I O 6 H_A_IO4 B13 7 3 3V 2 5V 1 2V General I O 7 H_A_IO5 C12 7 3 3V 2 5V 1 2V General I O 8 H_A_IO6 D11 7 3 3V 2 5V 1 2V General I O 9 H_A_IO7 A12 7 3 3V 2 5V 1...

Page 33: ...1 2 5V General I O 11 H_GPIO_07 L15 0 2 5V General I O 12 H_GPIO_08 M15 1 2 5V General I O 13 H_GPIO_09 J16 0 2 5V General I O 14 H_GPIO_10 L12 1 2 5V General I O 15 H_GPIO_11 K13 1 2 5V General I O 16 H_GPIO_12 K11 1 2 5V General I O 17 H_GPIO_13 J11 1 2 5V General I O 18 H_GPIO_14 J14 0 2 5V General I O 19 H_GPIO_15 J12 0 2 5V General I O 20 H_GPIO_16 G15 0 2 5V General I O 21 H_GPIO_17 E15 1 2 ...

Page 34: ...nection Diagram LED1 F16 LED2 G12 LED3 F13 LED4 F14 2 5V 3 10 2 Pins Distribution Table 3 11 LED Pins Distribution Signal Name FPGA Pin No BANK I O Description LED1 F16 0 2 5V LED1 LED2 G12 0 2 5V LED2 LED3 F13 0 2 5V LED3 LED4 F14 0 2 5V LED4 Note For the V2 0 development board the BANK0 voltage and BANK1 voltage can be set as 3 3V or 2 5V using J13 3 11 Key 3 11 1 Introduction Four key switches ...

Page 35: ...n Table 3 12 Key Pins Distribution Signal Name FPGA Pin No BANK I O Description KEY1 T2 4 1 5V KEY1 KEY2 T3 4 1 5V KEY2 KEY3 T4 4 1 5V KEY3 KEY4 T5 4 1 5V KEY4 3 12 Switch 3 12 1 Introduction Four slide switches are incorporated into the development board These are used to control input during testing The connection diagram is as follows ...

Page 36: ...O Circuit SW1 E9 SW2 E8 SW3 C7 SW4 D7 1 5V 3 12 2 Pins Distribution Table 3 13 Pins Distribution of the Switch Module Signal Name FPGA Pin No BANK I O Description SW1 E9 6 1 5V Slide Switch1 SW2 E8 6 1 5V Slide Switch2 SW3 C7 6 1 5V Slide Switch3 SW4 D7 6 1 5V Slide Switch4 ...

Page 37: ...4Gowin YunYuan Software DBUG354 1 0E 30 30 4Gowin YunYuan Software Please refer to Gowin Software User Guide for details ...

Page 38: ......

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