3 Development Board Circuit
3.4 Clock
DBUG392-1.0E
12(23)
3.4
Clock
3.4.1
Overview
The development board provides a 50MHz crystal oscillator connected
to the PLL input pin. This can be employed as the input clock for the PLL in
FPGA. Frequency division and multiplication of PLL can provide clocks
required by users.
3.4.2
Clock
Figure 3-3 Clock Circuit
106
FPGA_CLK
U1
X2
GW1N-
LV9EQ144C6I5
3.4.3
Pinout
Table 3-3 FPGA Clock Pinout
Name
Pin No.
BANK
Description
I/O Level
FPGA_CLK
106
1
50MHz crystal oscillator input 2.5V/1.2V
3.5
LED
3.5.1
Overview
There are four green LEDs in the development board and users can
display the required status through the LED. In addition, two LEDs are
reserved to signify the power supply and FPGA loading status.
You can test the LEDs in the following ways:
When the FPGA corresponding pin output signal is logic low, the LED is
lit;
If the signal is high, LED is off.
