3 Development Board Circuit
3.4 Clock, Reset
DBUG378-1.0E
15(25)
3.3.3
FPGA Power Pinout
Table 3-2 FPGA Power Pinout
Name
Pin No.
BANK Description
I/O Level
VCCO0
F11, B5, B110
0
I/O Bank Voltage
3.3V
VCCO1
B19, F12
、
B14
1
I/O Bank Voltage
2.5V
VCCO2
K21, E21, L17
2
I/O Bank Voltage
3.3V
VCCO3
M17, W21, P21
3
I/O Bank Voltage
3.3V
VCCO4
AA18, AA13, U12
4
I/O Bank Voltage
2.5V
VCCO5
AA9, AA4, U11
5
I/O Bank Voltage
2.5V
VCCO6
V2, N2, M6
6
I/O Bank Voltage
1.8V
VCCO7
L6, D2, J2
7
I/O Bank Voltage
2.5V
VCCPLLL K7, N7
-
PLLL
1.0V
VCCPLLR K16, N16
-
PLLR
1.0V
VCCX
U14, U9, F14, J6, F9,
P17, P6, J17
-
Auxiliary voltage
3.3V
VCC
J7, M16, T7, L7, L16,
H7, G9, T13, T14, G10,
M7, G11, T16, G14, G13,
G15, G16, P16, P6, H16,
G7, G16, G8, R16, J16,
T12, T11, R7, T15, T9,
T8, T10, T16
-
Core voltage
1.0V
3.4
Clock, Reset
3.4.1
Overview
The development board provides a 27MHz crystal oscillator connected
to the PLL input pin. This can be employed as the input clock for the PLL in
FPGA. Frequency division and multiplication of PLL can provide clocks
required by users.
For easier debugging, one reset signal is added on the development
board. It's low active.
