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Page 2: ...Mounting the battery holder Replacing the battery I O port map PROGRAMMING CONSIDERATIONS FOR THE SYSTEM SUPPORT 1 Power up initialization Programming the serial channel UART initialization Sample UA...
Page 3: ...representations or warranties with respect to the contents hereof and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose Further Godbout Electronic...
Page 4: ...otherwise ON if you are not using extended addressing OFF otherwise ON OFF DIP SWITCH 2 is located between U32 and U33 and is used to set the extended address that the ROM RAM responds to If you are...
Page 5: ...the System Support I with our CPU 8085 88 board or any other 8085 8088 8086 type board then install the shorting plug at jumper J13 so that the pins labeled 8 and c are connected together shorting plu...
Page 6: ...been so packed with features at such a reasonable cost as the System Support 1 and that makes it proud to be another member of the CompuPro family Thank you for choosing a CompuPro product welcome to...
Page 7: ...ed arise Provision has been made for either math chip whichever you prefer The math chip can run in an interrupt driven mode which allows the math functions to occur in parallel with other processing...
Page 8: ...owing table shows all possible I O addresses that the System Support 1 can reside at and the associated switch settings SWITCH 3 I O Address 5 Switch Position 6 7 8 The standard port block that we hav...
Page 9: ...following table shows all possible 4K byte boundaries that the memory may start at and the associated switch settings SWITCH 3 Memory Address 1 Switch Position 2 3 4 NOTE U16 occupies the upper 2K of...
Page 10: ...Switch 1 ON If you don t want the on board memory space to be disabled if you re going to use some kind of memory turn position 5 of Switch 1 OFF GLOBAL EXTENDED ADDRESS SELECTION Position 6 of Switch...
Page 11: ...ing in the diode and use a temperature controlled soldering iron or be sure it s less than 40 watts If you ever decide to use an EPROM in that socket be sure to remove the diode otherwise the clock ba...
Page 12: ...option then you must cut the trace connecting the two pads in the B block of J5 This trace is located on the back solder side of the PC board Use an XACTO knife and be extremely careful not to damage...
Page 13: ...or example if an interrupt controller already exists in your system the on board interrupts may be jumpered to any of the S 100 vectored interrupt lines This means that the interrupting capability of...
Page 14: ...nnected directly to J7 and J8 as is shown above This is because the polarity of the END signal is different between the 9511 and the 9512 J6 is used to select the appro priate polarity for this signal...
Page 15: ...lines A standard 26 pin transition connector has been provided at J1 to facilitate easy connection of a ribbon cable that usually has a DB 25 style connector on the other end Such a cable is availabl...
Page 16: ...CPU board that does not generate pSTVAL then you will need to make a small modification to the System Support 1 Proceed as follows Locate Jll It is located near the edge connector in approximately the...
Page 17: ...e a good practice because any of the other interrupts could be masked at the time of power failure thus defeating the purpose of the PWRFAIL signal CONNECTING THE BATTERY The battery connector supplie...
Page 18: ...r usually irreparable Ni cads will not be recharged by the board s circuitry Also note that using any battery other than the ones specified will void your warranty I O PURr MAP The System Support 1 us...
Page 19: ...rameters must be set like the baud rate word length etc the interval timer modes must be set if they are used and so on How your board is to be set up on power up is dependent soley on your system req...
Page 20: ...the meaning of the status bits Bit 0 TxRDY When low indicates that the transmitter is currently busy and you should wait before sending another character When high indicates that the transmitter is n...
Page 21: ...gic one This sets up the UART for asynchronous operation with a 16X baud rate Bits 2 and 3 Character Length These two bits are used to determine the length of the characters that will be sent and rece...
Page 22: ...ill be generatedby the UART and thereforewhat baud rate the UART will run at accordingto the following table Bits 4 5 6 and 7 For proper UART operation in the System Support 1 these four bits shouldal...
Page 23: ...d to a high state Bit 2 Receive Control When bit 2 is high the receiver section of the UART is enabled When bit 2 is low the receiver is disabled Normally this bit should be high Bit 3 Force Break Whe...
Page 24: ...or you may patch it for any other monitor or software you are using TEST PROGRAMFOR THE 2651 DART SETS UP THE UART FOR 9600 BAUD INTERNALLY GEN 8 BIT CHARACTERS 2 STOP BITS NO PARITY RTS LOW DTR LOW...
Page 25: ...it 6 Hold When this bit is high the clock s counters will be inhibited This line must be high for all write operations and may be optionally high for read operations If this line is kept high for more...
Page 26: ...e two digits since two bits can representthe numbers 0 through 3 The hours 10 digit will never go beyond 2 in the 24 hour mode and the days 10 digit will never go beyond 3 The upper two bits of the lo...
Page 27: ...he read and write bits low 3 Write the data to be written to the data register 4 Write the digit address in the lower four bits of the command registerwith the hold and write bits set high and the rea...
Page 28: ...LOCK this program assumes that the System Support 1 is addressed to the block of ports at 50H to change to a different address change BASE in equates 0050 005A 005B 0005 0010 0020 0040 BASE CLKCMD CLK...
Page 29: ...DIGITS TO WRITE 1 SET HOLD BIT AND WRITE IT OUT DECREMENT DIGIT COUNT jSKIP THIS NEXT BIT IF NOT DONE jCLEARA jCLEAR HOLD BIT SHOW THAT THE TIME IS NOW jWHATEVER PRINT THE STUFF WE RE DONE GET THE DIG...
Page 30: ...DIGIT jNO jOTHERWISE GET THE DIGIT jAND SET 24 HOUR MODE WRT2 WRT3 JMP MOV OUT POP ADI WRTI A C OSH WRT3 S HOLD WRT2 A C 03H jWAS IT THE DAYS 10 DIGIT jNO jOTHERWISE GET THE DIGIT jAND SET NON LEAP Y...
Page 31: ...R jPRINT TWO SPACES A PCHAR PRINTWO A I PCHAR PRINTWO A I PCHAR PRINTWO jPRINT TWO MORE DIGITS j PRINT A SLASH jPRINT THE LAST TWO DIGITS WE RE DONE this routine prints two digits from the clock It is...
Page 32: ...DBB01 CALL RDDGT READ IT AGAIN 0234 B8 CMP B COMPAREIT TO THE ONE WE JUST READ 0235 CA2F02 JZ FOR2 LOOP IF IT S THE SAME 0238 C32102 JMP FOR1 OTHERWISEPRINT IT AGAIN 023B E5 GETCHAR PUSH H SAVEHL 023C...
Page 33: ...TO OPERATING SYSTEM ODH OAH ODH OAH COMMAND ODH OAH THAT WAS NOT ONE OF THE ABOVE COMMAi IDS ODH OAH PLEASE TRY AGAIN DB ODH OAH WHAT IS THE TIME 24 HOUR FORMAT HH MM SS DB ODH OAH WHAT IS THE DATE M...
Page 34: ...the board addressed but their relative addresses are shown in the I O Port Map section of this manual The reprint below should explain everything you want to know about the 8259A and how to program i...
Page 35: ...so that I O servicing has little or no effect on the total system throughput There are two basic methods of handling the I O chores in a system status polling and interrupt servicing The status poll m...
Page 36: ...under software control using the EI Enable Inter rupt or 01 Disable Interrupt instructions These in structions either set or reset an internal interrupt enable flip flop The output of this flip flop...
Page 37: ...n be used to indicate to other system bus masters not to gain control of the system bus during the interrupt acknowl edge sequence A HOLD request won t be honored while LOCK is iow The 8259A is now re...
Page 38: ...upt Type 3 INTO is a conditional one byte interrupt instruction which selects interrupt Type 4 if the OF flag trap on overflow is set All the software interrupts vector program execu tion as the hardw...
Page 39: ...is selected the a output of the edge sense latch is rendered useless This means the level of the IR input is in complete control of interrupt generation the input won t be disarmed once acknowledged W...
Page 40: ...tion is transferred via this bus Vffi 2 Fffi 3 D7 DO 4 11 INT 1 0 Cascade Lines The CAS lines form a private 8259A bus to control a multi ple 8259A structure These pins are outputs for a master 8259A...
Page 41: ...ond interrupt vector byte for both 4 and 8 byte intervals The MSB of the interrupt vector address is placed on the data bus during the third INTA pulse Contents of the third interrupt vector byte is s...
Page 42: ...r ther requests of the same or lower priority are inhibited Irom generating an interrupt to the microprocessor A higher priority request though can generate an inter rupt thus vectoring program execut...
Page 43: ...he highest priority routine of the routines in service is finished 44 The main advantage of using the non specific EOI com mand is that IR level specification isn t necessary as in the Specific EOI Co...
Page 44: ...ific EOIcommand is executed When this happens bit 4 in the ISR is reset IR4 then becomes the lowest priority and IRS becomes the highest as in 13B 151 156 155 154 153 152 151 ISO A ISRSTATUS BEFORE PR...
Page 45: ...o IRO IR7 Any IRinput can be masked by writing to the IMRand setting the appropriate bit Likewise any IR in put can be enabled by clearing the correct IMR bit There are various uses for masking off in...
Page 46: ...the first INTA pulse If on any IR input the request goes inactive before the first INTA pulse the 8259A will respond as if IR7 was active In any design in which there s a possibility of this happening...
Page 47: ...s poll method of device moni toring by using the poll command This makes the status of the internallA inputs available to the user via software control The poll command offers an alterna tive to the i...
Page 48: ...ill take advantage of the 8259A s prioritizing features For those cases when the 8259A is using the poll command only and not the interrupt method each 8259A must receive an initialization sequence in...
Page 49: ...be the last choice when assign ing slaves to IR inputs Special Fully Nested Mode Depending on the application changes in the nested structure of the cascade mode may be desired This is because the ne...
Page 50: ...ization flow of the 8259A Both ICW1 and ICW2 must be issued for any form of 8259A operation However ICW3 and ICW4 are used only if designated so in ICW1 Determining the neces sity and use of each ICW...
Page 51: ...a 4 byte ad dress interval is to be used ADI must equal 1 For an 8 byte address interval ADI must equal O The state of ADI is ignored when the 8259A is in the MCS 86 88 mode LTIM The LTIM bit is used...
Page 52: ...on SFNM The SFNM bit designates selection of the special fully nested mode which is used in conjunction with the cascade mode Only the master should be programmed in the special fully nested mode to a...
Page 53: ...categories of operation associated with OCW3 interrupt status and interrupt masking Bit definition of OCW3 is as follows AIS AA P SMM ESMM The AIS bit is used to select the ISA or IAA for the read reg...
Page 54: ...EOI MCS 80 85 27 ICW4 H I 0 0 0 0 0 I I I Non buffered mode IIEOI 8086 8088 28 ICW4 I 0 0 0 0 I 0 0 0 Buffered mode slave no AEOI MCS 80 85 2Q ICW4 J I 0 0 0 0 0 0 1 Bufferedmode slave noAEOI 8086 808...
Page 55: ...that Intel advises that using the automatic end of interrupt mode in a master slave environment is not recommended ROUTINE FOR INITIALIZING MASTER AND SLAVE 8259As ON THE SYSTEM SUPPORT 1 this program...
Page 56: ...ng these instructions please send back the board concerned to CompuPro A charge of 40 00 will be assigned to any board whose owner wishes to disable interrupts but who does not under stand these instr...
Page 57: ...ctions See the section called Interval Timer Options in the hardware configuration section of this manual for more detailed information The interval timer s outputs also appear at J7 and J8 for connec...
Page 58: ...ined by assignment of pnority levels BLOCK DIAGRAM I I I j GATE ClK 0 1 DATA 0 Do 8 BUS BUFFER COUNTER 0 OUT 0 I I I RD ClK 1 COUNTER 0 GATE 1 l AO I I I t J I ClK 2 OUT cs J CONTROL WORD REGISTER OUT...
Page 59: ...gister The information stored In this register controls the operational MODE of each counter selection of binary or BCD counting and the loading of each count register The Control Word Register can on...
Page 60: ...actual counting operatIon of each counter IS completely independent and additIonal logIc is provided on chip so that the usual problems assocIated wIth efficient monItoring and management of external...
Page 61: ...put goes high the counter will start from the initial count Thus the gate input can be used to synchronize the counter When this mode is set the output will remain high until after the count register...
Page 62: ...8 No 9 Note The exclusive addresses of each counter s count register make the task of po og amming the 8253 a very simple matter and maximum effective use of the device will result if this feature is...
Page 63: ...ve Generator CLOCK OUTPUT In 4 OUTPUT In 51 MODE 4 Software Triggered Strobe CLOCK OUTPUT 0 LOAOn GATE L J OUTPUT 0 U MODE 5 Hardware Triggered Strobe CLOCK GATE I4 0 LJ OUTPUT In 41 GATE 4 3 4 1 OUTP...
Page 64: ...torage register so that ItS contents contain an accurate stable quantity The programmer then Issues a normal read command to the selected counter and the contents of the latched register IS available...
Page 65: ...The quickest and surest way to re align the math processor stack is to reset the system The user should not attempt to program these chips without a data sheet see pages 70 81 The program below can b...
Page 66: ...waway set up ok message print it test passed return to CP M length of table into reg c byte from table into reg a output byte from table to 9512 67 test routine for 9511 0103 114401 START LXI D GREET...
Page 67: ...NG BDOS 0 D ERRMSG C PSTRING BOOS 0 DB DB DB DB length of table into reg c hl reg points to table 2 input data from 9512 match with known result error if no match else update pointer into table decrem...
Page 68: ...atical capability of a wide variety of processor oriented systems Chebyshev polynomials are used in the implementation of the APU algorithms All transfers including operand result status and command i...
Page 69: ...data format is specified If bit 5 is a 0 floating point format is specified Bit 6 selects the precision of the data to be operated upon by fixed point commands only if bit 5 0 bit 6 must be 0 If bit 6...
Page 70: ...Logarilhm of A 0 9 R B U U 5 Z E POPF Slack Pop I 8 B C D A 5 Z PTOF Stack Push 1 7 A A B C 5 Z PUPI Push n onto Slack 1 A R A B C 5 Z PWR BAPower Function 0 B R C U U 5 Z E SIN Sine of A radians 0 2...
Page 71: ...e ex pressed as 1 2345x 105 The sixth digit has been discarded In most applications where the dynamic range of values to be represented Is large the loss of significance and hence accuracy of results...
Page 72: ...te until execution is complete and will then be raised to permit completion of the stack access 3 The 8231A is not busy and data removal has been re quested READY will be pulledlow for the lengthof ti...
Page 73: ...2 Cos 1X 1 2X2 1 74 In general the next term in the Chebyshev series can be recursively derived from the previous term as follows H T n X 2X IT n 1 X T n 2 X n 2 1 7 Common logarithms are computed by...
Page 74: ...t multiply and divide operations The 8232 s floating point arithmetic is a subset of the proposed IEEE standard It can be easily interfaced to enhance the computational capabilities of the host microp...
Page 75: ...op that generates the END output Thus such continuous reading could conflict with internal logic setting of the END flip flop at the end of command execution AFN D 1263C Symbol Pin No Type Name and De...
Page 76: ...the WR and I fI5 Inputs are both HIGH the READY output goes LOW with the CS input in anticipa tion of a transaction If WR goes LOW to initiate a write transaction with proper signals established on t...
Page 77: ...ed In TOS exchanging single precision operands located at TOS and NOS as well as pushing and popping single or double precision operands See also the sections on status register and operand formats Th...
Page 78: ...Z Exponent Underflow U Exponent Overflow V Divide Exception DI 5 If the exponent field of A is zero R or A will be zero AFN I263C 79 Hex1 Stack Contents2 Status Flags Instructton Description Code Alt...
Page 79: ...after READY goes HIGH the RD Input can return HIGH to complete the transaction 6 The CS and Ao inputs can change after appropriate hold time requirements are satisfied see timing dia gram 7 Repeat th...
Page 80: ...to divide by zero is made Cleared to zero otherwise Bit 4 Reserved Bit 5 Zero Z When 1 this bit indicates that the result returned to TOS after a command Is zero Cleared to zero otherwise Bit 6 Sign...
Page 81: ...um accuracy with no anomalies This means that a mathematically unsophisticated user will not be surprised by some of the results It Is probably possible for a sophisticated user to obtain reliable res...
Page 82: ...rring to the selected block of 16 I O addresses The address inputs to Ul9 are connected to address bits A3 Al Therefore each of the outputs of U19 will be active for two I O addresses Most of the chip...
Page 83: ...f U18 The other inputs to U18 are the inverted and non inverted All from the 5 100 bus The outputs of U18 will go low depending on the state of All which selects one or the other of the two RAM ROM lo...
Page 84: ...nterrupt acknowledge cycles to insure that a proper response is always sent in even the fastest of systems This PHANT signal is inverted by a section of U24 and becomes the PHNTM signal which is in tu...
Page 85: ...s come to expect from these type of LSI parts such as all the others on the board Instead the R W signal is a status signal telling the UART which direction the data bus should be in and the CE input...
Page 86: ...42 to be tri stated and the outputs of U39 to be enabled This assumes the READ bit is set high The master clock for the clock chip is provided by crystal X3 a 32 768 Khz watch crystal C12 and Cll C12...
Page 87: ...low the SHIFT LOAD input will be high so the clock can now shift the data through the register Since the G input was high a low will appear at the QH output after the falling edge of the next clock en...
Page 88: ...gister quad latch tri state dual one shot octal bus buffer quad XNOR O C octal latch hex bus buffer octal non inverting buffer octal inverting buffer octal comparator R5 232 driver R5 232 receiver OK...
Page 89: ...C9 10 C14 C13 C11 C12 R3 R1 R2 18 19 23 24 R22 27 30 33 R8 16 38 R10 13 15 20 21 26 R9 R14 R4 7 36 R37 R17 31 32 34 35 MECHANICAL COMPONENTS 1 circuit board 46 low profile sockets 3 8 position DIP swi...
Page 90: ...COMPONENT LAYOUT CD...
Page 91: ...HLOA 16 92 RJl 32 52 25LS2521 19 R17 XA 0 33 8 18 2 SYSTEM SUPPORT 1 COMPUPRO division GODBOUT ELECTRONICS 162G Pege 1 01 3 28 ROY In 16 52 12 01981...
Page 92: ...of 3 1S81 IRQl I IRQ2 U14 IRQJ IRQ SLAVE I Q5 I IRQ6 IRQ i8259A J Q A 74l S A 6MHz C WR Oy 93 5 12 021 6KRf J QJ OJ BATTERY K5 22 IRQ I Ql U15 IRQ2 MASTE IRQJ 18259A IRQ IRQ5 OUT 2 D1 OUTI D6 J 6 OUH...
Page 93: ...20 lD HEADER D825 H d U3I 81LS95i9Z U38 1415244 162G Pege 3 of 3 DB DB6 DB5 DB4 us RD U6 DB3 WR 0 1651 DB2 UART I OBI DB0 CLEAR RESET A0 A0 elD Al Al sDUT 45 R W l IT U45 BReL GND 4 5 068 I U4 A0 OK M...
Page 94: ...on Ba t tery Backup Global Extended Address PHANTOM Response Theory of Operation Parts List Parts Placement Diagram PHANTOM Response Options Programming Considerations also see under individual functi...
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