Global American 3308290, User Manual

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Wide, pipelined internal data path architecture
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Optimized transmit (Tx) and receive (Rx) queues
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32 KB configurable Rx and Tx first-in/first-out (FIFO)
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IEEE 802.3x*-compliant flow-control support with software controllable pause
times and threshold values
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Programmable host memory Rx buffers (256 B-16 KB)
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Descriptor ring management hardware for Tx and Rx
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Mechanism for reducing interrupts from Tx/Rx operations
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Integrated PHY for 10/100/1000 Mbps (full- and half-duplex)
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IEEE 802.3ab* auto-negotiation support
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IEEE 802.3ab PHY compliance and compatibility
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Tx/Rx IP, TCP, and UDP checksum offloading
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Tx TCP segmentation
2.9 PCI Bus Components
The PCI interface edge connector is connected to the PCI bus on the backplane. The PCI
bus edge connector is shown below.
Figure 2-20: PCI Edge Connector
The PCI is interfaced to four standard PCI expansion cards on a compatible PICMG 1.3
backplane.
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