GD32W51x User Manual
583
Figure 17-70. Timing chart of up counting mode, change TIMERx_CAR ongoing
TIMER_CK
CEN
CNT_CLK(PSC_CLK)
CNT_REG
5E
5F
60
61
62
63
00
01
02
03
04
05
06
07
Update event (UPE)
Update interrupt flag (UPIF)
Auto-reload register
65
63
change CAR Vaule
CNT_REG
5E
5F
60
61
62
63
64
65
00
01
02
62
63
00
Update event (UPE)
Update interrupt flag (UPIF)
Auto-reload register
65
63
change CAR Vaule
65
63
Auto-reload shadow
register
...
Hardware set
Hardware set
Software clear
Hardware set
ARSE = 0
ARSE = 1
Timer debug mode
When the Cortex
™
-M33 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0
register set to 1, the TIMERx counter stops.