GD32W51x User Manual
464
The dead time delay insertion ensures that no two complementary signals drive the active
state at the same time.
When the channel (x) match (TIMERx counter = CHxVAL) occurs, OxCPRE will be toggled
because under PWM0 mode. At point A in the
Figure 17-18. Complementary output with
CHx_O signal remains at the low value until the end of the deadtime
delay, while CHx_ON will be cleared at once. Similarly, at point B when counter match
(counter = CHxVAL) occurs again, OxCPRE is cleared, CHx_O signal will be cleared at once,
while CHx_ON signal remains at the low value until the end of the dead time delay.
Sometimes, we can see corner cases about the dead time insertion. For example:
The dead time delay is greater than or equal to the CHx_O duty cycle, then the CHx_O signal
is always the inactive value. (As show in the
Figure 17-18. Complementary output with dead-time
)
The dead time delay is greater than or equal to the CHx_ON duty cycle, then the
CHx_ON signal is always the inactive value.
Figure 17-18. Complementary output with dead-time insertion.
0
CHxVAL
CAR
CxOPRE
CHx_O
CHx_ON
Deadtime
Corner case Deadtime > pulse width
CHx_O
CHx_ON
Deadtime
Pulse width
Deadtime
A
B
Break function
In this function, the output CHx_O and CHx_ON are controlled by the POEN, IOS and ROS
bits in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register and
cannot be set both to active level when break occurs. The break sources are input break pin
and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by
setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by
the BRKP bit in TIMERx_CCHP.
When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and
CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the
