GD32W51x User Manual
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5.3.4.
Power saving modes
After a system reset or a power reset, the GD32W51x MCU operates at full function and all
power domains are active. Users can achieve lower power consumption through slowing
down the system clocks (HCLK, PCLK1, and PCLK2) or gating the clocks of the unused
peripherals or configuring the LDO output voltage by LDOVS bits in PMU_CTL0 register. The
LDOVS bits should be configured only when the PLL is off. Besides, five power saving modes
are provided to achieve even lower power consumption, they are Sleep mode, Deep-sleep
mode, Standby, SRAM_sleep and Wi-Fi_sleep mode.
Sleep mode
The Sleep mode is corresponding to the SLEEPING mode of the Cortex
®
-M33. In Sleep mode,
only clock of Cortex
®
-M33 is off. To enter the Sleep mode, it is only necessary to clear the
SLEEPDEEP bit in the Cortex
®
-M33 System Control Register, and execute a WFI or WFE
instruction. If the Sleep mode is entered by executing a WFI instruction, any interrupt can
wake up the system. If it is entered by executing a WFE instruction, any wakeup event can
wake up the system (If SEVONPEND is 1, any interrupt can wake up the system, refer to
Cortex-M33 Technical Reference Manual). The mode offers the lowest wakeup time as no
time is wasted in interrupt entry or exit.
According to the SLEEPONEXIT bit in the Cortex
®
-M33 System Control Register, there are
two options to select the Sleep mode entry mechanism.
Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as
WFI or WFE instruction is executed.
Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it
exits from the lowest priority ISR.
Deep-sleep mode
The Deep-sleep mode is based on the SLEEPDEEP mode of the Cortex
®
-M33. In Deep-sleep
mode, all clocks in the 1.2V domain are off, and all of IRC16M, HXTAL and PLLs are disabled.
The contents of SRAM0 and registers are preserved. The LDO can operate normally or in low
power mode depending on the LDOLP bit in the PMU_CTL0 register. Before entering the
Deep-sleep mode, it is necessary to set the SLEEPDEEP bit in the Cortex
®
-M33 System
Control Register, and clear the STBMOD bit in the PMU_CTL0 register. Then, the device
enters the Deep-sleep mode after a WFI or WFE instruction is executed. If the Deep-sleep
mode is entered by executing a WFI instruction, any interrupt from EXTI lines can wake up
the system. If it is entered by executing a WFE instruction, any wakeup event from EXTI lines
can wake up the system (If SEVONPEND is 1, any interrupt from EXTI lines can wake up the
system, refer to Cortex-M33 Technical Reference Manual). When exiting the Deep-sleep
mode, the IRC16M is selected as the system clock. Notice that an additional wakeup delay
will be incurred if the LDO operates in low power mode.
The low-driver mode in Deep-sleep mode can be entered by configuring the LDEN, LDNP,