GD32W51x User Manual
1000
SPICKSS[1:0]
Clock source
SITYP[1:0] Sam pling point
Description
clock signal
10
CKOUT/2 signal
(Generated at the
rising edge of
CKOUT)
xx
Rising edge of
each second
CKOUT signal
The external sigma delta
modulator divides the CKOUT
signal into 2 frequencies to
generate the serial input
communication clock. The data is
sampled at the falling edge of
every second CKOUT.
11
CKOUT/2 signal
(Generated at the
falling edge of
CKOUT)
xx
Falling edge of
each second
CKOUT signal
The external sigma delta
modulator divides the CKOUT
signal into 2 frequencies to
generate the serial input
communication clock. The data is
sampled at the rising edge of
every second CKOUT.
According to
Table 30-2. SPI interface clock configuration
, the sequence diagram of SPI
data transmission is shown in the figure below.
Figure 30-2. The sequence diagram of SPI data transmission
SITYP[1:0]=0
SPICKSS[1:0]=0
SITYP[1:0]=1
DATAINx
CKINx
Serial input clock source for SPI interface
SITYP[1:0]=0
SPICKSS[1:0]=1
SITYP[1:0]=1
DATAINx
CKOUT
Serial output clock source for SPI interface
SITYP[1:0]
DATAINx
CKOUT
Serial output clock source for SPI interface
SPICKSS[1:0]=3
SPICKSS[1:0]=2
SITYP[1:0]
Note:
if SPI data interface is adopted, the frequency range of clock source is 0-20MHz and
less than f
HPDFCLK
/4.
