GD32L23x User Manual
112
The source clock is divided by (PREDV + 1).
0000: input to PLL not divided
0001: input to PLL divided by 2
0010: input to PLL divided by 3
0011: input to PLL divided by 4
0100: input to PLL divided by 5
0101: input to PLL divided by 6
0110: input to PLL divided by 7
0111: input to PLL divided by 8
1000: input to PLL divided by 9
1001: input to PLL divided by 10
1010: input to PLL divided by 11
1011: input to PLL divided by 12
1100: input to PLL divided by 13
1101: input to PLL divided by 14
1110: input to PLL divided by 15
1111: input to PLL divided by 16
4.3.13.
Configuration register 2 (RCU_CFG2)
Address offset: 0x30
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADCPS
C[3:2]
Reserved
IRC16MDIVSEL
USART1SEL[1:0]
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
USBDSEL
LPUARTSEL[1:0]
LPTIMERSEL[1:0]
ADCSEL
I2C2SEL[1:0]
I2C1SEL[1:0]
I2C0SEL[1:0]
USART0SEL[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:30
ADCPSC[3:2]
Bit 3 and bit 2 of ADCPSC
see bits 15:14 of RCU_CFG0
30:21
Reserved
Must be kept at reset value
20:18
IRC16MDIVSEL
CK_IRC16M divided clock selection
0xx: CK_IRC16MDIV select CK_IRC16M
100: CK_IRC16MDIV select CK_IRC16M divided by 2
101: CK_IRC16MDIV select CK_IRC16M divided by 4
110: CK_IRC16MDIV select CK_IRC16M divided by 8
111: CK_IRC16MDIV select CK_IRC16M divided by 16
