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GigaDevice Semiconductor GD32F403 Series User Manual Download Page 27

                                                                                                     

GD32F403xx User Manual

 

27 

 

Figure 1-1. The structure of the Cortex

®

-M4 processor 

Nested

Vectored

Interrupt

Controller

(NVIC)

Cortex-M4 core

Floating Point

Unit(FPU)

Flash Patch

Breakpoint

(FPB)

Cortex-M4 processor

Memory

Protection

Unit(MPU)

Data

Watchpoint

And Trace

(DWT)

AHB

Access port

(AHB-AP)

Bus Matrix

Instrumentation

Trace Macrocell

(ITM)

Trace Port

Interface Unit

(TPIU)

Serial-Wire

Or JTAG

Debug Port

(SWDP or SWJ-

DP)

CoreSight

ROM table

Wake-up

Interrupt

Controller

(WIC)

Interrupts and 
Power control

Trace Port

Interface

System

AHB-Lite

System

interface

DCode

AHB-Lite

Data

interface

ICode

AHB-Lite

Data

interface

Serial-Wire or

JTAG Debug

Interface

PPB APB

Debug system

interface

 

1.2. 

System architecture 

A 32-bit multilayer bus is implemented in the

 

GD32F403xx devices, which enables parallel 

access paths between multiple masters and slaves in the system. The multilayer bus consists 

of  an  AHB  interconnect matrix, one AHB  bus and  two APB buses. The  interconnection 

relationship of the AHB interconnect matrix is sho

wn below. In the following table, “1” indicates 

the  corresponding master  is  able  to  access the  corresponding slave through  the  AHB 

interconnect matrix, while the  blank means the  corresponding master cannot access the 

corresponding slave through the AHB interconnect matrix.  

Table 1-1. The interconnection relationship of the AHB interconnect matrix 

 

IBUS  DBUS  SBUS  DMA0  DMA1 

FMC-I 

1 

 

 

 

 

 

 

 

 

FMC-D 

 

 

1 

 

 

1 

1 

SRAM 

1 

1 

1 

1 

1 

EXMC 

1 

1 

1 

1 

1 

AHB 

 

 

 

 

1 

1 

1 

Summary of Contents for GD32F403 Series

Page 1: ...GigaDevice Semiconductor Inc GD32F403xx Arm Cortex M4 32 bit MCU User Manual Revision 2 6 Jul 2022 ...

Page 2: ...onfiguration registers 37 2 Flash memory controller FMC 39 2 1 Introduction 39 2 2 Main features 39 2 3 Function description 39 2 3 1 Flashmemory architecture 39 2 3 2 Read operations 40 2 3 3 Unlock the FMC_CTLx registers 40 2 3 4 Page erase 41 2 3 5 Mass erase 42 2 3 6 Main flash programming 44 2 3 7 Option bytes Erase 45 2 3 8 Option bytes modify 46 2 3 9 Option bytes description 46 2 3 10 Page...

Page 3: ...domain 59 3 3 2 VDD VDDA power domain 60 3 3 3 1 2V power domain 62 3 3 4 Power saving modes 62 3 4 PMU registers 66 3 4 1 Control register PMU_CTL 66 3 4 2 Control andstatus register PMU_CS 68 4 Backup registers BKP 70 4 1 Introduction 70 4 2 Main features 70 4 3 Function description 70 4 3 1 RTC clock calibration 70 4 3 2 Tamper detection 70 4 4 BKP registers 72 4 4 1 Backup data register x BKP_...

Page 4: ... register RCU_ADDCTL 110 5 3 15 Additional clock interrupt register RCU_ADDINT 111 5 3 16 APB1 additional reset register RCU_ADDAPB1RST 112 5 3 17 APB1 additional enable register RCU_ADDAPB1EN 112 6 Clock trim controller CTC 114 6 1 Overview 114 6 2 Characteristics 114 6 3 Function overview 114 6 3 1 REF sync pulse generator 115 6 3 2 CTC trim counter 115 6 3 3 Frequency evaluation and automatical...

Page 5: ...unction 139 8 3 9 GPIO I O compensationcell 139 8 4 Remapping function I O and debug configuration 139 8 4 1 Introduction 139 8 4 2 Main features 140 8 4 3 JTAG SWD alternate function remapping 140 8 4 4 ADC AF remapping 141 8 4 5 TIMERAF remapping 141 8 4 6 USART AF remapping 143 8 4 7 I2C0 AF remapping 143 8 4 8 SPI I2S AF remapping 144 8 4 9 CAN AF remapping 144 8 4 10 Ethernet AF remapping 145...

Page 6: ...2 Free data register CRC_FDATA 167 9 4 3 Control register CRC_CTL 168 10 Direct memory access controller DMA 169 10 1 Overview 169 10 2 Characteristics 169 10 3 Block diagram 170 10 4 Function overview 170 10 4 1 DMA operation 170 10 4 2 Peripheral handshake 172 10 4 3 Arbitration 172 10 4 4 Address generation 172 10 4 5 Circular mode 173 10 4 6 Memory to memory mode 173 10 4 7 Channel configurati...

Page 7: ...4 Functionaloverview 193 12 4 1 Foreground calibration function 193 12 4 2 ADC clock 194 12 4 3 ADC enable 194 12 4 4 Routine sequence 194 12 4 5 Operation modes 194 12 4 6 Conversion result threshold monitor function 197 12 4 7 Data storagemode 197 12 4 8 Sample time configuration 198 12 4 9 External triggerconfiguration 198 12 4 10 DMA request 199 12 4 11 ADC internal channels 199 12 4 12 Progra...

Page 8: ...conversion 222 13 4 DAC registers 223 13 4 1 Control register DAC_CTL 223 13 4 2 Software trigger register DAC_SWT 225 13 4 3 DAC0 12 bit right aligned data holding register DAC0_R12DH 226 13 4 4 DAC0 12 bit left aligned data holding register DAC0_L12DH 226 13 4 5 DAC0 8 bit right aligned data holding register DAC0_R8DH 227 13 4 6 DAC1 12 bit right aligned data holding register DAC1_R12DH 227 13 4...

Page 9: ...248 15 4 4 RTC prescaler low register RTC_PSCL 249 15 4 5 RTC divider high register RTC_DIVH 249 15 4 6 RTC divider low register RTC_DIVL 249 15 4 7 RTC counter high register RTC_CNTH 250 15 4 8 RTC counter low register RTC_CNTL 250 15 4 9 RTC alarm high register RTC_ALRMH 251 15 4 10 RTC alarm low register RTC_ALRML 251 16 Timers TIMERx 252 16 1 Advanced timer TIMERx x 0 7 253 16 1 1 Overview 253...

Page 10: ... 2 Characteristics 398 17 3 Function overview 399 17 3 1 USART frame format 400 17 3 2 Baud rate generation 401 17 3 3 USART transmitter 401 17 3 4 USART receiver 402 17 3 5 Use DMA for data buffer access 404 17 3 6 Hardware flow control 405 17 3 7 Multi processor communication 406 17 3 8 LIN mode 407 17 3 9 Synchronous mode 408 17 3 10 IrDA SIRENDEC mode 409 17 3 11 Half duplex communication mode...

Page 11: ...s and interrupts 443 18 4 Register definition 445 18 4 1 Control register 0 I2C_CTL0 445 18 4 2 Control register 1 I2C_CTL1 447 18 4 3 Slave address register 0 I2C_SADDR0 448 18 4 4 Slave address register 1 I2C_SADDR1 448 18 4 5 Transfer buffer register I2C_DATA 449 18 4 6 Transfer status register 0 I2C_STAT0 449 18 4 7 Transfer status register 1 I2C_STAT1 452 18 4 8 Clock configure register I2C_C...

Page 12: ...I_CRCPOLY 492 19 5 6 RX CRC register SPI_RCRC 492 19 5 7 TX CRC register SPI_TCRC 493 19 5 8 I2S control register SPI_I2SCTL 494 19 5 9 I2S clock prescaler register SPI_I2SPSC 495 19 5 10 Quad SPI modecontrol register SPI_QCTL of SPI0 496 20 Secure digital input output interface SDIO 498 20 1 Introduction 498 20 2 Main features 498 20 3 SDIO bus topology 498 20 4 SDIO functional description 501 20...

Page 13: ... register SDIO_DATATO 552 20 8 8 Data length register SDIO_DATALEN 552 20 8 9 Data control register SDIO_DATACTL 553 20 8 10 Data counter register SDIO_DATACNT 554 20 8 11 Status register SDIO_STAT 555 20 8 12 Interrupt clear register SDIO_INTC 556 20 8 13 Interrupt enable register SDIO_INTEN 557 20 8 14 FIFO counter register SDIO_FIFOCNT 559 20 8 15 FIFO data register SDIO_FIFO 560 21 External me...

Page 14: ... data0 register CAN_TMDATA0x x 0 2 628 22 4 12 Transmit mailbox data1 register CAN_TMDATA1x x 0 2 629 22 4 13 Receive FIFO mailbox identifier register CAN_RFIFOMIx x 0 1 629 22 4 14 Receive FIFO mailbox property register CAN_RFIFOMPx x 0 1 630 22 4 15 Receive FIFO mailbox data0 register CAN_RFIFOMDATA0x x 0 1 630 22 4 16 Receive FIFO mailbox data1 register CAN_RFIFOMDATA1x x 0 1 631 22 4 17 Filter...

Page 15: ...IFO 642 23 5 6 Operation guide 644 23 6 Interrupts 649 23 7 Registerdefinition 651 23 7 1 Global control and status registers 651 23 7 2 Host control and status registers 672 23 7 3 Device control andstatus registers 684 23 7 4 Power andclock control register USBFS_PWRCLKCTL 708 24 Revision history 709 ...

Page 16: ...Analog configuration 138 Figure 8 5 Alternate function configuration 139 Figure 9 1 Block diagram of CRC calculation unit 166 Figure 10 1 Block diagram of DMA 170 Figure 10 2 Handshake mechanism 172 Figure 10 3 DMA interrupt logic 174 Figure 10 4 DMA0 requestmapping 175 Figure 10 5 DMA1 requestmapping 176 Figure 12 1 ADCmodule block diagram 193 Figure 12 2 Single operation mode 194 Figure 12 3 Con...

Page 17: ...16 15 CAPWM timechart 267 Figure 16 16 Complementary output with dead time insertion 270 Figure 16 17 Output behavior in response to a break The break high active 271 Figure 16 18 Example of counter operation in encoder interface mode 272 Figure 16 19 Example of encoder interface mode with CI0FE0 polarity inverted 272 Figure 16 20 Hall sensor is used to BLDC motor 274 Figure 16 21 Hall sensor timi...

Page 18: ...ing chart of PSC value change from 0 to 2 373 Figure 16 61 Timing chart of up counting mode PSC 0 2 374 Figure 16 62 Timing chart of up counting mode change TIMERx_CAR on the go 374 Figure 16 63 Channels input capture principle 375 Figure 16 64 Output compare under three modes 377 Figure 16 65 Basic timer block diagram 389 Figure 16 66 Timing chart of internal clock divided by 1 390 Figure 16 67 T...

Page 19: ...A typical simplex connection Master Transmit only Slave Receive 462 Figure 19 7 A typical bidirectional connection 462 Figure 19 8 Timing diagram of TI master mode with discontinuous transfer 464 Figure 19 9 Timing diagram of TI master mode with continuous transfer 465 Figure 19 10 Timing diagram of TI slave mode 465 Figure 19 11 Timing diagram of NSS pulse with continuous transmit 466 Figure 19 1...

Page 20: ... 01 CHLEN 1 CKPL 0 477 Figure19 40 PCM standard short frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 1 478 Figure 19 41 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 478 Figure 19 42 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 1 478 Figure 19 43 PCM standard long frame synchronization mode timing diagram...

Page 21: ...562 Figure 21 2 EXMCmemory banks 563 Figure 21 3 Four regions of bank0 address mapping 564 Figure 21 4 NAND PC Card address mapping 565 Figure 21 5 Diagram of bank1 common space 565 Figure 21 6 Mode 1 read access 570 Figure 21 7 Mode 1 write access 570 Figure 21 8 Mode A read access 571 Figure 21 9 Mode A write access 572 Figure 21 10 Mode 2 B read access 573 Figure 21 11 Mode 2 write access 574 F...

Page 22: ...t mode filter 609 Figure 22 10 16 bit list mode filter 609 Figure 22 11 The bit time 613 Figure 23 1 USBFS block diagram 636 Figure 23 2 Connection with host or device mode 637 Figure 23 3 Connection with OTG mode 638 Figure 23 4 State transition diagram of host port 638 Figure 23 5 HOST mode FIFO space in SRAM 643 Figure 23 6 Host mode FIFO access registermap 643 Figure 23 7 Device mode FIFO spac...

Page 23: ...te function remapping 143 Table 8 8 I2C0 alternate function remapping 144 Table 8 9 SPI I2S alternate function remapping 144 Table 8 10 CAN alternate function remapping 144 Table 8 11 ENET alternate function remapping 145 Table 8 12 CTC alternate function remapping 145 Table 8 13 OSC32 pins configuration 146 Table 8 14 OSC pins configuration 146 Table 10 1 DMA transfer operation 171 Table 10 2 int...

Page 24: ...2S bitrate calculation formulas 480 Table 19 8 Audio sampling frequency calculation formulas 481 Table 19 9 Direction of I2S interface signals for each operation mode 481 Table 19 10 I2S interrupt 486 Table 20 1 SDIO I O definitions 502 Table 20 2 Command format 508 Table 20 3 Card command classes CCCs 509 Table 20 4 Basic commands class 0 511 Table 20 5 Block Oriented read commands class 2 513 Ta...

Page 25: ... 1 related registers configuration 570 Table 21 7 Mode A related registers configuration 572 Table 21 8 Mode 2 B related registers configuration 574 Table 21 9 Mode C related registers configuration 576 Table 21 10 Mode D related registers configuration 578 Table 21 11 Multiplex mode related registers configuration 580 Table 21 12 Timing configurations of synchronousmultiplexed read mode 583 Table...

Page 26: ...ced make the Cortex M4 processor suitable for market products that require microcontrollers with high performance and low power consumption The Cortex M4 processor is based on the ARMv7 architecture and supports a powerful and scalable instruction set including general dataprocessing I O control tasks advanced data processing bit field manipulations and DSP Somesystem peripherals listed below are ...

Page 27: ...Serial Wire or JTAG Debug Interface PPB APB Debug system interface 1 2 System architecture A 32 bit multilayer bus is implemented in the GD32F403xx devices which enables parallel access pathsbetweenmultiplemastersand slavesinthesystem Themultilayerbusconsists of an AHB interconnect matrix one AHB bus and two APB buses The interconnection relationshipof theAHBinterconnectmatrixisshownbelow Inthefol...

Page 28: ...egions The System regions include the internal SRAM region and the Peripheral region DMA0 and DMA1 are the buses of DMA0 and DMA1 respectively There are also several slaves connected with the AHB interconnect matrix including FMC I FMC D SRAM EXMC AHB APB1 and APB2 FMC I is the instruction bus of the flash memory controller whileFMC D is the databus of the flash memory controller SRAM is on chip s...

Page 29: ...GPIOC GPIOD GPIOE GPIOF TIMER0 TIMER7 TIMER8 10 UART3 4 CAN1 TIMER 11 13 ADC0 2 AHB Peripherals FMC USBFS CRC RCU GP DMA 12 chs Slave EXMC 12 bit SAR ADCs Powered By VDDA ARM Cortex M4 Processor Fmax 168MHz SW JTAG System DCode ICode AHB Matrix APB2 Fmax 168MHz APB1 Fmax 84MHZ CTC SDIO 1 3 Memory map The Arm Cortex M4processorisstructuredinHarvardarchitecturewhichcanuseseparate buses to fetchinstr...

Page 30: ...herals External device AHB3 0xA000 0000 0xA000 0FFF EXMC SWREG External RAM 0x9000 0000 0x9FFF FFFF EXMC PC CARD 0x7000 0000 0x8FFF FFFF EXMC NAND 0x6000 0000 0x6FFF FFFF EXMC NOR PSRAM SRA M Peripheral AHB1 0x5000 0000 0x5003 FFFF USBFS 0x4008 0000 0x4FFF FFFF Reserved 0x4004 0000 0x4007 FFFF Reserved 0x4002 BC00 0x4003 FFFF Reserved 0x4002 B000 0x4002 BBFF Reserved 0x4002 A000 0x4002 AFFF Reserv...

Page 31: ...F TIMER10 0x4001 5000 0x4001 53FF TIMER9 0x4001 4C00 5 0x4001 4FFF TIMER8 0x4001 4800 0x4001 4BFF Reserved 0x4001 4400 0x4001 47FF Reserved 0x4001 4000 0x4001 43FF Reserved 0x4001 3C00 0x4001 3FFF ADC2 0x4001 3800 0x4001 3BFF USART0 0x4001 3400 0x4001 37FF TIMER7 0x4001 3000 0x4001 33FF SPI0 0x4001 2C00 0x4001 2FFF TIMER0 0x4001 2800 0x4001 2BFF ADC1 0x4001 2400 0x4001 27FF ADC0 0x4001 2000 0x4001...

Page 32: ...4000 4800 0x4000 4BFF USART2 0x4000 4400 0x4000 47FF USART1 0x4000 4000 0x4000 43FF Reserved 0x4000 3C00 0x4000 3FFF SPI2 I2S2 0x4000 3800 0x4000 3BFF SPI1 I2S1 0x4000 3400 0x4000 37FF Reserved 0x4000 3000 0x4000 33FF FWDGT 0x4000 2C00 0x4000 2FFF WWDGT 0x4000 2800 0x4000 2BFF RTC 0x4000 2400 0x4000 27FF Reserved 0x4000 2000 0x4000 23FF TIMER13 0x4000 1C00 0x4000 1FFF TIMER12 0x4000 1800 0x4000 1B...

Page 33: ...Aliased to Main Flash or Boot loader 0x0002 0000 0x000F FFFF 0x0000 0000 0x0001 FFFF 1 3 1 Bit banding In order to reduce the time of read modify write operations the Cortex M4 processor provides a bit banding function to perform a single atomic bit operation The memory map includes two bit band regions These occupy the SRAM and Peripherals respectively These bit band regions map each word in an a...

Page 34: ...tion blocks for the boot loader Option bytes to configure the device Refer to Flash Memory Controller FMC Chapter for more details 1 4 Boot configuration The GD32F403xx devices provide three kinds of boot sources which can be selected by the BOOT0 and BOOT1 pins The details are shown in the following table The value on the two pins is latched on the 4th rising edge of CK_SYS after a reset It is up...

Page 35: ... beginning at 0x2000 0000 is selected as the boot source in the application initialization code you have to relocate the vector table in SRAM using the NVIC exception table and offset register The embedded boot loader is located in the System memory which is used to reprogram the Flash memory In GD32F403xx devices the boot loader can be activated through the USART0 PA9and PA10 USART1 PD5and PD6 or...

Page 36: ...Y 15 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASH_DENSITY 15 0 r Bits Fields Descriptions 31 16 SRAM_DENSITY 15 0 SRAM density The value indicates the on chip SRAM density of the device in Kbytes Example 0x0008 indicates 8 Kbytes 15 0 FLASH_DENSITY 15 0 Flash memory density The value indicates the Flash memory density of the device in Kbytes Example 0x0020 indicates 32 Kbytes 1 5 2 Unique devic...

Page 37: ...er be altered by user 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 95 80 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNIQUE_ID 79 64 r Bits Fields Descriptions 31 0 UNIQUE_ID 95 64 Unique device ID 1 6 System configuration registers Base address 0x4002 103C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CEE R...

Page 38: ...GD32F403xx UserManual 38 1 Code execution efficiency enhancement 6 0 Reserved Must be kept at reset value NOTE 1 Only bit 7 can be read modify write other bits are not permitted ...

Page 39: ...alf word bit programming page erase and mass erase operation 16B option bytes block for user application requirements Option bytes are uploaded to the option byte control registers on every system reset Flash security protectionto prevent illegal code data access Page erase program protection to prevent unexpected operation 2 3 Function description 2 3 1 Flash memory architecture For GD32F403xx wi...

Page 40: ...wo write operations are writing 0x45670123 and 0xCDEF89AB to the FMC_KEY0 register After the two write operations theLK bit in FMC_CTL0 register is reset to 0 by hardware The software can lock the FMC_CTL again by setting the LK bit in FMC_CTL0 register to 1 Any wrong operations to the FMC_KEY0 set the LK bit to 1 and lock FMC_CTL0 register and lead to a bus error The OBPG bit and OBER bit in FMC_...

Page 41: ...ntil all the operations have finished by checking the value of the BUSY bit in FMC_STATx registers 7 Read and verify the page if required using a DBUS access When the operation is executed successfully the ENDF in FMC_STATx registers is set and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTLx registers is set Note that a correct target page address must be confirmed Or the so...

Page 42: ...ank1 under security protection the address should not only be written to FMC_ADRR1 but also to FMC_ADDR0 2 3 5 Mass erase The FMC provides a complete erase function which is used to initialize the main flash block contents This erase can affect only on Bank0 by setting MER bit to 1 in the FMC_CTL0 register oronlyonBank1bysettingMERbitto 1intheFMC_CTL1register oronentireflash by setting MER bits to...

Page 43: ... registers is set and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTLx registers is set Since all flash data will be modified to a value of 0xFFFF_FFFF the mass erase operation can be implementedusingaprogramthat runs inSRAM orby using thedebuggingtool that accesses the FMC registers directly For GD32F403xx with flash more than 512KB the mass erase procedure applied to bank1 ...

Page 44: ...sing a DBUS access When the operation is executed successfully the ENDF in FMC_STATx registers is set and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTLx registers is set Note that the word half word programming operationchecks the address if it has been erased If the address has not been erased PGERR bit in the FMC_STATx registers will be set when program the address except...

Page 45: ...2 3 7 Option bytes Erase The FMC provides an erase function which is used to initialize the option bytes block in flash The following steps show the erase sequence 1 Unlock the FMC_CTL0 register if necessary 2 Check the BUSY bit in FMC_STAT0 register to confirm that no Flash memory operation is in progress BUSY equal to 0 Otherwise wait until the operation has finished 3 Unlock the option bytes op...

Page 46: ...checking the value of the BUSY bit in FMC_STAT0 register 8 Read and verify the Flash memory if required using a DBUS access When the operation is executed successfully the ENDF in FMC_STAT0 register is set and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL0 register is set Note that the word half word programming operationchecks the address if it has been erased If the addre...

Page 47: ...active 1 unprotected 0x1fff f809 WP_N 7 0 WP complement value bit 7 to 0 0x1fff f80a WP 15 8 Page Erase Program Protection bit 15 to 8 0x1fff f80b WP_N 15 8 WP complement value bit 15 to 8 0x1fff f80c WP 23 16 Page Erase Program Protection bit 23 to 16 0x1fff f80d WP_N 23 16 WP complement value bit 23 to 16 0x1fff f80e WP 31 24 Page Erase Program Protection bit 31 to 24 WP 30 24 Each bit is relate...

Page 48: ...block are accessible by all operations Under protection when setting SPC byte and its complement value to any value except 0x5AA5 the security protection is performed Note that a power reset should be followed instead of a system reset if the SPC modification is performed while the debug module is still connected to JTAG SWD device Under the security protection the main flash can only be accessed ...

Page 49: ...eset value 2 0 WSCNT 2 0 Wait state counter register These bits is set and reset by software The WSCNT valid when WSEN bit in FMC_WSEN is set 000 0 wait state added 001 1 wait state added 010 2 wait state added 011 111 reserved 2 4 2 Unlock key register 0 FMC_KEY0 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 50: ...k option bytes command in FMC_CTL0 register 2 4 4 Status register 0 FMC_STAT0 Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENDF WPERR Reserved PGERR Reserved BUSY rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 6 Reserved Must be kept at reset...

Page 51: ... 4 3 2 1 0 Reserved ENDIE Reserved ERRIE OBWEN Reserved LK START OBER OBPG Reserved MER PER PG rw rw rw rs rs rw rw rw rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 ENDIE End of operation interrupt enable bit This bit is set or cleared by software 0 no interrupt generated by hardware 1 end of operation interrupt enable 11 Reserved Must be kept at reset value 10 ERRIE...

Page 52: ... erase for bank0 command bit This bit is set or cleared by software 0 no effect 1 main flash mass erase command for bank0 1 PER Main flash page erase for bank0 command bit This bit is set or clear by software 0 no effect 1 main flash page erase command for bank0 0 PG Main flash program for bank0 command bit This bit is set or clear by software 0 no effect 1 main flash program command for bank0 Not...

Page 53: ...r Bits Fields Descriptions 31 26 Reserved Must be kept at reset value 25 10 DATA 15 0 Store DATA of option bytes block after system reset 9 2 USER 7 0 Store USER of option bytes block after system reset 1 SPC Option bytes security protection code 0 no protection 1 protection 0 OBERR Option bytes read error bit This bit is set by hardware when the option bytes and its complement byte do not match t...

Page 54: ...Y 31 0 with keys to unlock FMC_CTL1 register 2 4 10 Status register 1 FMC_STAT1 Address offset 0x4C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENDF WPERR Reserved PGERR Reserved BUSY rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 6 Reserved Product reserved ID c...

Page 55: ...27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENDIE Reserved ERRIE Reserved LK START Reserved MER PER PG rw rw rs rs rw rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 ENDIE End of operation interrupt enable bit This bit is set or cleared by software 0 no interrupt generated by hardware 1 end of operation interrupt enable 1...

Page 56: ... software 0 no effect 1 main flash program command for bank1 Note This register should be reset after the corresponding flash operation completed 2 4 12 Address register 1 FMC_ADDR1 Address offset 0x54 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR 15 0 W Bits Fields Des...

Page 57: ...also protected by the FMC_KEYx register It is necessary to writing 0x45670123 and 0xCDEF89AB to the FMC_KEYx register 0 no wait state added when fetch flash 1 wait state added when fetch flash 2 4 14 Product ID register FMC_PID Address offset 0x100 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PID 31 16 r 15 14 13 12 11 10 9...

Page 58: ... embedded LDO in the VDD VDDA domain is used to supply the 1 2V domain power A power switch is implemented for the Backup domain It can be powered from the VBAT voltage when the main VDD supply is shut down 3 2 Characteristics Three power domains VBAK VDD VDDA and 1 2V power domains Three power saving modes Sleep Deep sleep and Standby modes Internal Voltage regulator LDO supplies around 1 2V volt...

Page 59: ...l standby voltage supplied by a battery or by another source The power switch is controlled by the Power Down Reset circuit in the VDD VDDA domain If no external battery is used in the application it is recommended to connect VBAT pin externally to VDD pin with a 100nF external ceramic decoupling capacitor The Backup domain reset sources includes the Backup domain power on reset BPOR and the Backu...

Page 60: ...des two parts VDD domain and VDDA domain VDD domain includes HXTAL high speed crystal oscillator LDO voltage regulator POR PDR power on down reset FWDGT free watchdog timer all pads except PC13 PC14 PC15 etc VDDA domain includes ADC DAC AD DA converter IRC8M internal 8MHz RC oscillator IRC48M internal 48MHz RC oscillator at 48MHz frequency IRC40K internal 40KHz RC oscillator PLLs phase locking loo...

Page 61: ...ister PMU_CS indicates if VDD VDDA is higherorlowerthantheLVDthreshold This event is internally connectedtotheEXTI line16andcangenerateaninterrupt if it is enabledthrough the EXTI registers Figure 3 3 Waveform of the LVD threshold shows the relationship between the LVD threshold and the LVD output LVD interrupt signal depends on EXTI line 16 rising or falling edge configuration The following figur...

Page 62: ...SA 3 3 3 1 2V power domain 1 2V power domain supplies power for Cortex M4 logic AHB APB peripherals the APB interfaces for the Backup domain and the VDD VDDA domain etc Once the 1 2V is powered up the POR will generate a reset sequence on the 1 2V power domain If need to enter the expected power saving mode the associatedcontrol bits must be configured Then once a WFI Wait for Interrupt or WFE Wai...

Page 63: ...s to select the Sleep mode entry mechanism Sleep now if the SLEEPONEXIT bit is cleared the MCU enters Sleep mode as soon as WFI or WFE instruction is executed Sleep on exit if the SLEEPONEXIT bit is set the MCU enters Sleep mode as soon as it exits from the lowest priority ISR Deep sleep mode The Deep sleep mode is based on the SLEEPDEEP mode of the Cortex M4 In Deep sleep mode all clocks in the 1...

Page 64: ...o continue to execute the following procedure Standby mode The Standby mode is based on the SLEEPDEEP mode of the Cortex M4 too In Standby mode the whole 1 2V domain is power off the LDO is shut down and all of IRC8M HXTAL and PLL are disabled Before entering the Standby mode it is necessary to set the SLEEPDEEP bit in the Cortex M4 System Control Register and set the STBMOD bit in the PMU_CTL reg...

Page 65: ... SEVONPEND is 1 for WFE Any interrupt from EXTI lines for WFI Any event or interrupt when SEVONPEND is 1 from EXTI for WFE 1 NRST pin 2 WKUP pin 3 FWDGT reset 4 RTC Wakeup Latency None IRC8M wakeup time LDO wakeup time added if LDO is in low power mode Power on sequence Note In Standby mode all I Os are in high impedance state except NRST pin PC13 pin when configured for RTC function PC14 and PC15...

Page 66: ...able in Deep sleep mode 17 HDS High driver mode switch Set this bit by software only when HDRF flag is set and IRC8M or HXTAL used as system clock After this bit is set the system enters High driver mode This bit can be cleared by software And cleared by hardware when exit from Deep sleep mode or when the HDEN bit is clear 0 No High driver mode switch 1 High driver mode switch 16 HDEN High driver ...

Page 67: ...ble 0 Disable write access to the registers in Backup domain 1 Enable write access to the registers in Backup domain After reset any write access to the registers in Backup domain is ignored This bit has to be set to enable write access to these registers 7 5 LVDT 2 0 Low Voltage Detector Threshold 000 2 1V 001 2 3V 010 2 4V 011 2 6V 100 2 7V 101 2 9V 110 3 0V 111 3 1V 4 LVDEN Low Voltage Detector...

Page 68: ...rved WUPEN Reserved LVDF STBF WUF r rw r r r Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 18 LDRF 1 0 Low driver mode ready flag These bits are set by hardware when enter Deep sleep mode and the LDO in Low driver mode These bits are cleared by software when write 11 00 normal driver in Deep sleep mode 01 Reserved 10 Reserved 11 Low driver mode in Deep sleep mode 17 HDSRF ...

Page 69: ... Status Flag 0 Low Voltage event has not occurred VDD is higher than the specified LVD threshold 1 Low Voltage event occurred VDD is equal to or lower than the specified LVD threshold Note The LVD function is stopped in Standby mode 1 STBF Standby Flag 0 The device has not entered the Standby mode 1 The device has been in the Standby mode This bit is cleared only by a POR PDR or by setting the STB...

Page 70: ... enabled by setting the BKPWEN bit in the PMU_CTL register 4 2 Main features 84 bytes Backup registers which can keep data under power saving mode If tamper event is detected Backup registers will be reset The active level of Tamper source PC13 can be configured RTC Clock Calibration register provides RTC alarm and second output selection and sets the calibration value Tamper control and status re...

Page 71: ...tion configuration should be set before enable TAMPER pin When the tamper event is detected the corresponding TEF bit in theBKP_TPCS register will be set Tamper event can generate an interrupt if tamperinterruptis enabled Any tamperevent will reset all Backupdataregisters Note When TPAL 0 1 if the TAMPER pin is already high low before it is enabled by setting TPEN bit an extra tamper event is dete...

Page 72: ...or power reset 4 4 2 RTC signal output control register BKP_OCTL Address offset 0x2C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CALDIR CCOSEL Reserved ROSEL ASOEN COEN RCCV 6 0 rw rw rw rw rw rw Bits Fields Descriptions 15 CALDIR RTC clock calibration direction 0 Slowed down 1 Speed up This bit is reset only by a Backup...

Page 73: ...t only by a POR 6 0 RCCV 6 0 RTC clock calibration value The value indicates how many clock pulses are ignored or added every 2 20 RTC clock pulses This bit is reset only by a Backup domain reset 4 4 3 Tamper pin control register BKP_TPCTL Address offset 0x30 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TPAL TPEN...

Page 74: ... is reset by writing 1 to the TIR bit or the TPIE bit being 0 8 TEF Tamper event flag 0 No tamper event occurred 1 A tamper event occurred This bit is reset by writing 1 to the TER bit 7 3 Reserved Must be kept at reset value 2 TPIE Tamper interrupt enable 0 Disable the tamper interrupt 1 Enable the tamper interrupt This bit is reset only by a system reset and wake up from Standby mode 1 TIR Tampe...

Page 75: ...tandby mode The power reset sets all registerstotheirreset valuesexcept the backupdomain The powerreset whose active signal is low it will be de asserted when the internal LDO voltage regulator is ready to provide 1 2V power The RESET service routine vector is fixed at address 0x0000_0004 in the memory map System reset A system reset is generated by the following events A power reset POWER_RSTn A ...

Page 76: ...5 2 Clock control unit CCTL 5 2 1 Overview The clock control unit provides a range of frequencies and clock functions These include a Internal 8M RC oscillator IRC8M a Internal 48M RC oscillator IRC48M a High Speed crystal oscillator HXTAL a Low Speed Internal 40K RC oscillator IRC40K a Low Speed crystal oscillator LXTAL three Phase Lock Loop PLL a HXTAL clock monitor clock prescalers clock multip...

Page 77: ...UT0SEL 3 0 48 MHz EXT1 2 1000 1001 1010 CK_PLL1 CK_PLL2 1011 CK_PLL2 1 2 3 15 16 PREDV1 8 9 10 14 16 20 PLL1 PLL1MF PLL2MF 8 14 16 18 32 40 PLL2 CK_PLL1 CK_PLL2 1 2 3 15 16 x2 I2S1 2SEL 0 1 CK_I2S 1 EXT1 to CK_OUT PREDV0SEL 48 MHz IRC48M CTC CK48MSEL CK_CTC 1 0 1 0 CK_IRC48M PLLPRESEL ADC Prescaler 5 6 10 20 0 1 ADCPSC 3 CK_IRC48M The frequency of AHB APB2 and the APB1 domains can be configured by...

Page 78: ...stics 4 to 32 MHz High Speed crystal oscillator HXTAL Internal 8 MHz RC oscillator IRC8M Internal 48 MHz RC oscillator IRC48M 32 768 Hz Low Speed crystal oscillator LXTAL Internal 40KHz RC oscillator IRC40K PLL clock source can be HXTAL IRC8M orIRC48M HXTAL clock monitor 5 2 3 Function overview High speed crystal oscillator HXTAL The high speed external crystal oscillator HXTAL which has a frequen...

Page 79: ... required The IRC8M RC oscillator can be switched on or off using the IRC8MEN bit in the control register RCU_CTL The IRC8MSTB flag in the control register RCU_CTL is used to indicate if the internal 8M RC oscillatoris stable Thestart up timeof theIRC8M oscillatoris shorterthantheHXTALcrystal oscillator An interrupt can be generated if the related interrupt enable bit IRC8MSTBIE in the clock inter...

Page 80: ... the RCU_INT register is set as the PLL1 becomes stable The PLL2 can be switched on or off by using the PLL2EN bit in the RCU_CTL register The PLL2STB flag in the RCU_CTL register will indicate if the PLL2 clock is stable An interrupt can be generated if the related interrupt enable bit PLL2STBIE in the RCU_INT register is set as the PLL2 becomes stable The three PLLs are closed by hardware when e...

Page 81: ...rol register RCU_CTL This function should be enabled after the HXTAL start up delay and disabled when the HXTAL is stopped Once the HXTAL failure is detected the HXTAL will be automatically disabled The HXTAL clock stuck interrupt flag CKMIF in the clock interrupt register RCU_INT will be set and the HXTAL failure event will be generated This failure interrupt is connected to the non maskable Inte...

Page 82: ...011 CK_PLL2 Voltage control The 1 2V domain voltagein Deep sleep mode can be controlled by DSLPVS 2 0 bit in the Deep sleep mode voltage register RCU_DSV Table 5 2 1 2V domain voltage selected in deep sleep mode DSLPVS 2 0 Deep sleep mode voltage V 000 1 0 001 0 9 010 0 8 011 0 7 ...

Page 83: ...st be kept at reset value 29 PLL2STB PLL2 clock stabilization flag Set by hardware to indicate if the PLL2 output clock is stable and ready for use 0 PLL2 is not stable 1 PLL2 is stable 28 PLL2EN PLL2 enable Set and reset by software Reset by hardware when entering Deep sleep or Standby mode 0 PLL2 is switched off 1 PLL2 is switched on 27 PLL1STB PLL1 clock stabilization flag Set by hardware to in...

Page 84: ... speed crystal oscillator HXTAL clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0 0 Disable the HXTAL Bypass mode 1 Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the input clock 17 HXTALSTB High speed crystal oscillator HXTAL clock stabilization flag Set by hardware to indicate if the HXTAL oscillator is stable and ready for use 0 HXTAL os...

Page 85: ...t 0x04 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 USBFSP SC 2 PLLMF 5 4 ADCPSC 2 CKOUT0SEL 3 0 USBFSPSC 1 0 PLLMF 3 0 PREDV0 _LSB PLLSEL rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCPSC 1 0 APB2PSC 2 0 APB1PSC 2 0 AHBPSC 3 0 SCSS 1 0 SCS 1 0 rw rw rw rw r rw Bits Fields Des...

Page 86: ...lication factor Caution The PLL output frequency must not exceed 168 MHz 000000 PLL source clock x 2 000001 PLL source clock x 3 000010 PLL source clock x 4 000011 PLL source clock x 5 000100 PLL source clock x 6 000101 PLL source clock x 7 000110 PLL source clock x 8 000111 PLL source clock x 9 001000 PLL source clock x 10 001001 PLL source clock x 11 001010 PLL source clock x 12 001011 PLL sourc...

Page 87: ...on Set and reset by software to control the PLL clock source 0 IRC8M 2 clock selected as source clock of PLL 1 HXTAL or IRC48M PLLPRESEL of RCU_CFG1 register selected as source clock of PLL 15 14 ADCPSC 1 0 ADC clock prescaler selection These bits bit 28 of RCU_CFG0 and bit 29 of RCU_CFG1 are written by software to define the ADC prescaler factor Set and cleared by software 0000 CK_APB2 2 selected...

Page 88: ...1 0 System clock switch status Set and reset by hardware to indicate the clock source of system clock 00 select CK_IRC8M as the CK_SYS source 01 select CK_HXTAL as the CK_SYS source 10 select CK_PLL as the CK_SYS source 11 reserved 1 0 SCS 1 0 System clock switch Set by software to select the CK_SYS source Because the change of CK_SYS has inherent latency software should read SCSS to confirm wheth...

Page 89: ...et CKMIF flag 22 PLL2STBIC PLL2 stabilization Interrupt Clear Write 1 by software to reset the PLL2STBIF flag 0 Not reset PLL2STBIF flag 1 Reset PLL2STBIF flag 21 PLL1STBIC PLL1 stabilization Interrupt Clear Write 1 by software to reset the PLL1STBIF flag 0 Not reset PLL1STBIF flag 1 Reset PLL1STBIF flag 20 PLLSTBIC PLL stabilization Interrupt Clear Write 1 by software to reset the PLLSTBIF flag 0...

Page 90: ...rupt 11 HXTALSTBIE HXTAL stabilization interrupt enable Set and reset by software to enable disable the HXTAL stabilization interrupt 0 Disable the HXTAL stabilization interrupt 1 Enable the HXTAL stabilization interrupt 10 IRC8MSTBIE IRC8M stabilization interrupt enable Set and reset by software to enable disable the IRC8M stabilization interrupt 0 Disable the IRC8M stabilization interrupt 1 Enab...

Page 91: ... and the HXTALSTBIE bit is set Reset when setting the HXTALSTBIC bit by software 0 No HXTAL stabilization interrupt generated 1 HXTAL stabilization interrupt generated 2 IRC8MSTBIF IRC8M stabilization interrupt flag Set by hardware when the internal 8 MHz RC oscillatorclock is stable and the IRC8MSTBIE bit is set Reset when setting the IRC8MSTBIC bit by software 0 No IRC8M stabilization interrupt ...

Page 92: ...w rw rw rw rw rw rw rw Bits Fields Descriptions 31 22 Reserved Must be kept at reset value 21 TIMER10RST Timer 10 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER10 20 TIMER9RST Timer 9 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER9 19 TIMER8RST Timer 8 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER8 18 16 Reserved Must b...

Page 93: ...reset 1 Reset the ADC0 8 PGRST GPIO port G reset This bit is set and reset by software 0 No reset 1 Reset the GPIO port G 7 PFRST GPIO portF reset This bit is set and reset by software 0 No reset 1 Reset the GPIO port F 6 PERST GPIO port E reset This bit is set and reset by software 0 No reset 1 Reset the GPIO port E 5 PDRST GPIO port D reset This bit is set and reset by software 0 No reset 1 Rese...

Page 94: ... 17 16 Reserved DACRST PMURST BKPIRST CAN1RS T CAN0RS T Reserved I2C1RST I2C0RST UART4R ST UART3R ST USART2 RST USART1 RST Reserved rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI2RST SPI1RST Reserved WWDGT RST Reserved TIMER13 RST TIMER12 RST TIMER11 RST TIMER6R ST TIMER5R ST Reserved TIMER3R ST TIMER2R ST Reserved rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions ...

Page 95: ...C0RST I2C0 reset This bit is set and reset by software 0 No reset 1 Reset the I2C0 20 UART4RST UART4 reset This bit is set and reset by software 0 No reset 1 Reset the UART4 19 UART3RST UART3 reset This bit is set and reset by software 0 No reset 1 Reset the UART3 18 USART2RST USART2 reset This bit is set and reset by software 0 No reset 1 Reset the USART2 17 USART1RST USART1 reset This bit is set...

Page 96: ...set the TIMER13 7 TIMER12RST TIMER12 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER12 6 TIMER11RST TIMER11 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER11 5 TIMER6RST TIMER6 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER6 4 TIMER5RST TIMER5 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER5 3 Rese...

Page 97: ...N DMA0EN rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 USBFSEN USBFS clock enable This bit is set and reset by software 0 Disabled USBFS clock 1 Enabled USBFS clock 11 Reserved Must be kept at reset value 10 SDIOEN SDIO clock enable This bit is set and reset by software 0 Disabled SDIO clock 1 Enabled SDIO clock 9 Reserved Must be kept at reset v...

Page 98: ...set and reset by software 0 Disabled DMA1 clock 1 Enabled DMA1 clock 0 DMA0EN DMA0 clock enable This bit is set and reset by software 0 Disabled DMA0 clock 1 Enabled DMA0 clock 5 3 7 APB2 enable register RCU_APB2EN Address offset 0x18 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIMER10...

Page 99: ...lock enable This bit is set and reset by software 0 Disabled USART0 clock 1 Enabled USART0 clock 13 TIMER7EN TIMER7 clock enable This bit is set and reset by software 0 Disabled TIMER7 clock 1 Enabled TIMER7 clock 12 SPI0EN SPI0 clock enable This bit is set and reset by software 0 Disabled SPI0 clock 1 Enabled SPI0 clock 11 TIMER0EN TIMER0 clock enable This bit is set and reset by software 0 Disab...

Page 100: ...4 PCEN GPIO port C clock enable This bit is set and reset by software 0 Disabled GPIO port C clock 1 Enabled GPIO port C clock 3 PBEN GPIO port B clock enable This bit is set and reset by software 0 Disabled GPIO port B clock 1 Enabled GPIO port B clock 2 PAEN GPIO port A clock enable This bit is set and reset by software 0 Disabled GPIO port A clock 1 Enabled GPIO port A clock 1 Reserved Must be ...

Page 101: ...e 0 Disabled DAC clock 1 Enabled DAC clock 28 PMUEN PMU clock enable This bit is set and reset by software 0 Disabled PMU clock 1 Enabled PMU clock 27 BKPIEN Backup interface clock enable This bit is set and reset by software 0 Disabled Backup interface clock 1 Enabled Backup interface clock 26 CAN1EN CAN1 clock enable This bit is set and reset by software 0 Disabled CAN1 clock 1 Enabled CAN1 cloc...

Page 102: ...1 clock 1 Enabled USART1 clock 16 Reserved Must be kept at reset value 15 SPI2EN SPI2 clock enable This bit is set and reset by software 0 Disabled SPI2 clock 1 Enabled SPI2 clock 14 SPI1EN SPI1 clock enable This bit is set and reset by software 0 Disabled SPI1 clock 1 Enabled SPI1 clock 13 12 Reserved Must be kept at reset value 11 WWDGTEN WWDGT clock enable This bit is set and reset by software ...

Page 103: ...3 clock 1 TIMER2EN TIMER2 clock enable This bit is set and reset by software 0 Disabled TIMER2 clock 1 Enabled TIMER2 clock 0 Reserved Must be kept at reset value 5 3 9 Backup domain control register RCU_BDCTL Address offset 0x20 Reset value 0x0000 0018 reset by backup domain reset This register can be accessed by byte 8 bit half word 16 bit and word 32 bit Note The LXTALEN LXTALBPS RTCSRC and RTC...

Page 104: ...XTAL selected as RTC source clock 10 CK_IRC40K selected as RTC source clock 11 CK_HXTAL 128 selected as RTC source clock 7 5 Reserved Must be kept at reset value 4 3 LXTALDRI 1 0 LXTAL drive capability Set and reset by software Backup domain reset resets this value 00 Lower driving capability 01 Medium low driving capability 10 Medium high driving capability 11 Higher driving capability reset valu...

Page 105: ...dby reset generated Reset by writing 1 to the RSTFC bit 0 No low power management reset generated 1 Low power management reset generated 30 WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated Reset by writing 1 to the RSTFC bit 0 No window watchdog reset generated 1 Window watchdog reset generated 29 FWDGTRSTF Free watchdog timer reset flag Set b...

Page 106: ... 23 2 Reserved Must be kept at reset value 1 IRC40KSTB IRC40K stabilization flag Set by hardware to indicate if the IRC40K output clock is stable and ready for use 0 IRC40K is not stable 1 IRC40K is stable 0 IRC40KEN IRC40K enable Set and reset by software 0 Disable IRC40K 1 Enable IRC40K 5 3 11 AHB reset register RCU_AHBRST Address offset 0x28 Reset value 0x0000 0000 This register can be accessed...

Page 107: ...CU_CFG1 30 PLLPRESEL PLL clock source preselection 0 HXTAL selected as PLL source clock 1 CK_IRC48M selected as PLL source clock 29 ADCPSC 3 Bit 4 of ADCPSC see bits 15 14 of RCU_CFG0 and bit 28 of RCU_CFG0 28 19 Reserved Must be kept at reset value 18 I2S2SEL I2S2 clock source selection Set and reset by software to control the I2S2 clock source 0 System clock selected as I2S2 source clock 1 CK_PL...

Page 108: ...clock x 19 10010 PLL2 source clock x 20 10011 PLL2 source clock x 21 10100 PLL2 source clock x 22 10101 PLL2 source clock x 23 10110 PLL2 source clock x 24 10111 PLL2 source clock x 25 11000 PLL2 source clock x 26 11001 PLL2 source clock x 27 11010 PLL2 source clock x 28 11011 PLL2 source clock x 29 11100 PLL2 source clock x 30 11101 PLL2 source clock x 31 11110 PLL2 source clock x 32 11111 PLL2 s...

Page 109: ...10 PREDV2 input source clock divided by 15 1111 PREDV2 input source clock divided by 16 3 0 PREDV0 3 0 PREDV0 division factor This bit is set and reset by software These bits can be written when PLL is disable Note The bit 0 of PREDV0 is same as bit 17 of RCU_CFG0 so modifying Bit 17 of RCU_CFG0 also modifies bit 0 of RCU_CFG1 0000 PREDV0 input source clock not divided 0001 PREDV0 input source clo...

Page 110: ...tage is default value 0 1 V in Deep sleep mode customers are not recommended to use it 010 The core voltage is default value 0 2 V in Deep sleep mode customers are not recommended to use it 011 The core voltage is default value 0 3 V in Deep sleep mode customers are not recommended to use it 1xx Reserved 5 3 14 Additional clock control register RCU_ADDCTL Address offset 0xC0 Reset value 0x8000 000...

Page 111: ...generate CK48M clock which select IRC48M clock or PLL48M clock 0 Don t select IRC48M clock use CK_PLL clock divided by USBFSPSC 1 Select IRC48M clock 5 3 15 Additional clock interrupt register RCU_ADDINT Address offset 0xCC Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved IRC48MS TBIC Reser...

Page 112: ...zation interrupt generated 5 0 Reserved Must be kept at reset value 5 3 16 APB1 additional reset register RCU_ADDAPB1RST Address offset 0xE0 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CTC RST Reserved rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Fields Descriptions 31 28 Res...

Page 113: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Fields Descriptions 31 28 Reserved Must be kept at reset value 27 CTCEN CTC clock enable This bit is set and reset by software 0 Disabled CTC clock 1 Enabled CTC clock 26 0 Reserved Must be kept at reset value ...

Page 114: ...rate referencesignal source It canautomatically adjust thetrimvaluetoprovideapreciseIRC48M clock 6 2 Characteristics Two external reference signal source GPIO LXTAL clock Provide software reference sync pulse Automatically trimmed by hardware without any software action 16 bits trim counter with reference signal source capture and reload 8 bits clock trim base value to frequency evaluation and aut...

Page 115: ...y setting REFPOL bit in CTC_CTL1 register and can be divided to a suitable frequency with a configurable prescaler by setting REFPSC bits in CTC_CTL1 register Thirdly if asoftwarereferencepulseneeded write1to SWREFPULbitinCTC_CTL0 register The software reference pulse generated in last step is logical OR with the external reference pulse 6 3 2 CTC trim counter The CTC trim counter is clocked by CK...

Page 116: ...s the current clock is slower than correct clock the frequency of 48M It needs to improve TRIMVALUE in CTC_CTL0 register If a REF sync pulse occurs on up counting it means the current clock is faster than correct clock the frequency of 48M It needs to reduce TRIMVALUE in CTC_CTL0 register The CKOKIF CKWARNIF CKERR and REFMISS in CTC_STAT register shows the frequency evaluation scope If the AUTOTRI...

Page 117: ...VALUE in CTC_CTL0 register is not changed Counter 128 x CKLIM when up counting The REFMISS in CTC_STAT register set and an interrupt generated if ERRIE bit in CTC_CTL0 register is 1 The TRIMVALUE in CTC_CTL0 register is not changed If adjusting the TRIMVALUE in CTC_CTL0 register over the value of 63 the overflow will be occurred whileadjustingtheTRIMVALUE underthevalueof 0 theunderflowwill beoccur...

Page 118: ...GD32F403xx UserManual 118 CKLIM 𝐹𝑐𝑙𝑜𝑐𝑘 𝐹𝑅𝐸𝐹 0 12 2 6 2 The typical step size is 0 12 Where the 𝐹𝑐𝑙𝑜𝑐𝑘 is the frequency of correct clock IRC48M the 𝐹𝑅𝐸𝐹 is the frequency of reference sync pulse ...

Page 119: ...is mode used to hardware trim The middle value is 32 When increase 1 the IRC48M clock frequency add around 57KHz When decrease 1 the IRC48M clock frequency sub around 57KHz 7 SWREFPUL Software reference source sync pulse This bit is set by software and generates a reference sync pulse to CTC counter This bit is cleared by hardware automatically and read as 0 0 No effect 1 generates a software refe...

Page 120: ...4 2 Control register 1 CTC_CTL1 Address offset 0x04 Reset value 0x2022 BB7F This register has to be accessed by word 32 bit This register cannot be modified when CNTEN is 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REF POL Reserved REFSEL 1 0 Reserved REFPSC 2 0 CKLIM 7 0 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RLVALUE 15 0 rw Bits Fields Descriptions 31 REFPOL Reference signal sou...

Page 121: ...fine the clock trim base limit value These bits used to frequency evaluation and automatically trim process Please refer to the Frequency evaluation and automatically trim process for detail 15 0 RLVALUE 15 0 CTC counter reload value These bits are set and cleared by software to define the CTC counter reload value These bits reload to CTC trim counter when a reference sync pulse received to start ...

Page 122: ...he clock is too fast to be trimmed to correct frequency or other error occur When the ERRIE in CTC_CTL0 register is set an interrupt occurs This bit is cleared by writing 1 to ERRIC bit in CTC_INTC register 0 No Reference sync pulse miss occur 1 Reference sync pulse miss occur 8 CKERR Clock trim error bit This bit is set by hardware when the clock trim error occurs This is occur when the CTC trim ...

Page 123: ...ccurs This bit is cleared by writing 1 to CKWARNIC bit in CTC_INTC register 0 No Clock trim warning occur 1 Clock trim warning occur 0 CKOKIF Clock trim OK interrupt flag This bit is set by hardware when the clock trim is OK If the CTC trim counter smaller to 3 x CKLIM when a reference sync pulse detected this bit will be set This means the clock is OK to use The TRIMVALUE need not to adjust or ad...

Page 124: ...ead as 0 Write 1 to clear ERRIF TRIMERR REFMISS and CKERR bits in CTC_STAT register Write 0 is no effect 1 CKWARNIC CKWARNIF interrupt clear bit This bit is written by software and read as 0 Write 1 to clear CKWARNIF bit in CTC_STAT register Write 0 is no effect 0 CKOKIC CKOKIF interrupt clear bit This bit is written by software and read as 0 Write 1 to clear CKOKIF bit in CTC_STAT register Write ...

Page 125: ...peripheral interrupts 4 bits interrupt priority configuration 16 priority levels Efficient interrupt processing Support exception pre emption and tail chaining Wake up system from power saving mode Up to 19 independent edge detectors in EXTI Three trigger types rising falling and bothedges Software interrupt or event trigger Trigger sources configurable 7 3 Interrupts function overview The Arm Cor...

Page 126: ...le 0x0000_003C System tick timer The SysTick calibrationvalue is 21000 and SysTick clock frequency is fixed to HCLK 0 125 So this will give a 1ms SysTick interrupt if HCLK is configured to 168MHz Table 7 2 Interrupt vector table Interrupt Number Vector Number Interrupt Description Vector Address IRQ 0 16 WWDGT interrupt 0x0000_0040 IRQ 1 17 LVD from EXTI interrupt 0x0000_0044 IRQ 2 18 Tamper inter...

Page 127: ... TIMER0 channel capture compare interrupt 0x0000_00AC IRQ 28 44 reserved 0x0000_00B0 IRQ 29 45 TIMER2 global interrupt 0x0000_00B4 IRQ 30 46 TIMER3 global interrupt 0x0000_00B8 IRQ 31 47 I2C0 event interrupt 0x0000_00BC IRQ 32 48 I2C0 error interrupt 0x0000_00C0 IRQ 33 49 I2C1 event interrupt 0x0000_00C4 IRQ 34 50 I2C1 error interrupt 0x0000_00C8 IRQ 35 51 SPI0 global interrupt 0x0000_00CC IRQ 36 ...

Page 128: ...errupt 0x0000_0114 IRQ54 70 TIMER5 global interrupt 0x0000_0118 IRQ55 71 TIMER6 global interrupt 0x0000_011C IRQ56 72 DMA1 channel0 global interrupt 0x0000_0120 IRQ57 73 DMA1 channel1 global interrupt 0x0000_0124 IRQ58 74 DMA1 channel2 global interrupt 0x0000_0128 IRQ59 75 DMA1 channel3 global interrupt 0x0000_012C IRQ60 76 DMA1 channel4 global interrupt 0x0000_0130 IRQ61 77 reserved 0x0000_0134 I...

Page 129: ...rce includes 16 external lines from GPIO pins and 3 lines from internal modules including LVD RTC Alarm USB Wakeup All GPIO pins can be selected as an EXTI trigger source by configuringAFIO_EXTISSx registers in GPIO module please refer to GPIO and AFIO section for detail EXTI can provide not only interrupts but also event signals to the processor The Cortex M4 processor fully implements the Wait F...

Page 130: ...4 PG4 5 PA5 PB5 PC5 PD5 PE5 PF5 PG5 6 PA6 PB6 PC6 PD6 PE6 PF6 PG6 7 PA7 PB7 PC7 PD7 PE7 PF7 PG7 8 PA8 PB8 PC8 PD8 PE8 PF8 PG8 9 PA9 PB9 PC9 PD9 PE9 PF9 PG9 10 PA10 PB10 PC10 PD10 PE10 PF10 PG10 11 PA11 PB11 PC11 PD11 PE11 PF11 PG11 12 PA12 PB12 PC12 PD12 PE12 PF12 PG12 13 PA13 PB13 PC13 PD13 PE13 PF13 PG13 14 PA14 PB14 PC14 PD14 PE14 PF14 PG14 15 PA15 PB15 PC15 PD15 PE15 PF15 PG15 16 LVD 17 RTC Al...

Page 131: ...escriptions 31 19 Reserved Must be kept at reset value 18 0 INTENx Interrupt enablebit 0 Interrupt from Linex is disabled 1 Interrupt from Linex is enabled 7 6 2 Event enable register EXTI_EVEN Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EVEN18 EVEN17 EVEN16 rw rw rw 15 14 13 12 11 10 9 8 7 6 5...

Page 132: ...id 1 Rising edge of Linex is valid as an interrupt event request 7 6 4 Falling edge trigger enable register EXTI_FTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FTEN18 FTEN17 FTEN16 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTEN15 FTEN14 FTEN13 FTEN12 FTEN11 FTEN10 FTEN9 FTEN8 FTEN7 FTEN6...

Page 133: ... software interrupt event request 1 Activate the EXTIx software interrupt event request 7 6 6 Pending register EXTI_PD Address offset 0x14 Reset value undefined This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PD18 PD17 PD16 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 P...

Page 134: ...h of the GPIO pins can be configured by software as output push pull or open drain input peripheral alternate function or analog mode Each GPIO pin can be configured as pull up pull down or floating All GPIOs are high current capable except for analog mode 8 2 Characteristics Input output direction control Schmitt trigger input function enable control Each pin weak pull up pull down function Outpu...

Page 135: ...to IO compensation control register AFIO_CPSCTL Figure 8 1 Basic structure of a standard I O port bit shows the basic structure of an I O port bit Figure 8 1 Basic structure of a standard I O port bit Vss Output Control Vdd Output Control Register Input Status Register Write Read Write Alternate Function Output Read Alternate Function Input Analog Input Output Input driver Output driver I O pin Sc...

Page 136: ...asingleatomicAPB2writeaccessby programming 1 to the bit operate register GPIOx_BOP or for clearing only GPIOx_BC The other bits will not be affected 8 3 2 External interrupt event lines All ports have external interrupt capability To use external interrupt lines the port must be configured in input mode 8 3 3 Alternate functions AF When the port is configured as AFIO set CTLy bits to 0b10 or 0b11 ...

Page 137: ...hen setting 1 in the output control register Push Pull Mode the pad outputs low level when setting 0 in the output control register while the pad output high level when setting 1 in the output control register A read access to the port output control register gets the last writtenvalue A read access to the port input status register gets theI O state Figure 8 3 Output configuration shows the outpu...

Page 138: ...evicepackages the GPIO supports some alternate functions mapped to some other pins by software When be configured as alternate function The output buffer is enabled in Open Drain or Push Pull configuration The output buffer is driven by the peripheral The schmitt trigger input is enabled The weak pull up and pull downresistors could be chosen when input The I O pin data is stored into the port inp...

Page 139: ...apowermodule 8 3 9 GPIO I O compensation cell If the I O port output speed need more than 50MHz it is recommended to use the compensation cell for slew rate control toreduce the I O noise effects on the power supply Compensation cell is disabled after reset it needs to be enabled by the user After enabling the compensation cell the complete flag CPS_RDY is set to indicate that the compensation cel...

Page 140: ...ED0 PE4 TRACED1 PE5 TRACED2 PE6 TRACED3 To reduce the number of GPIOs used for debug the user can configure SWJ_CFG 2 0 bits in theAFIO_PCF0 to different value Refer to table below Table 8 3 Debug port mapping and Pin availability SWJ_CFG 2 0 JTAG DP and SW DP Pin availability PA13 PA14 PA15 PB3 PB4 000 JTAG DP Enabled and SW DP Enabled Reset state X X X X X 001 JTAG DP Enabled and SW DP Enabled b...

Page 141: ...rigger rountine conversion is connected to EXTI11 ADC1_ETRGRER_REMA P 1 ADC1 external signal trigger rountine conversion is connected to TIMER7_TRGO 1 Remap available only for High density and Extra density devices 8 4 5 TIMER AF remapping Table 8 5 TIMERx alternate function remapping Alternate function TIMERx_REMAP 1 0 x 0 1 2 TIMERx_REMAP x 8 9 10 12 13 0 00 no remap 1 01 partial remap 10 partia...

Page 142: ...TIMER12_CH0 PA6 PF8 TIMER13_CH0 PA7 PF9 1 TIMER0 remap available only for 100 pin and 144 pin packages 2 TIMER1_CH0 and TIMER1_ETI share the same pin but cannot be used at the same time 3 TIMER2 remap available only for 64 pin 100 pin and 144 pin packages 4 TIMER3 remap available only for 100 pin and 144 pin packages 5 TIMER8 9 10 12 13 refer to the AF remap and debug I O configuration register 1 ...

Page 143: ...ART1_TX PD6 USART1_RX PD7 USART1_CK USART2_REMAP 1 0 00 no remap PB10 USART2_TX PB11 USART2_RX PB12 USART2_CK PB13 USART2_CTS PB14 USART2_RTS USART2_REMAP 1 0 01 partial remap 2 PC10 USART2_TX PC11 USART2_RX PC12 USART2_CK PB13 USART2_CTS PB14 USART2_RTS USART2_REMAP 1 0 11 full remap 3 PD8 USART2_TX PD9 USART2_RX PD10 USART2_CK PD11 USART2_CTS PD12 USART2_RTS 1 Remap available only 100 pin and 14...

Page 144: ...CK PB4 SPI0_MISO PB5 SPI0_MOSI PB6 SPI0_IO2 PB7 SPI0_IO3 SPI2_REMAP 0 PA15 SPI2_NSS I2S2_WS PB3 SPI2_SCK I2S2_CK PB4 SPI2_MISO PB5 SPI2_MOSI I2S2_SD SPI2_REMAP 1 PA4 SPI2_NSS I2S2_WS PC10 SPI2_SCK I2S2_CK PC11 SPI2_MISO PC12 SPI2_MOSI I2S2_SD 8 4 9 CAN AF remapping The CAN0 signals can be mapped on Port A Port B or Port D as shown in table below For port D remapping is not possible in devices deli...

Page 145: ...PD9 RXD0 PD10 RXD1 PD11 RXD2 PD12 RXD3 8 4 11 CTC AF remapping Refer toAFIO port configurationregister 1 AFIO_ PCF1 Table 8 12 CTC alternate function remapping Register CTC_SYNC CTC_REMAP 1 0 00 PA8 CTC_REMAP 1 0 01 PD15 CTC_REMAP 1 0 10 or 11 PF0 8 4 12 CLK pins AF remapping The LXTAL oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose I O PC14 and PC15 individually when the LXT...

Page 146: ...Table 8 13 OSC32 pins configuration Alternate function LXTAL ON LXTAL OFF PC14 OSC32_IN PC14 PC15 OSC32_OUT PC15 TheHXTALoscillatorpins OSC_IN OSC_OUTcanbeusedas general purposeI OPD0 PD1 Table 8 14 OSC pins configuration Alternate function HXTAL ON HXTAL OFF PD0 OSC_IN PD0 PD1 OSC_OUT PD1 ...

Page 147: ...TL4 1 0 MD4 1 0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTL3 1 0 MD3 1 0 CTL2 1 0 MD2 1 0 CTL1 1 0 MD1 1 0 CTL0 1 0 MD0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 CTL7 1 0 Pin 7 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 29 28 MD7 1 0 Pin 7 mode bits These bits are set and cleared by software refer to MD0 1 0 de...

Page 148: ...iption 11 10 CTL2 1 0 Pin 2 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 9 8 MD2 1 0 Pin 2 mode bits These bits are set and cleared by software refer to MD0 1 0 description 7 6 CTL1 1 0 Pin 1 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 5 4 MD1 1 0 Pin 1 mode bits These bits are set and cleared by softwar...

Page 149: ...CTL9 1 0 MD9 1 0 CTL8 1 0 MD8 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 CTL15 1 0 Pin 15 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 29 28 MD15 1 0 Pin 15 mode bits These bits are set and cleared by software refer to MD0 1 0 description 27 26 CTL14 1 0 Pin 14 configuration bits These bits are set and cleared by software refer to CTL0...

Page 150: ...ription 9 8 MD10 1 0 Pin 10 mode bits These bits are set and cleared by software refer to MD0 1 0 description 7 6 CTL9 1 0 Pin 9 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 5 4 MD9 1 0 Pin 9 mode bits These bits are set and cleared by software refer to MD0 1 0 description 3 2 CTL8 1 0 Pin 8 configuration bits These bits are set and cleared by softwar...

Page 151: ...7 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OCTL15 OCTL14 OCTL13 OCTL12 OCTL11 OCTL10 OCTL9 OCTL8 OCTL7 OCTL6 OCTL5 OCTL4 OCTL3 OCTL2 OCTL1 OCTL0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 OCTLy Pin output control y 0 15 These bits are set and cleared by software 0 Pin output low 1 Pin output high 8 5 5 Port bit ...

Page 152: ...s to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 w w w w w w w w w w w w w w w w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CRy Pin Clear bit y y 0 15 These bits are set and cleared by software 0 No action on the correspon...

Page 153: ...ked 1 The corresponding bit port configuration is locked when LKK bit is 1 8 5 8 Port bit speed register GPIOx_ SPD x A G Address offset 0x3C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPD15 SPD14 SPD13 SPD12 SPD11 SPD10 SPD9 SPD8 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 rw rw...

Page 154: ...s connected to the I O selected by the PORT 2 0 and PIN 3 0 bits 6 4 PORT 2 0 Event output port selection Set and cleared by software Select the port to output the Cortex EVENTOUT signal 000 Select PORT A 001 Select PORT B 010 Select PORT C 011 Select PORT D 100 Select PORT E 3 0 PIN 3 0 Event output pin selection Set and cleared by software Select the pin to output the Cortex EVENTOUT signal 0000...

Page 155: ...onfigure the SWJ and trace alternate function I Os The SWJ Serial Wire JTAG supports JTAG or SWD access to the Cortex debug port The default state after reset is SWJ ON without trace This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS JTCK pin 000 Full SWJ JTAG DP SW DP reset state 001 Full SWJ JTAG DP SW DP but without NJTRST 010 JTAG DP Disabled and SW DP Enabled...

Page 156: ...CH3 PB9 1 Full remap TIMER3_CH0 PD12 TIMER3_CH1 PD13 TIMER3_CH2 PD14 TIMER3_CH3 PD15 11 10 TIMER2_ REMAP 1 0 TIMER2 remapping These bits are set and cleared by software 00 No remap TIMER2_CH0 PA6 TIMER2_CH1 PA7 TIMER2_CH2 PB0 TIMER2_CH3 PB1 01 Not used 10 Partial remap TIMER2_CH0 PB4 TIMER2_CH1 PB5 TIMER2_CH2 PB0 TIMER2_CH3 PB1 11 Full remap TIMER2_CH0 PC6 TIMER2_CH1 PC7 TIMER2_CH2 PC8 TIMER2_CH3 ...

Page 157: ...PA3 USART1_CK PA4 1 Remap USART1_CTS PD3 USART1_RTS PD4 USART1_TX PD5 USART1_RX PD6 USART1_CK PD7 2 USART0_REMAP USART0 remapping This bit is set and cleared by software 0 No remap USART0_TX PA9 USART0_RX PA10 1 Remap USART0_TX PB6 USART0_RX PB7 1 I2C0_REMAP I2C0 remapping This bit is set and cleared by software 0 No remap I2C0_SCL PB6 I2C0_SDA PB7 1 Remap I2C0_SCL PB8 I2C0_SDA PB9 0 SPI0_REMAP SP...

Page 158: ...pin 0110 PG3 pin Other configurationsare reserved 11 8 EXTI2_SS 3 0 EXTI 2 sources selection 0000 PA2 pin 0001 PB2 pin 0010 PC2 pin 0011 PD2 pin 0100 PE2 pin 0101 PF2 pin 0110 PG2 pin Other configurationsare reserved 7 4 EXTI1_SS 3 0 EXTI 1 sources selection 0000 PA1 pin 0001 PB1 pin 0010 PC1 pin 0011 PD1 pin 0100 PE1 pin 0101 PF1 pin 0110 PG1 pin Other configurationsare reserved 3 0 EXTI0_SS 3 0 ...

Page 159: ...I4_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI7_SS 3 0 EXTI 7 sources selection 0000 PA7 pin 0001 PB7 pin 0010 PC7 pin 0011 PD7 pin 0100 PE7 pin 0101 PF7 pin 0110 PG7 pin Other configurationsare reserved 11 8 EXTI6_SS 3 0 EXTI 6 sources selection 0000 PA6 pin 0001 PB6 pin 0010 PC6 pin 0011 PD6 pin 0100 PE6 pin 0101 PF6 pin 0110 PG6 pin Other co...

Page 160: ...as to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11_SS 3 0 EXTI10_SS 3 0 EXTI9_SS 3 0 EXTI8_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI11_SS 3 0 EXTI 11 sources selection 0000 PA11 pin 0001 PB11 pin 0010 PC11 pin 0011 PD11 pin 0100 PE11 pin 0101 PF11 pin 0110 PG1...

Page 161: ...8 pin 0100 PE8 pin 0101 PF8 pin 0110 PG8 pin Other configurationsare reserved 8 5 14 EXTI sources selection register 3 AFIO_EXTISS3 Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI15_SS 3 0 EXTI14_SS 3 0 EXTI13_SS 3 0 EXTI12_SS 3 0 rw rw rw rw Bits Fields D...

Page 162: ...rces selection 0000 PA13 pin 0001 PB13 pin 0010 PC13 pin 0011 PD13 pin 0100 PE13 pin 0101 PF13 pin 0110 PG13 pin Other configurationsare reserved 3 0 EXTI12_SS 3 0 EXTI 12 sources selection 0000 PA12 pin 0001 PB12 pin 0010 PC12 pin 0011 PD12 pin 0100 PE12 pin 0101 PF12 pin 0110 PG12 pin Other configurationsare reserved 8 5 15 AFIO port configuration register 1 AFIO_PCF1 Address offset 0x1C Reset v...

Page 163: ...ted to the output default 1 The NADV signal is not connected The I O pin can be used by another peripheral 9 TIMER13_REMAP TIMER13 remapping This bit is set and cleared by software it controls the mapping of the TIMER13_CH0 alternate function onto the GPIO ports 0 No remap PA7 1 Remap PF9 8 TIMER12_REMAP TIMER12 remapping This bit is set and cleared by software it controls the mapping of the TIMER...

Page 164: ...0 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CPS_RDY Reserved CPS_EN r rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 CPS_RDY I O compensation cell is ready or not This bit is read only 0 I O compensation cell is not ready 1 I O compensation cell is ready 7 1 Reserv...

Page 165: ...ate 32 bit CRC code with fixed polynomial 9 2 Characteristics 32 bit data input and 32 bit data output Calculation period is 4 AHB clock cycles for 32 bit input data size from data entered to the calculation result available Free 8 bit register is unrelated to calculationand can be used for any other goals by any other peripheral devices Fixed polynomial 0x4C11DB7 X32 X26 X23 X22 X16 X12 X11 X10 X...

Page 166: ... 32 bit raw data and CRC_DATA register will receive the raw data and store the calculation result If the CRC_DATA register has not been cleared by software setting the CRC_CTL register the new input raw data will be calculated based on the result of previous value of CRC_DATA During CRC calculation AHB will not be hanged because of the existence of the 32 bit input buffer This module supplies an 8...

Page 167: ...tware writes and reads This register is used to calculate new data and the register can be written the new data directly Written value cannot be read because the read value is the previous CRC calculation result 9 4 2 Free data register CRC_FDATA Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 1...

Page 168: ... value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RST rw Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 RST Set this bit can reset the CRC_DATA register to the value of 0xFFFFFFFF then automatically cleared itself to 0 by hardware This bit will take no effe...

Page 169: ... CPU access to the system bus for some bus cycles Round robin scheduling is implemented in the bus matrix to ensure at least half of the system bus bandwidth for the CPU 10 2 Characteristics Programmable length of data to betransferred max to 65536 12 channels and each channel are configurable 7 for DMA0 and 5 for DMA1 AHB and APB peripherals FLASH SRAM can be accessed as source and destination Ea...

Page 170: ...s coming at the same time Channel management to control address data selection and data counting 10 4 Function overview 10 4 1 DMA operation Each DMA transfer consists of two operations including the loading of data from the source and the storage of the loaded data to the destination The source and destination addresses are computed by the DMA controller based on the programmed values in the DMA_...

Page 171: ...2 7 0 0x1 3 Write B4 7 0 0x2 4 Write B6 7 0 0x3 8 bits 32 bits 1 Read B0 7 0 0x0 2 Read B1 7 0 0x1 3 Read B2 7 0 0x2 4 Read B3 7 0 0x3 1 Write 000000B0 31 0 0x0 2 Write 000000B1 31 0 0x4 3 Write 000000B2 31 0 0x8 4 Write 000000B3 31 0 0xC 8 bits 16 bits 1 Read B0 7 0 0x0 2 Read B1 7 0 0x1 3 Read B2 7 0 0x2 4 Read B3 7 0 0x3 1 Write 00B0 15 0 0x0 2 Write 00B1 15 0 0x2 3 Write 00B2 15 0 0x4 4 Write ...

Page 172: ...ripheral Peripheral releases the request signal when it receives the acknowledge signal The DMA controller deasserts the acknowledge signal when it receives low request signal Peripheral launches the next request 10 4 3 Arbitration When two or more requests are received at the same time the arbiter determines which request is served based on the priorities of channels There are two stage prioritie...

Page 173: ... configuration When starting a new DMA transfer it is recommended to respect the following steps 1 Read the CHEN bit and judge whether the channel is enabled or not If the channel is enabled clear the CHEN bit by software When the CHEN bit is read as 0 configuring and starting a new DMA transfer is allowed 2 ConfiguretheM2M bit and DIRbit intheDMA_CHxCTLregisterto setthetransfermode 3 Configure th...

Page 174: ...errupt event occurs and enabled on the channel Figure 10 3 DMA interrupt logic and and and or FTFIFx FTFIEx HTFIFx HTFIEx ERRIFx ERRIEx CHxINTF NOTE x indicates channel number for DMA0 x 0 6 for DMA1 x 0 4 10 4 9 DMA request mapping Several requests from peripherals may be mapped to one DMA channel They are logically ORed before entering the DMA For details see the following Figure 10 4 DMA0 reque...

Page 175: ...annel 3 M2M SPI1 I2S1_TX USART0_RX I2C1_RX TIMER0_UP TIMER3_CH2 or or Channel 4 M2M USART1_RX I2C0_TX TIMER0_CH2 TIMER2_CH0 TIMER2_TG or or Channel 5 M2M USART1_TX I2C0_RX TIMER3_UP or or Channel 6 M2M Periphera l Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 TIMER0 TIMER0_CH0 TIMER0_CH1 TIMER0_CH3 TIMER0_TG TIMER0_CMT TIMER0_UP TIMER0_CH2 TIMER2 TIMER2_CH2 TIMER2_CH3 TIMER...

Page 176: ...e priority high low SPI2 I2S2_TX TIMER7_CH3 TIMER7_TG TIMER7_CMT or or Channel 1 M2M UART3_RX TIMER5_UP DAC_CH0 TIMER7_CH0 or or Channel 2 M2M SDIO TIMER6_UP DAC_CH1 or or Channel 3 M2M ADC2 UART3_TX TIMER4_CH0 TIMER7_CH1 or or Channel 4 M2M Table 10 4 DMA1 requests for each channel Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 TIMER5 TIMER5_UP TIMER6 TIMER6_UP TIMER7 TIMER7_CH2 TIM...

Page 177: ...GD32F403xx UserManual 177 Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 SDIO SDIO ...

Page 178: ... 27 23 19 15 11 7 3 ERRIFx Error flag of channel x x 0 6 Hardware set and software cleared by configuring DMA_INTC register 0 Transfer error has not occurred on channelx 1 Transfer error has occurred on channel x 26 22 18 14 10 6 2 HTFIFx Half transfer finish flag of channel x x 0 6 Hardware set and software cleared by configuring DMA_INTC register 0 Half number of transfer has not finished on cha...

Page 179: ...nel x x 0 6 0 No effect 1 Clear error flag 26 22 18 14 10 6 2 HTFIFCx Clear bit for half transfer finish flag of channelx x 0 6 0 No effect 1 Clear half transfer finish flag 25 21 17 13 9 5 1 FTFIFCx Clear bit for full transfer finish flag of channel x x 0 6 0 No effect 1 Clear full transfer finish flag 24 20 16 12 8 4 0 GIFCx Clear global interrupt flag of channel x x 0 6 0 No effect 1 Clear GIFx...

Page 180: ...a size of memory Software set and cleared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 9 8 PWIDTH 1 0 Transfer data size of peripheral Software set and cleared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 7 MNAGA Next address generation algorithm of memory Software set and cleared 0 Fixed address mode 1 Increasing ad...

Page 181: ... Enable bit for channel half transfer finish interrupt Software set and cleared 0 Disable channel half transfer finish interrupt 1 Enable channel half transfer finish interrupt 1 FTFIE Enable bit for channel full transfer finish interrupt Software set and cleared 0 Disable channel full transfer finish interrupt 1 Enable channel full transfer finish interrupt 0 CHEN Channel enable Software set and ...

Page 182: ...ADDR x 0 6 where x is a channel number Address offset 0x10 0x14 x Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PADDR 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PADDR 15 0 rw Bits Fields Descriptions 31 0 PADDR 31 0 Peripheral base address These bits can not be written when CHEN in the DMA_CHxCTL register is 1 When PWIDTH is 01 16 bit the LSB of these bits is ignored ...

Page 183: ...en CHEN in the DMA_CHxCTL register is 1 When MWIDTH in the DMA_CHxCTL register is 01 16 bit the LSB of these bits is ignored Access is automatically aligned to a half word address When MWIDTH in the DMA_CHxCTL register is 10 32 bit the two LSBs of these bits are ignored Access is automatically aligned to a word address ...

Page 184: ...an be accessedby a debug tool via Serial Wire SW Debug Port or JTAG interface JTAG Debug Port 11 2 1 Switch JTAG or SW interface By default the JTAGinterface is active The sequence for switching from JTAGto SWD is Send 50 or more TCK cycles withTMS 1 Send the 16 bit sequenceon TMS 1110011110011110 0xE79E LSB first Send 50 or more TCK cycles withTMS 1 The sequence for switching from SWD to JTAG is ...

Page 185: ...BSD JTAG IDCODE is 0x790007A3 11 2 4 Debug reset The JTAG DP and SW DP register are in the power on reset domain The System reset initializes the majority of the Cortex M4 excluding NVIC and debug logic FPB DWT and ITM TheNJTRST reset canresetJTAGTAPcontrolleronly So it canperform debugfeature under system reset Such as halt after reset which is the debugger sets halt under system reset and the co...

Page 186: ... in sleep mode 11 3 2 Debug support for TIMER I2C WWDGT FWDGT and CAN When the core halted and the corresponding bit in DBG control register 1 DBG_CTL0 is set the following behaved For TIMER the timer counters stopped and hold for debug For I2C SMBUS timeout hold for debug For WWDGT or FWDGT the counter clock stopped for debug For CAN the receive register stopped counting for debug ...

Page 187: ...his register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIMER10 _HOLD TIMER9_ HOLD TIMER8_ HOLD TIMER13 _HOLD TIMER12 _HOLD TIMER11 _HOLD Reserved CAN1_H OLD TIMER6_ HOLD TIMER5_ HOLD Reserved TIMER7_ HOLD I2C1_HO LD rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C0_HO LD CAN0_H OLD TIMER3_ HOLD TIMER2_ HOLD Reserved TIMER0_...

Page 188: ... 25 TIMER11_HOLD TIMER 11 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER 11 counter for debug when core halted 24 22 Reserved Must be kept at reset value 21 CAN1_HOLD CAN1 hold bit This bit is set and reset by software 0 no effect 1 the receive register of CAN1 stops receiving data when core halted 20 TIMER6_HOLD TIMER 6 hold bit This bit is set and reset by software 0...

Page 189: ...halted 12 TIMER2_HOLD TIMER 2 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER 2 counter for debug when core halted 11 Reserved Must be kept at reset value 10 TIMER0_HOLD TIMER 0 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER 0 counter for debug when core halted 9 WWDGT_HOLD WWDGT hold bit This bit is set and reset by software 0 no effect 1 h...

Page 190: ... and system clock are provided by CK_IRC8M a system reset generated when exit standby mode 1 DSLP_HOLD Deep sleep mode hold register This bit is set and reset by software 0 no effect 1 At the Deep sleep mode the clock of AHB bus and system clock are provided by CK_IRC8M 0 SLP_HOLD Sleep mode hold register This bit is set and reset by software 0 no effect 1 At the sleep mode the clock of AHB is on ...

Page 191: ... 8 bit or 6 bit Foreground calibration function Programmable samplingtime Data storage mode the most significant bit and the least significant bit DMA support Analog input channels 16 external analog inputs 1 channel for internal temperature sensor VSENSE 1 channel for internal reference voltage VREFINT Start of conversion can be initiated By software By hardware triggers Operation modes Converts ...

Page 192: ... 1 ADC internal input signals Internal signal name Description VSENSE Internal temperature sensor output voltage VREFINT Internal voltage reference output voltage Table 12 2 ADC input pins definition Name Description VDDA Analog power supply equal to VDD and 2 6 V VDDA 3 6 V VSSA Ground for analog power supply equal to VSS VREFP The positive reference voltage for the ADC 2 6 V VREFP VDDA VREFN The...

Page 193: ...alibration factor which is internally applied to theADC until the next ADC power off The application must not use the ADC during calibration and must wait until it is completed Calibration should be performed before startingA D conversion The calibrationis initiated by setting bit CLB 1 CLB bit stays at 1 during all the calibration sequence It is then cleared by hardware as soon as the calibration...

Page 194: ...pports up to 16 channels and each channel is called routine channel The RL 3 0 bits in theADC_RSQ0 register specify the total conversion sequence length The ADC_RSQ0 ADC_RSQ2 registers specify the selected channels of the routine sequence Note Although the ADC supports 18 multiplexed channels the maximum length of the sequence is only 16 12 4 5 Operation modes Single operation mode In the single o...

Page 195: ...e The conversion data will be stored in theADC_RDATA register Figure 12 3 Continuous operation mode CH2 CH2 CH2 CH2 CH2 CH2 EOC Routine trigger Sample Convert CH2 Software procedure for continuous operation on a routine channel 1 Set the CTN bit in the ADC_CTL1 register 2 Configure RSQ0 with the analog channel number 3 Configure ADC_SAMPTx register 4 Configure ETERC and ETSRC bits in the ADC_CTL1 ...

Page 196: ...6 CH2 CH1 EOC One circle of routine sequence RL 7 Routine trigger CH12 CH17 Software procedure for scan operation mode on a routine sequence 1 Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register 2 Configure ADC_RSQx and ADC_SAMPTx registers 3 Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need 4 Prepare the DMA module to transfer data from the ADC_RDATA ...

Page 197: ...e DMA module 6 Set the SWRCST bit or generate an external trigger for the routine sequence 7 Repeat step6 if in need 8 Wait the EOC flag to be set 9 Clear the EOC flag by writing 0 to it 12 4 6 Conversion result threshold monitor function The analog watchdog is enabled when the RWDEN bit in the ADC_CTL0 register is set for routine sequence This function is used to monitor whether the conversionres...

Page 198: ... to sample the input voltage can be specified by the SPTn 2 0 bits in theADC_SAMPT0 andADC_SAMPT1 registers A different sample time can be specified for each channel For 12 bits resolution the total sampling and conversion time is sampling time 12 5 CK_ADC cycles Example CK_ADC 30MHz and sample time is 1 5 cycles the total conversion time is 1 5 12 5 CK_ADC cycles that means 0 467us 12 4 9 Externa...

Page 199: ...nel ADC0_CH17 is enabled The temperature sensor can be used to measure the ambient temperature of the device The sensor output voltage can be converted into a digital value by ADC The sampling time for the temperature sensor is recommended to be set to at least ts_temp µs please refer to the datasheet When this sensor is not in use it can be put in power down mode by resetting theTSVREN bit The ou...

Page 200: ...own in Table 12 5 tCONV timings depending on resolution Table 12 5 tCONV timings depending on resolution DRES 1 0 bits tCONV ADC clock cycles tCONV ns at fADC 30MHz tSMPL min ADC clock cycles tADC ADC clock cycles tADC us at fADC 30MHz 12 12 5 417 ns 1 5 14 467 ns 10 10 5 350 ns 1 5 12 400 ns 8 8 5 283 ns 1 5 10 333 ns 6 6 5 217 ns 1 5 8 267 ns 12 4 13 On chip hardware oversampling The on chip har...

Page 201: ...s the upper bits of the result are simply truncated Figure 12 10 Numerical example with 5 bits shift and rounding shows a numerical example of the processing from a raw 20 bit accumulated data to the final 16 bit result Figure 12 10 Numerical example with 5 bits shift and rounding 2 A C D 6 Raw 20 bit data 19 15 11 7 3 0 1 5 6 6 15 11 7 3 0 Final result after 5 bit shift and rounding to nearest Th...

Page 202: ...e compared to standard conversion mode the sampling time remains equal throughout the oversampling sequence New data is supplied every N conversions and the equivalent delay is equal to N tADC N tSMPL tCONV 3 1 12 5 ADC sync mode In devices with more than one ADC the ADC sync modecan be used In ADC sync mode the conversion starts alternately or simultaneously triggered by ADC0 to ADC1 according to...

Page 203: ...equence configuredbytheETSRC 2 0 bitsintheADC_CTL1 register and ADC1 routine sequence is configured as software trigger mode At the end of conversion event on ADC0 or ADC1 an EOC interrupt is generated if enabled on one of the two ADC interrupt when the ADC0 ADC1 routine channels are all converted The behavior of routine parallel mode shows in the Figure 12 12 Routine parallel mode on 10 channels ...

Page 204: ... the Figure 12 13 Routine follow up fast mode the CTN bit of ADCs are set After an EOC interrupt is generated by ADC0 in case of setting the EOCIE bit we can use a 32 bit DMA which transfers to SRAM the ADC_RDATA register containing the ADC1 converted data in the 31 16 bits field and the ADC0 converted data in the 15 0 bits field Note The sampling time of the routine channel of the two ADCs should...

Page 205: ...e ADC1 converted data in the 31 16 bits field and the ADC0 converted data in the 15 0 bits field Note The maximum sampling time allowed is 14 CK_ADC cycles to avoid the overlap betweenADC0 andADC1 sampling phases in the event that they convert the same channel Figure 12 14 Routine follow up slowmode CH1 ADC0 ADC1 Routine trigger Sample Convert EOC ADC0 EOC ADC1 CH1 CH1 CH1 CH1 CH1 CH1 CH1 14 CK_AD...

Page 206: ... conversion 0 Conversion is not started 1 Conversion is started Set by hardware when routine sequence conversion starts Cleared by software writing 0 to it 3 2 Reserved Must be kept at reset value 1 EOC End flag of routine sequence conversion 0 No end of routine sequence conversion 1 End ofroutine sequence conversion Set by hardware at the end of a routine sequence conversion Cleared by software w...

Page 207: ...6 SYNCM 3 0 Sync mode selection These bits use to select the operating mode 0000 Free mode 0001 0101 Reserved 0110 Routine parallel mode 0111 Routine follow up fast mode 1000 Routine follow up slow mode 1001 1111 Reserved Note 1 These bits are only used in ADC0 2 Users must disable sync mode before any configuration change 15 13 DISNUM 2 0 Number of conversions in discontinuous mode The number of ...

Page 208: ...00 ADC channel 4 00101 ADC channel 5 00110 ADC channel 6 00111 ADC channel 7 01000 ADC channel 8 01001 ADC channel 9 01010 ADC channel 10 01011 ADC channel 11 01100 ADC channel 12 01101 ADC channel 13 01110 ADC channel 14 01111 ADC channel15 10000 ADC channel16 10001 ADC channel17 Other values are reserved Note ADC0 analog inputs Channel16 and Channel17 are internally connected to the temperature ...

Page 209: ...of routine sequence Set 1 on this bit starts a conversion of a routine sequence if ETSRC is 111 It is set by software and cleared by software or by hardware immediately after the conversion starts 21 Reserved Must be kept at reset value 20 ETERC External trigger enable for routine sequence 0 External trigger for routine sequence disable 1 External trigger for routine sequence enable 19 17 ETSRC 2 ...

Page 210: ...1 Calibration start 1 CTN Continuous mode 0 Continuous operation mode disable 1 Continuous operation mode enable 0 ADCON ADC ON The ADC will be wake up when this bit is changed from low to high and take a stabilization time When this bit is high and 1 is written to it with other bits of this register unchanged the conversion will start 0 ADC disable and power down 1 ADC enable 12 7 4 Sample time r...

Page 211: ...les 011 channel sampling time is 28 5 cycles 100 channel sampling time is 41 5 cycles 101 channel sampling time is 55 5 cycles 110 channel sampling time is 71 5 cycles 111 channel sampling time is 239 5 cycles 12 7 5 Sample time register 1 ADC_SAMPT1 Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ...

Page 212: ...s 41 5 cycles 101 channel sampling time is 55 5 cycles 110 channel sampling time is 71 5 cycles 111 channel sampling time is 239 5 cycles 12 7 6 Watchdog high threshold register ADC_WDHT Address offset 0x24 Reset value 0x0000 0FFF This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WDHT 11 0 rw Bits...

Page 213: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RL 3 0 RSQ15 4 1 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSQ15 0 RSQ14 4 0 RSQ13 4 0 RSQ12 4 0 rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 20 RL 3 0 Routine sequence length The total number of conversion in routine sequence equals to RL 3 0 1 19 15 RSQ15 4 0 refer to RSQ0 4 0 description 14 10 RSQ14...

Page 214: ...o RSQ0 4 0 description 12 7 10 Routine sequence register 2 ADC_RSQ2 Address offset 0x34 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RSQ5 4 0 RSQ4 4 0 RSQ3 4 1 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSQ3 0 RSQ2 4 0 RSQ1 4 0 RSQ0 4 0 rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset v...

Page 215: ...the routine data of ADC1 These bits are only used in ADC0 15 0 RDATA 15 0 Routine channel data These bits contain routine channelconversion value which is read only 12 7 12 Oversample control register ADC_OVSAMPCTL Address offset 0x80 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 216: ...01 Shift 1 bit 0010 Shift 2 bits 0011 Shift 3 bits 0100 Shift 4 bits 0101 Shift 5 bits 0110 Shift 6 bits 0111 Shift 7 bits 1000 Shift 8 bits Other codes reserved Note The software allows this bit to be written only when ADCON 0 this ensures that no conversion is in progress 4 2 OVSR 2 0 Oversampling ratio This bit filed defines the number of oversampling ratio 000 2x 001 4x 010 8x 011 16x 100 32x ...

Page 217: ...GD32F403xx UserManual 217 ensures that no conversion is in progress ...

Page 218: ...e optionally buffered for higher drive capability The two DACs can work independently or concurrently 13 2 Characteristics DAC s main features are as follows 8 bit or 12 bit resolution Right or left data alignment DMA support Conversion update synchronously Conversion triggered by external triggers Configurable internal buffer extern voltage reference VREF Noise wave LFSR noise mode andTriangle no...

Page 219: ...r analog power supply Power VREF reference voltage Analog Input DAC_OUTx DACx analog output Analog output The GPIO pins PA4 for DAC0 PA5 for DAC1 should be configured to analog mode before enable the DAC module 13 3 Function description 13 3 1 DAC enable TheDACs canbe powered on by settingtheDENx bit intheDAC_CTLregister AtWAKEUP time is needed to startup the analog DAC submodule 13 3 2 DAC output...

Page 220: ...er The TIMERx_TRGO signals are generated from the timers while the software trigger can be generated by setting the SWTRx bits in the DAC_SWT register 13 3 5 DAC workflow If the external trigger is enabled by setting the DTENx bit in DAC_CTL register the DAC holding data is transferred to the DAC output data DACx_DO register when the selected trigger event happened When the external trigger is dis...

Page 221: ...X0 X4 X XOR X12 NOR 12 Triangle noise mode in this mode a triangle signal is added to the DACx_DH value The minimum value of the triangle signal is 0 while the maximum value of the triangle signal is 2 DWBWx 1 Figure 13 3 DAC triangle noisewave 2 DWBWx 1 DACx_DH value 13 3 7 DAC output calculate The analog output voltages on the DAC pin are determined by the following equation VDACx_out VREF DAC_D...

Page 222: ..._DH to DACx_DO of two DACs is performing at the same time There are three concurrent registers that can be used to load the DACx_DH value DACC_R8DH DACC_R12DH and DACC_L12DH You just need to access a unique register to realize driving both DACs at the same time When external trigger is enabled DTENx bit of two DACs must be set both DTSEL0 and DTSEL1 bits shouldbe configured with the same value Whe...

Page 223: ...of the noise wave signal of DAC1 These bits indicate that unmask LFSR bit n 1 0 in LFSR noise mode or the amplitude of the triangle is 2 n 1 1 in triangle noise mode where n is the bit width of wave 0000 The bit width of the wave signal is 1 0001 The bit width of the wave signal is 2 0010 The bit width of the wave signal is 3 0011 The bit width of the wave signal is 4 0100 The bit width of the wav...

Page 224: ... 1 DAC1 enabled 15 13 Reserved Must be kept at reset value 12 DDMAEN0 DAC0 DMA enable 0 DAC0 DMA mode disabled 1 DAC0 DMA mode enabled 11 8 DWBW0 3 0 DAC0 noise wave bit width These bits specify bit width of the noise wave signal of DAC0 These bits indicate that unmask LFSR bit n 1 0 in LFSR noise mode or the amplitude of the triangle is 2 n 1 1 in triangle noise mode where n is the bit width of w...

Page 225: ... 1 000 TIMER5 TRGO 001 TIMER2 TRGO 010 TIMER6 TRGO 011 Reserved 100 Reserved 101 TIMER3 TRGO 110 EXTI line 9 111 Software trigger 2 DTEN0 DAC0 trigger enable 0 DAC0 trigger disabled 1 DAC0 trigger enabled 1 DBOFF0 DAC0 output buffer turn off 0 DAC0 output buffer turns on to reduce the output impedance and improve the driving capability 1 DAC0 output buffer turns off 0 DEN0 DAC0 enable 0 DAC0 disab...

Page 226: ...his register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC0_DH 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 DAC0_DH 11 0 DAC0 12 bit right aligned data These bits specify the data that is to be converted by DAC0 13 4 4 DAC0 12 bit left aligned data holding register DA...

Page 227: ...rved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC0_DH 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 DAC0_DH 7 0 DAC0 8 bit right aligned data These bits specify the MSB 8 bits of the data that is to be converted by DAC0 13 4 6 DAC1 12 bit right aligned data holding register DAC1_R12DH Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed...

Page 228: ...set value 15 4 DAC1_DH 11 0 DAC1 12 bit left aligned data These bits specify the data that is to be converted by DAC1 3 0 Reserved Must be kept at reset value 13 4 8 DAC1 8 bit right aligned data holding register DAC1_R8DH Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 ...

Page 229: ...These bits specify the data that is to be converted by DAC1 15 12 Reserved Must be kept at reset value 11 0 DAC0_DH 11 0 DAC0 12 bit right aligned data These bits specify the data that is to be converted by DAC0 13 4 10 DAC concurrent mode 12 bit left aligned data holding register DACC_L12DH Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 ...

Page 230: ...served 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC1_DH 7 0 DAC0_DH 7 0 rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 8 DAC1_DH 7 0 DAC1 8 bit right aligned data These bits specify the MSB 8 bit of the data that is to be converted by DAC1 7 0 DAC0_DH 7 0 DAC0 8 bit right aligned data These bits specify the MSB 8 bit of the data that is to be converted by DAC0 13 4 12 DA...

Page 231: ... data output register DAC1_DO Address offset 0x30 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC1_DO 11 0 r Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 DAC1_DO 11 0 DAC1 data output These bits which are read only reflect the data that is ...

Page 232: ...he FWDGT can operate even if the main clock fails It s suitable for the situation that requires an independent environment and lower timing accuracy The free watchdog timer causes a reset when the internal down counter reaches 0 The register write protection functionin free watchdog can beenabled to prevent it from changing the configuration unexpectedly 14 1 2 Characteristics Free running 12 bit ...

Page 233: ...et thesoftwareshouldreloadthecounterbefore the counter reaches 0x000 The FWDGT_PSC register and the FWDGT_RLD register are written protected Before writing these registers the software should write the value 0x5555 to the FWDGT_CTL register These registers will be protected again by writing any other value to the FWDGT_CTL register When an update operation of the prescaler register FWDGT_PSC or th...

Page 234: ...1 0 025 26208 025 The FWDGT timeout can be more accurate by calibrating the IRC40K Note When after the execution of watchdog reload operation if the MCU needs enter the deepsleep standby modeimmediately more than 3 IRC40K clock intervals must be inserted in the middle of reload and deepsleep standby mode commands by software setting ...

Page 235: ..._RLD write protection 0xCCCC Start the free watchdog counter When the counter reduces to 0 the free watchdog generates a reset 0xAAAA Reload the counter Prescaler register FWDGT_PSC Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserve...

Page 236: ...e kept at reset value 11 0 RLD 11 0 Free watchdog timer counter reload value Write 0xAAAA in the FWDGT_CTL register will reload the FWDGT counter with the RLD value These bits are write protected Write 0x5555 in the FWDGT_CTL register before writing these bits During a write operation to this register the RUD bit in the FWDGT_STAT register is set and the value read from this register is invalid If...

Page 237: ...peration to FWDGT_RLD register this bit is set and the value read from FWDGT_RLD register is invalid This bit is reset by hardware after the update operation of FWDGT_RLD register 0 PUD Free watchdog timer prescaler value update During a write operation to FWDGT_PSC register this bit is set and the value read from FWDGT_PSC register is invalid Thisbit is reset by hardware after the update operatio...

Page 238: ...itable for the situation that requires an accurate timing 14 2 2 Characteristics Programmable free running 7 bit downcounter Generate reset in two conditions when WWDGT is enabled Reset when the counter reached 0x3F The counter is refreshed when the value of the counter is greater than the window register value Early wakeup interrupt EWI if the watchdog is started and the interrupt is enabled the ...

Page 239: ...keup interrupt EWI is enabled by setting the EWIE bit in the WWDGT_CFG register and the interrupt will be generated when the counter reaches 0x40 The software cando somethingsuchas communicationordataloggingintheinterruptserviceroutine ISR in order to analyse the reason of software malfunctions or save the important data before resetting the device Moreover the software can reload the counter in I...

Page 240: ...CNT 6 0 0x40 Max timeout value CNT 6 0 0x7F 1 1 00 48 76 μs 3 12 ms 1 2 01 97 52 μs 6 24 ms 1 4 10 195 04 μs 12 48 ms 1 8 11 390 08 μs 24 96 ms If the WWDGT_HOLD bit in DBG module is cleared the WWDGT continues to work even the Cortex M4 core halted Debug mode While the WWDGT_HOLD bit is set the WWDGT stops in Debug mode ...

Page 241: ... the watchdog timer counter A reset occurs when the value of this counter decreases from 0x40 to 0x3F When the value of this counter is greater than the window value writing this counter also causes a reset Configuration register WWDGT_CFG Address offset 0x04 Reset value 0x0000 007F This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res...

Page 242: ...gister WWDGT_STAT Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWIF rw Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 EWIF Early wakeup interrupt flag When the counter reaches 0x40 this bit is set by hardware e...

Page 243: ...times slower than the PCLK1 clock RTC clock source A HXTAL clock divided by 128 B LXTAL oscillator clock C IRC40K oscillator clock Maskable interrupt source A Alarm interrupt B Second interrupt C Overflow interrupt 15 3 Function overview The RTC circuits consist of two major units APB interface located in PCLK1 clock domain and RTC core located in RTC clock domain APB Interface is connected with t...

Page 244: ...ng the BKPWEN bit in the PMU_CTL 15 3 2 RTC reading TheAPB interface and RTC core are located in two different power supply domains In the RTC core only counter and divider registers are readable registers And the values in the two registers and the RTC flags are internally updated at each rising edge of the RTC clock which is resynchronized by theAPB1 clock When the APB interface is immediately e...

Page 245: ...flag assertion Before the update of the RTC Counter the RTC second interrupt flag SCIF is asserted on the last RTCCLK cycle Before the counter equal to the RTCAlarm value which stored in theAlarm register increases by one the RTCAlarm interrupt flag ALRMIF is asserted on the last RTCCLK cycle Before the counter equals to 0x0 the RTC Overflow interrupt flag OVIF is asserted on the last RTCCLK cycle...

Page 246: ...246 Figure 15 3 RTC second and overflow waveform example RTC_PSC 3 RTC_ Overflow FFFFFFFD FFFFFFFE FFFFFFFF 0 1 RTC_Second RTC_ CNT OVIF RTC_PSC OVIF flag can be cleared by software RTCCLK 2 3 1 0 3 1 1 3 3 2 1 0 2 0 2 0 2 1 ...

Page 247: ...pt at reset value 2 OVIE Overflow interrupt enable 0 Disable overflow interrupt 1 Enable overflow interrupt 1 ALRMIE Alarm interrupt enable 0 Disable alarm interrupt 1 Enable alarm interrupt 0 SCIE Second interrupt enable 0 Disable second interrupt 1 Enable second interrupt 15 4 2 RTC control register RTC_CTL Address offset 0x04 Reset value 0x0020 This register can be accessed by half word 16 bit ...

Page 248: ...Alarm event not detected 1 Alarm event detected An interrupt named RTC global interrupt will occur if the ALRMIE bit is set in RTC_INTEN And another interrupt named the RTC Alarm interrupt will occur if the EXTI 17 is enabled in interrupt mode 0 SCIF Second interrupt flag 0 Second event not detected 1 Second event detected An interrupt will occur if the SCIE bit is set in RTC_INTEN Set by hardware...

Page 249: ...he frequency of SC_CLK is the RTCCLK frequency divided by PSC 19 0 1 15 4 5 RTC divider high register RTC_DIVH Address offset 0x10 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DIV 19 16 r Bits Fields Descriptions 31 4 Reserved Must be kept at reset value 3 ...

Page 250: ...r can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 31 16 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 31 16 RTC counter value high 15 4 8 RTC counter low register RTC_CNTL Address offset 0x1C Reset value 0x0000 This register can be accessed by half word 16 bit or ...

Page 251: ...7 6 5 4 3 2 1 0 ALRM 31 16 w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 ALRM 31 16 RTC alarm value high 15 4 10 RTC alarm low register RTC_ALRML Address offset 0x24 Reset value 0xFFFF This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALRM 15 0 w Bits Fields De...

Page 252: ...Single Pulse Quadrature Decoder Master slave management Inter connection 1 2 3 TRGO TO DAC DMA 4 Debug Mode 1 TIMER0 ITI0 Reserved ITI1 Reserved ITI2 TIMER2_TRGO ITI3 TIMER3_TRGO TIMER7 ITI0 TIMER0_TRGO ITI1 Reserved ITI2 TIMER3_TRGO ITI3 Reserved 2 TIMER2 ITI0 TIMER0_TRGO ITI1 Reserved ITI2 Reserved ITI3 TIMER3_TRGO TIMER3 ITI0 TIMER0_TRGO ITI1 Reserved ITI2 TIMER2_TRGO ITI3 TIMER7_TRGO 3 TIMER8 ...

Page 253: ... 16 1 2 Characteristics Total channel num 4 Counter width 16 bits Source of counter clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Quadrature Decoder used to track motion and determine both rotation direction and position Hall sensor for 3 phase motor control Programmable prescaler 16 bits The factor canb...

Page 254: ...r Interrupt Register set and update Interrupt collector and controller APB BUS CK_TIMER CH0_IN CH1_IN CH2_IN CH3_IN CI0 ITI0 ITI1 ITI2 ITI3 ETI CAR Repeater Output Logic generation of outputs signals in compare PWM and mixed modes according to initialization complementary mode software output control deadtime insertion break input output mask and polarity control BRKEN BRKI N CKM clock monitor CH0...

Page 255: ...is clocked by other clock sources selected by theTRGS 2 0 in the TIMERx_SMCFG register details as follows When the SMC 2 0 bits are set to 0x4 0x5 or 0x6 the internal clock CK_TIMER is the counter prescaler driving clock source Figure 16 2 Timing chart of internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 ...

Page 256: ...ETI signal rising edge to clock the counter prescaler Clock prescaler The counter clock PSC_CK is obtained by the TIMER_CK through the prescaler and the prescale factor can be configured from 1 to 65536 through the prescaler register TIMERx_PSC The new written prescaler value will not take effect until the next update event Figure 16 3 Timing chart of PSC value change from 0 to 2 TIMER_CK CEN PSC_...

Page 257: ...event is disabled When an update event occurs all the shadow registers repetition counter counter auto reload register prescaler register are updated Figure 16 4 Timing chart of up counting mode PSC 0 2 show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR 0x99 Figure 16 4 Timing chart of up counting mode PSC 0 2 CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2...

Page 258: ...gister to 0 in a count down direction Once the counter reaches to 0 the counter the counter will start counting down from the counter reload value again and an underflow event will be generated In addition the update event will be generated after TIMERx_CREP 1 times of underflow The counting direction bit DIR in the TIMERx_CTL0 register should beset to 1 for the down counting mode When the update ...

Page 259: ...9 Figure 16 6 Timing chart of down counting mode PSC 0 2 CEN PSC_CLK CNT_REG 5 4 3 2 1 0 99 98 97 96 95 94 93 92 Update event UPE Update interrupt flag UPIF CNT_REG 3 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set PSC 0 PSC 2 TIMER_CK 91 PSC_CLK 2 1 0 99 98 ...

Page 260: ...and generates an underflow event when the counter counts to 1 in the down counting direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode Setting the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0 and generates an update event irrespective of whether the counter is counting ...

Page 261: ...vents canbeconfigured by the TIMERx_CREP register Counter repetition is used to generator update event or updates the timer registers only after a given number N 1 of cycles of the counter where N is CREP in TIMERx_CREP register The repetition counter is decremented at each counter overflow does not exist in down counting mode and underflow does not exist in up counting mode Setting the UPG bit in...

Page 262: ... then the subsequent update events will be generated on the overflow Figure 16 9 Repetition timechart for center aligned counter CEN 3 2 1 0 1 2 98 99 98 2 1 0 Underflow Overflow TIMERx_CREP 0x0 TIMER_CK 1 2 98 99 98 2 UPIF TIMERx_CREP 0x1 1 0 1 2 98 99 98 97 UPIF UPIF TIMERx_CREP 0x2 PSC_CLK Figure 16 10 Repetition timechart for up counter CEN CNT_REG 96 97 98 99 0 1 98 99 0 1 98 99 Underflow Ove...

Page 263: ...l is built around a channel capture compare register including an input stage channel controller and an output stage Channel input capture function Channel input capture function allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital filter a channel polarity selection edge detection and a channel prescaler When a...

Page 264: ...edge are detected You can select one of them by CHxP One more selector is for the other channel and trig controlled by CHxMS The IC_prescaler make several the input event generate one effective capture event On the capture event TIMERx_CHxCV will restore the value of counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the i...

Page 265: ...n measure the PWM duty Channel output compare function In channel output compare function the TIMERx can generate timed pulses with programmableposition polarity durationandfrequency Whenthecountermatchesthevalue in the TIMERx_CHxCV register of an output compare channel the channel n output can be set cleared or toggled based on CHxCOMCTL When the counter reaches the value in the TIMERx_CHxCV regi...

Page 266: ...gisters Based on the counter mode we can also divide PWM into EAPWM Edge aligned PWM and CAPWM Centre aligned PWM The EAPWM period is determined by TIMERx_CAR and duty cycle is determined by TIMERx_CHxCV Figure16 14 EAPWM timechartshowstheEAPWM outputand interrupts waveform The CAPWM period is determined by 2 TIMERx_CAR and duty cycle is by 2 TIMERx_CHxCV Figure 16 15 CAPWM timechart shows the CAP...

Page 267: ...1 Cx OUT Interrupt signal CHxIF CHxOF CAM 2 b01 downonly CAM 2 b10 up only CHxIF CHxOF CAM 2 b11 up down CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode the OxCPRE signal Channel x Output prepare signal is definedby settingtheCHxCOMCTLfiled TheOxCPREsignalhas several types of output function These include keeping the original level by setting the ...

Page 268: ...05 Here the output can be forced to an inactive active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values The OxCPRE signal can be forced to 0 when the ETIFE signal is derived from the external ETI pin and when it is set to a high level by setting the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register The OxCPRE signal will not return to its active level u...

Page 269: ... clock is enable CHx_O ISOx CHx_ON ISOxN 1 0 1 1 0 0 1 0 0 CHx_O CHx_ON LOW CHx_O CHx_ON output disable 1 CHx_O LOW CHx_O output disable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON LOW CHx_ON output disable 1 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 0 CHx_O CHxP CHx_O output disable CHx_ON CHxNP CHx_ON output d...

Page 270: ...AL occurs again OxCPRE is cleared CHx_Osignal will be cleared at once while CHx_ON signal remains at the low value until the end of the dead time delay Sometimes we can see corner cases about the dead time insertion For example The dead time delay is greater than or equal to the CHx_O duty cycle then the CHx_O signal is always the inactive value As show in the Figure 16 16 Complementary output wit...

Page 271: ... a break occurs the BRKIF bit in the TIMERx_INTF register is set If BRKIE is 1 an interrupt generated Figure 16 17 Output behavior in response to a break The breakhigh active OxCPRE CHx_O CHx_ON BRKIN CHx_O CHx_ON CHx_O CHx_ON ISOx ISOxN ISOx ISOxN CHxEN 1 CHxNEN 1 CHxP 0 CHxNP 0 ISOx ISOxN CHxEN 1 CHxNEN 0 CHxP 0 CHxNP 0 ISOx ISOxN CHxEN 1 CHxNEN 0 CHxP 0 CHxNP 0 ISOx ISOxN Quadrature decoder The...

Page 272: ...0FE0 CI1FE1 Rising Falling Rising Falling CI0 only counting CI1FE1 High Down Up CI1FE1 Low Up Down CI1 only counting CI0FE0 High Up Down CI0FE0 Low Down Up CI0 and CI1 counting CI1FE1 High Down Up X X CI1FE1 Low Up Down X X CI0FE0 High X X Up Down CI0FE0 Low X X Down Up Note means no counting X means impossible Figure 16 18 Example of counter operation in encoder interface mode CI0 CI1 UP down Cou...

Page 273: ...back circuit is finished also you change configuration to fit your request About the TIMER_in it need have input XOR function so you can choose from Advanced General L0TIMER And TIMER_out need have functions of complementary and Dead time so only advanced timer can be chosen Else based on the timers internal connection relationship pair s timers can be selected For example TIMER_in TIMER0 TIMER_ou...

Page 274: ...PU Core Hall Sensor Rotor Position signals Driver Motor MCU BLDC Motor Figure 16 21 Hall sensor timing between two timers CH0VAL Counter CI0 OXR CH0_IN CH1_IN CH2_IN CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Va Va Vb Vb Vc Vc Advanced General L0 TIMER_in under input capture mode Advanced TIMER_out under output compare mode PWM with Dead time ...

Page 275: ... ITI3 100 CI0F_ED 101 CI0FE0 110 CI1FE1 111 ETIFP If you choose the CI0FE0 or CI1FE1 configure the CHxP and CHxNP for the polarity selection and inversion If you choose the ETIF configure the ETP for polarity selection and inversion For the ITIx no filter and prescaler can be used FortheCIx configureFilter by CHxCAPFLT no prescaler can be used For the ETIF configure Filter by ETFC and Prescaler by...

Page 276: ...EN CNT_REG 5E 5F 60 61 62 CI0 TRGIF CI0FE0 63 Exam3 Event mode The counter will start to count when a rising trigger input TRGS 2 0 3 b11 1 ETIF is the selection ETP 0 no polarity change ETPSC 1 divided by 2 ETFC 0 no filter Figure 16 24 Event mode TIMER_CK CNT_REG 5E 5F 60 61 ETI TRGIF ETIFP Single pulse mode Single pulse mode is opposite to the repetitive mode which can be enabled by setting SPM...

Page 277: ...fter a trigger rising occurs in the single pulse mode the OxCPRE signal will immediately be forced to the state which the OxCPRE signal will change to as the compare match event occurs without taking the comparison result into account The CHxCOMFEN bit is available only when the output channel is configured to operate in the PWM0 or PWM1 output mode and the trigger source is derived from the trigg...

Page 278: ...ate event UPE as trigger output MMC 3 b010 in the TIMER2_CTL1 register Then timer2 drives a periodic signal on each counter overflow 2 Configure theTimer2 period TIMER2_CAR registers 3 Select the Timer0 input trigger source from Timer2 TRGS 3 b010 in the TIMERx_SMCFGregister 4 ConfigureTimer0 in external clock mode 0 SMC 3 b111 inTIMERx_SMCFG register 5 Start Timer0 by writing 1 in the CEN bit TIM...

Page 279: ...of TIMER2 TIMER_CK CNT_REG CNT_REG CEN 61 62 63 11 12 13 TRGIF 14 TIMER2 TIMER0 Using an external trigger to start 2 timers synchronously We configure the start of Timer0 is triggered by the enableof Timer2 and Timer2 is triggered by its CI0input risesedge To ensure2timers start synchronously Timer2must beconfigured in Master Slave mode Do as follow 1 Configure Timer2 slave mode to get the input t...

Page 280: ...MATB In fact register TIMERx_DMATB is only a buffer timer will map theTIMERx_DMATB to an internal register appointed by the field of DMATA in TIMERx_DMACFG If the field of DMATC in TIMERx_DMACFG is 0 1 transfer then the timer s DMA request is finished While if TIMERx_DMATC is not 0 such as 3 4 transfers then timer will send 3 more requests to DMA and DMA will access timer s registers DMATA 0x4 DMA...

Page 281: ...or TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 Center aligned and counting down assert mode The counter counts under center aligned and channel is configured in output mode CHxMS 00 in TIMERx_CHCTL0 register O...

Page 282: ...bit is used to enable or disable the update event generation 0 Update event enable When an update event occurs the corresponding shadow registers are loaded with their preloaded values These events generate update event The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event 1 Update event disable Note When this bit is set to 1 setting UPG...

Page 283: ... is reset CH0_O is set low 1 When POEN bit is reset CH0_O is set high The CH0_O output changes after a dead time if CH0_ON is implemented This bit can be modified onlywhen PROT 1 0 bits in TIMERx_CCHP register is 00 7 TI0S Channel 0 trigger input selection 0 The TIMERx_CH0 pin input is selected as channel 0 trigger input 1 The result of combinational XOR of TIMERx_CH0 CH1 and CH2 pins is selected ...

Page 284: ...gister update control When the commutation control shadow enable for CHxEN CHxNEN and CHxCOMCTL bits are set CCSE 1 these shadow registers update are controlled as below 0 The shadow registers update by when CMTG bit is set 1 The shadow registers update by when CMTG bit is set or a rising edge of TRGI occurs When a channel does not have a complementary output this bit has no effect 1 Reserved Must...

Page 285: ... 1 0 External trigger prescaler The frequency of external trigger signal ETIFP must not be at higher than 1 4 of TIMER_CK frequency When the external trigger signal is a fast clock the prescaler can be enabled to reduce ETIFP frequency 00 Prescaler disable 01 The prescaler is 2 10 The prescaler is 4 11 The prescaler is 8 11 8 ETFC 3 0 External trigger filter control The external trigger can be fil...

Page 286: ... bits must not be changed when slave mode is enabled 3 Reserved Must be kept at reset value 2 0 SMC 2 0 Slave mode control 000 Disable mode The slave mode is disabled The prescaler is clocked directly by the internal clock TIMER_CK when CEN bit is set high 001 Quadrature decoder mode 0 The counter counts on CI0FE0 edge while the direction depends on CI1FE1 level 010 Quadrature decoder mode 1 The c...

Page 287: ...t be kept at reset value 14 TRGDEN Trigger DMA request enable 0 disabled 1 enabled 13 CMTDEN Commutation DMA request enable 0 disabled 1 enabled 12 CH3DEN Channel 3 capture compare DMA request enable 0 disabled 1 enabled 11 CH2DEN Channel 2 capture compare DMA request enable 0 disabled 1 enabled 10 CH1DEN Channel 1 capture compare DMA request enable 0 disabled 1 enabled 9 CH0DEN Channel 0 capture ...

Page 288: ...offset 0x10 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 15 13 Reserved Must be kept at reset value 12 CH3OF Channel 3 over capture flag ...

Page 289: ...nterrupt flag This flag is set by hardware when channel s commutation event occurs and cleared by software 0 No channel commutation interrupt occurred 1 Channel commutation interrupt occurred 4 CH3IF Channel 3 s capture compare interrupt flag Refer to CH0IF description 3 CH2IF Channel 2 s capture compare interrupt flag Refer to CH0IF description 2 CH1IF Channel 1 s capture compare interrupt flag R...

Page 290: ... the TRGIF flag in TIMERx_INTF register is set related interrupt or DMA transfer can occur if enabled 0 No generate a trigger event 1 Generate a trigger event 5 CMTG Channel commutation event generation This bit is set by software and cleared by hardware automatically When this bit is set channel s capture compare controlregisters CHxEN CHxNEN and CHxCOMCTL bits are updated based on the value of C...

Page 291: ...x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1COM CEN CH1COMCTL 2 0 CH1COM SEN CH1COM FEN CH1MS 1 0 CH0COM CEN CH0COMCTL 2 0 CH0COM SEN CH0COM FEN CH0MS 1 0 CH1CAPFLT 3 0 CH1CAPPSC 1 0 CH0CAPFLT 3 0 CH0CAPPSC 1 0 rw rw rw rw rw rw Output compare mode Bits Fields Descriptions 15 CH1COMCEN Channel 1 output compare clear enable Refer t...

Page 292: ...are register TIMERx_CH0CV 011 Toggle on match O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV 100 Force low O0CPRE is forced to low level 101 Force high O0CPRE is forced to high level 110 PWM mode0 When counting up O0CPRE is high when the counter is smaller than TIMERx_CH0CV and low otherwise When counting down O0CPRE is low when the counter is larger than TIM...

Page 293: ...s programmed as input mode IS0 is connected to CI1FE0 11 Channel 0 is programmed as input mode IS0 is connected to ITS Note When CH0MS 1 0 11 it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register Input capture mode Bits Fields Descriptions 15 12 CH1CAPFLT 3 0 Channel 1 input capture filter control Refer to CH0CAPFLT description 11 10 CH1CAPPSC 1 0 Channel 1...

Page 294: ...ut capture occurs on every 8 channel input edges 1 0 CH0MS 1 0 Channel 0 mode selection Same as Output compare mode Channel control register 1 TIMERx_CHCTL1 Address offset 0x1C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3COM CEN CH3COMCTL 2 0 CH3COM SEN CH3COM FEN CH3MS 1 0 CH2COM CEN CH2COMCTL 2 0 CH2COM SEN CH2COM F...

Page 295: ...ive level and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits 000 Timing mode The O2CPRE signal keeps stable independent of the comparison between the output compare register TIMERx_CH2CV and the counter TIMERx_CNT 001 Set the channel output O2CPRE signal is forced high when the counter is equals to the output compare register TIMERx_CH2CV 010 Clear the channel output O2CPRE sign...

Page 296: ...t quickly compare disable 1 Channel 2 output quickly compare enable 1 0 CH2MS 1 0 Channel 2 I O mode selection This bit field specifies the work mode of the channel and the input signal selection This bit field is writable only when the channel is not active CH2EN bit in TIMERx_CHCTL2 register is reset 00 Channel 2 is programmed as output mode 01 Channel 2 is programmed as input mode IS2 is connec...

Page 297: ... capture prescaler This bit field specifies the factor of the prescaler on channel 2 input The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear 00 Prescaler disable input capture occurs on every channel input edge 01 The input capture occurs on every 2 channel input edges 10 The input capture occurs on every 4 channel input edges 11 The input capture occurs on every 8 channel i...

Page 298: ...fer to CH0P description 4 CH1EN Channel 1 capture compare function enable Refer to CH0EN description 3 CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode this bit specifies the complementary output signal polarity 0 Channel 0 complementary output high level is active level 1 Channel 0 complementary output low level is active level When channel 0 is configured...

Page 299: ...0 bit filed in TIMERx_CCHP register is 11 or 10 0 CH0EN Channel 0 capture compare function enable When channel 0 is configured in output mode setting this bit enables CH0_O signal in active state When channel 0 is configured in input mode setting this bit enables the capture event in channel0 0 Channel 0 disabled 1 Channel 0 enabled Counter register TIMERx_CNT Address offset 0x24 Reset value 0x000...

Page 300: ... specifies the auto reload value of the counter Note When the timer is configured in input capture mode this register must be configured a non zero value such as 0xFFFF which is larger than user expected value Counter repetition register TIMERx_CREP Address offset 0x30 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved...

Page 301: ...adow register updates every update event Channel 1 capture compare value register TIMERx_CH1CV Address offset 0x38 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1VAL 15 0 rw Bits Fields Descriptions 15 0 CH1VAL 15 0 Capture or compare value of channel1 When channel 1 is configured in input mode this bit filed indicates t...

Page 302: ...d 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3VAL 15 0 rw Bits Fields Descriptions 15 0 CH3VAL 15 0 Capture or compare value of channel 3 When channel3 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 3 is configured in output mode this bit filed contains value to be compared to the count...

Page 303: ...reak enable This bit can be set to enable the BRKIN and CCS clock failure event inputs 0 Break inputs disabled 1 Break inputs enabled This bit can be modified only when PROT 1 0 bit filed in TIMERx_CCHP register is 00 11 ROS Run mode off state configure When POEN bit is set this bit specifies the output state for the channels which has a complementary output and has been configured in output mode ...

Page 304: ... channel is configured in output are writing protected This bit field can be written only once after the reset Once the TIMERx_CCHP register has been written this bit field will be writing protected 7 0 DTCFG 7 0 Dead time configure The relationship between DTVAL value and the duration of dead time is as follow DTCFG 7 5 The duration of dead time 3 b0xx DTCFG 7 0 tDTS_CK 3 b10x 64 DTCFG 5 0 tDTS_C...

Page 305: ...accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMATB 15 0 rw Bits Fields Descriptions 15 0 DMATB 15 0 DMA transfer buffer When a read or write operation is assigned to this register the register located at the address range Start Addr Transfer Timer 4 will be accessed The transfer Timer is calculated by hardware and ranges from 0 to DMATC Configuration register T...

Page 306: ...GD32F403xx UserManual 306 0 No effect 0 OUTSEL The output value selection This bit field set and reset by software 1 If POEN and IOS is 0 the output disabled 0 No effect ...

Page 307: ...r width 16 bits Sourceof countclockis selectable internalclock internal trigger external input external trigger Multiple counter modes count up count down count up down Quadrature decoder used to track motion and determine both rotation direction and position Hall sensor for 3 phase motor control Programmable prescaler 16 bits Factor can be changed on the go Each channel is user configurable Input...

Page 308: ...caler Filter TIMERx_CHxCV Register Interrupt Register set and update Interrupt collector and controller APB BUS CK_TIMER CH0_IN CH1_IN CH2_IN CH3_IN CI0 ITI0 ITI1 ITI2 ITI3 ETI CAR Output Logic generation of outputs signals in compare PWM and mixed modes according to initialization software output mask and polarity control CH0_O DMA controller TIMERx_TRGO Interrupt CH1_O CH2_O CH3_O Update Trigger...

Page 309: ...locked by other clock sources selected by theTRGS 2 0 in theTIMERx_SMCFG register and described as follows When the SMC 2 0 bits are set to 0x4 0x5 or 0x6 the internal clock CK_TIMER is the counter prescaler driving clock source Figure 16 30 Timing chart of internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 0...

Page 310: ...k PSC_CK is obtained by the TIMER_CK through the prescaler and the prescale factor can be configured from 1 to 65536 through the prescaler register TIMERx_PSC The new written prescaler value will not take effect until the next update event Figure 16 31 Timing chart of PSC valuechange from 0 to 2 TIMER_CK CEN PSC_CLK CNT_REG Reload Pulse Prescaler CNT Prescaler shadow 94 95 96 97 98 99 0 2 0 2 0 1 ...

Page 311: ...ter are updated Figure 16 32 Timing chart of up counting mode PSC 0 2 show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR 0x99 Figure 16 32 Timing chart of up counting mode PSC 0 2 CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF CNT_REG 96 Update event UPE Update interrupt flag UPIF Hardware set Software ...

Page 312: ... the TIMERx_CAR register to 0 in a count down direction Once the counter reaches to 0 the counter will start counting down from thecounter reload value The update event is generated at each counter underflow The counting direction bit DIR in the TIMERx_CTL0 register should beset to 1 for the down counting mode When the update event is set by the UPG bit in the TIMERx_SWEVGregister the counter valu...

Page 313: ...1 PSC_CLK 2 1 0 99 98 Figure 16 35 Down counter timechart change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 5 4 3 2 1 0 99 98 97 96 95 94 93 92 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 5 4 3 2 1 0 99 1 0 120 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 Auto reload shadow register Hardw...

Page 314: ...SWEVG register will initialize the counter value to 0 irrespective of whether the counter is counting up or down in the center align counting mode and generates an update event The UPIF bit in theTIMERx_INTF register can be set to 1 either when an underflow event or an overflow event occurs While the CHxIF bit is associated with the value of CAM in TIMERx_CTL0 The details refer to Figure 16 36 Tim...

Page 315: ...s or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Channel input capture function Channel input capture function allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital filter a channel polarity selection edge de...

Page 316: ... One more selector is for the other channel and trig controlled by CHxMS The IC_prescaler make several the input event generate one effective capture event On the capture event TIMERx_CHxCV will restore the value of Counter So the process can be divided to several steps as below Step1 Filter Configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and requested signal quality configure c...

Page 317: ... output compare function In channel output compare function the TIMERx can generate timed pulses with programmable position polarity duration and frequency When the counter matches the value in the CHxVAL register of an output compare channel the channel n output can be set cleared or toggled based on CHxCOMCTL when the counter reaches the value in the CHxVAL register the CHxIF bit is set and the ...

Page 318: ...ters Basedonthecountermode wehavecanalsodivide PWM intoEAPWM EdgealignedPWM and CAPWM Centre aligned PWM The EAPWM period is determined by TIMERx_CAR and duty cycle is by TIMERx_CHxCV Figure 16 39 EAPWM timechart shows the EAPWM output and interrupts waveform The CAPWM period is determined by 2 TIMERx_CAR and duty cycle is determined by 2 TIMERx_CHxCV Figure 16 40 CAPWM timechart shows the CAPWM o...

Page 319: ...1 Cx OUT Interrupt signal CHxIF CHxOF CAM 2 b01 downonly CAM 2 b10 up only CHxIF CHxOF CAM 2 b11 up down CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode the OxCPRE signal Channel x Output prepare signal is definedby settingtheCHxCOMCTLfiled TheOxCPREsignalhas several types of output function These include keeping the original level by setting the ...

Page 320: ...l ETI pin and when it is set to a high level by setting the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register The OxCPRE signal will not return to its active level until the next update event occurs Quadrature decoder Refer to Quadrature decoder Hall sensor function Refer to Hall sensor function Master slave management The TIMERx can be synchronized with a trigger in several modes including the res...

Page 321: ...I0 no filter and prescaler can be used Figure 16 41 Restart mode TIMER_CK CEN CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 00 01 02 UPIF ITI0 TRGIF Internal sync delay Exam2 Pause mode The counter can be paused when the trigger input is low TRGS 2 0 3 b10 1 CI0FE0 is the selection TI0S 0 Non xor CH0P 0 no inverted Capture will be sensitive to the rising edge only Filter is bypass in this example Figur...

Page 322: ...tting the CEN bit to 1 usingsoftware SettingtheCENbit to1ora triggerfrom the triggersignals edgecangenerate a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 using software the counter will be stopped and its value held In the single pulse mode the trigger active edge which sets the CEN bit to 1...

Page 323: ...TB then DMA will access the TIMERx_DMATB In fact register TIMERx_DMATB is only a buffer timer will map theTIMERx_DMATB to an internal register appointed by the field of DMATA in TIMERx_DMACFG If the field of DMATC in TIMERx_DMACFG is 0 1 transfer then the timer s DMA request is finished While if TIMERx_DMATC is not 0 such as 3 4 transfers then timer will send 3 more requests to DMA and DMA will ac...

Page 324: ...or TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 Center aligned and counting down assert mode The counter counts under center aligned and channel is configured in output mode CHxMS 00 in TIMERx_CHCTL0 register O...

Page 325: ...DIS Update disable This bit is used to enable or disable the update event generation 0 Update event enable When an update event occurs the corresponding shadow registers are loaded with their preloaded values These events generate update event The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event 1 Update event disable Note When this bit...

Page 326: ...pause mode is high 010 When an update event occurs a TRGO trigger signal is output The update source depends on UPDIS bit and UPS bit 011 When a capture or compare pulse event occurs in chann el0 a TRGO trigger signal is output 100 When a compare event occurs a TRGO trigger signal is output The compare source is from O0CPRE 101 When a compare event occurs a TRGO trigger signal is output The compar...

Page 327: ...me time Note External clock mode 0 enable is in this register s SMC bit filed 13 12 ETPSC 1 0 External trigger prescaler The frequency of external trigger signal ETIFP must not be at higher than 1 4 of TIMER_CK frequency When the external trigger signal is a fast clock the prescaler can be enabled to reduce ETIFP frequency 00 Prescaler disable 01 The prescaler is 2 10 The prescaler is 4 11 The pre...

Page 328: ...output CI0FE0 110 channel 1 input Filtered output CI1FE1 111 External trigger input filter output ETIFP These bits must not be changed when slave mode is enabled 3 Reserved Must be kept at reset value 2 0 SMC 2 0 Slave mode control 000 Disable mode The slave mode is disabled The prescaler is clocked directly by the internal clock TIMER_CK when CEN bit is set high 001 Quadrature decoder mode 0 The ...

Page 329: ...E CH2IE CH1IE CH0IE UPIE rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 15 Reserved Must be kept at reset value 14 TRGDEN Trigger DMA request enable 0 disabled 1 enabled 13 Reserved Must be kept at reset value 12 CH3DEN Channel 3 capture compare DMA request enable 0 disabled 1 enabled 11 CH2DEN Channel 2 capture compare DMA request enable 0 disabled 1 enabled 10 CH1DEN Channel 1 capt...

Page 330: ...ss offset 0x10 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 15 13 Reserved Must be kept at reset value 12 CH3OF Channel 3 over capture flag Refer to CH0...

Page 331: ...er to CH0IF description 2 CH1IF Channel 1 s capture compare interrupt flag Refer to CH0IF description 1 CH0IF Channel 0 s capture compare interrupt flag This flag is set by hardware and cleared by software When channel 0 is in input mode this flag is set when a capture event occurs When channel 0 is in output mode this flag is set when a compare event occurs If Channel0 is set to input mode this b...

Page 332: ...ure or compare event in channel 0 it is automatically cleared by hardware When this bit is set the CH1IF flag is set the corresponding interrupt or DMA request is sent if enabled In addition if channel 1 is configured in input mode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is set if the CH0IF flag was already high 0 No generate a channel 1 capture or ...

Page 333: ...1 is connected to CI0FE1 11 Channel 1 is programmed as input mode IS1 is connected to ITS Note When CH1MS 1 0 11 it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register 7 CH0COMCEN Channel 0 output compare clear enable When this bit is set if the ETIFP signal is detected as high level the O0CPRE signal will be cleared 0 Channel 0 output compare clear disable ...

Page 334: ... enable The PWM mode can be used without verifying the shadow register only in single pulse mode when SPM 1 This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH0MS bit filed is 00 2 CH0COMFEN Channel 0 output compare fast enable When this bit is set the effect of an event on the trigger in input on the capture compare output will be accelerated if the channel is...

Page 335: ...ing capacity configured by this bit it is considered to be an effective level The filtering capability configuration is as follows CH0CAPFLT 3 0 Times fSAMP 4 b0000 Filter disabled 4 b0001 2 fCK_TIMER 4 b0010 4 4 b0011 8 4 b0100 6 fDTS 2 4 b0101 8 4 b0110 6 fDTS 4 4 b0111 8 4 b1000 6 fDTS 8 4 b1001 8 4 b1010 5 fDTS 16 4 b1011 6 4 b1100 8 4 b1101 5 fDTS 32 4 b1110 6 4 b1111 8 3 2 CH0CAPPSC 1 0 Chan...

Page 336: ...CH0COMFEN description 9 8 CH3MS 1 0 Channel 3 mode selection This bit field specifies the direction of the channel and the input signal selection This bit field is writable only when the channel is not active CH3EN bit in TIMERx_CHCTL2 register is reset 00 Channel 3 is programmed as output mode 01 Channel 3 is programmed as input mode IS3 is connected to CI3FE3 10 Channel 3 is programmed as input ...

Page 337: ... when the counter is larger than TIMERx_CH2CV and low otherwise If configured in PWM mode the O2CPRE level changes only when the output compare mode is adjusted from Timing mode to PWM mode or the comparison result changes This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH2MS bit filed is 00 COMPARE MODE 3 CH2COMSEN Channel 2 compare output shadow enable When ...

Page 338: ...to CH0CAPFLT description 11 10 CH3CAPPSC 1 0 Channel 3 input capture prescaler Refer to CH0CAPPSC description 9 8 CH3MS 1 0 Channel 3 mode selection Same as Output compare mode 7 4 CH2CAPFLT 3 0 Channel 2 input capture filter control The CI2 input signal can be filtered by digital filter and this bit field configure the filtering capability Basic principle of digital filter continuouslysample the ...

Page 339: ... be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH3P CH3EN Reserved CH2P CH2EN Reserved CH1P CH1EN Reserved CH0P CH0EN rw rw rw rw rw rw rw rw Bits Fields Descriptions 15 14 Reserved Must be kept at reset value 13 CH3P Channel 3 capture compare function polarity Refer to CH0P description 12 CH3EN Channel 3 capture compare function enable Refer to CH0E...

Page 340: ... TIMERx_CCHP register is 11 or 10 0 CH0EN Channel 0 capture compare function enable When channel 0 is configured in output mode setting this bit enables CH0_O signal in active state When channel 0 is configured in input mode setting this bit enables the capture event in channel0 0 Channel 0 disabled 1 Channel 0 enabled Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 This registe...

Page 341: ...hen the timer is configured in input capture mode this register must be configured a non zero value such as 0xFFFF which is larger than user expected value Channel 0 capture compare value register TIMERx_CH0CV Address offset 0x34 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 15 0 CH0...

Page 342: ...ry update event Channel 2 capture compare value register TIMERx_CH2CV Address offset 0x3C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2VAL 15 0 rw Bits Fields Descriptions 15 0 CH2VAL 15 0 Capture or compare value of channel 2 When channel 2 is configured in input mode this bit filed indicates the counter value corresp...

Page 343: ...4 3 2 1 0 Reserved DMATC 4 0 Reserved DMATA 4 0 rw rw Bits Fields Descriptions 15 14 Reserved Must be kept at reset value 12 8 DMATC 4 0 DMA transfer count This filed defines the number n of the register that DMA will access R W n DMATC 4 0 1 DMATC 4 0 is from 5 b0_0000 to 5 b1_0001 7 5 Reserved Must be kept at reset value 4 0 DMATA 4 0 DMA transfer access start address This filed define the first...

Page 344: ...C Configuration register TIMERx_CFG Address offset 0xFC Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL Reserved rw Bits Fields Descriptions 15 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxVAL register selection This bit field set and reset by software 1 If write the CHxVAL register the write valu...

Page 345: ...but there may be synchronized to provide a larger timer with their counters incrementing in unison 16 3 2 Characteristics Total channel num 2 Counter width 16 bits Source of count clock is selectable internal clock internal trigger external input counter mode count up only Programmable prescaler 16 bit Factor can be changed on the go Each channel is user configurable Input capture mode Output comp...

Page 346: ...tector Edge selector Prescaler Trigger processor Trigger Selector Counter Counter TIMERx_CHxCV Register Interrupt Register set and update Interrupt collector and controller APB BUS CK_TIMER CH0_IN CH1_IN CI0 ITI0 ITI1 ITI2 ITI3 CAR Output Logic generation of outputs signals in compare PWM and mixed modes according to initialization software output mask and polarity control CH0_O TIMERx_TRGO Interr...

Page 347: ... is clocked by other clock sources selected by theTRGS 2 0 in the TIMERx_SMCFG register and described as follows When the SMC bits are set to 0x4 0x5 or 0x6 the internal clock CK_TIMER is the counter prescaler driving clock source Figure 16 46 Timing chart of internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04...

Page 348: ...ad value which is defined in the TIMERx_CAR register in a count up direction Once the counter reaches the counter reload value the counter will start counting up from 0 again The update event is generated at each counter overflow The counting direction bit DIR in the TIMERx_CTL1 register should be set to 0 for the up counting mode When the update event is set by the UPG bit in the TIMERx_SWEVGregi...

Page 349: ... 8 PSC_CLK 97 98 99 0 1 Figure 16 49 Timing chart of up counting mode change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 ...

Page 350: ...input captureprinciple CI0 Synchronizer D presclare Capture Register CH0VAL Clock Processer Counter TIMER_CK Q Filter D Q D Q Edge Detector CI1FE0 ITS CH0MS CH0IF CH0IE CH0_CC_I TIMERx_CC_INT Capture INT From Other Channal CH0CAPPSC Edge selector inverter Based on CH0P CH0NP CI0FE0 Rising Falling ITI0 ITI3 ITI1 ITI2 CI0FED Rising Falling IS0 CI0FED First the channel input signal CIx is synchronize...

Page 351: ...nel control register TIMERx_CHCTL0 and set capture on risingedge Select channel 1 capture signal to CI0 by setting CH1MS to 2 b10 in the channel control register TIMERx_CHCTL0 and set capture on falling edge The counter set to restart mode and restart on channel 0 rising edge Then the TIMERX_CH0CV can measure the PWM period and theTIMERx_CH1CV can measure the PWM duty Channel output compare functi...

Page 352: ...etting the CHxCOMCTL bits to 3 b110 PWM mode0 or to 3 b 111 PWM mode1 the channel can outputs PWM waveform according to the TIMERx_CAR registers andTIMERx_CHxCV registers Basedonthecountermode wehavecanalsodividePWM intoEAPWM EdgealignedPWM and CAPWM Centre aligned PWM The EAPWM period is determined by TIMERx_CAR and duty cycleis by TIMERx_CHxCV Figure 16 52 EAPWM timechart shows the EAPWM output ...

Page 353: ...chart 0 CHxVAL CAR PWM MODE0 PWM MODE1 Cx OUT Cx OUT Interrupt signal CHxIF CHxOF Figure 16 53 CAPWM timechart 0 CHxVAL CAR PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF CAM 2 b01 down only CAM 2 b10 up only CHxIF CHxOF CAM 2 b11 up down CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode the OxCPRE signal Channel ...

Page 354: ...x05 Here the output can be forced to an inactive active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values Master slave management TheTIMERx canbesynchronizedwithatriggerinseveral modes includingtheRestart mode the Pause mode and the Event mode which is selected by the SMC 2 0 in the TIMERx_SMCFGregister The trigger input of these modes can be selected b...

Page 355: ...nter can be paused when the trigger input is low TRGS 2 0 3 b101 CI0FE0 is the selection CH0P 0 no inverted Capture will be sensitive to the rising edge only Filter is bypass in this example Figure 16 55 Pause mode TIMER_CK CEN CNT_REG 94 95 96 97 98 CI0 TRGIF CI0FE0 99 Exam3 Event mode The counter will start to count when a rising trigger input TRGS 2 0 3 b10 1 CI0FE0 is the selection CH0P 0 no i...

Page 356: ...the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 using software the counter will be stopped and its value held In the single pulse mode the trigger active edge which sets the CEN bit to 1 will enable the counter However there exist several clock delays to perform the comparison result between the counter value and t...

Page 357: ..._CAR 99 TIMER_CK PSC_CLK CEN CNT_REG 0 1 2 3 4 5 98 99 00 OxCPRE CI1 Under SPM counter stop Timers interconnection Refer to Advanced timer TIMERx x 0 7 Timer debug mode When theCortex M4halted andtheTIMERx_HOLDconfigurationbit inDBG_CTL0 register set to 1 the TIMERx counter stops ...

Page 358: ... DTS 00 fDTS fCK_TIMER 01 fDTS fCK_TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 4 Reserved Must be kept at reset value 3 SPM Single pulse mode 0 Single pulse mode disable The counter continues after update event 1 Single pulse mode enable The counter coun...

Page 359: ...bit must be set by software when timer works in external clock pause mode and encoder mode Slave mode configuration register TIMERx_SMCFG Address offset 0x08 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MSM TRGS 2 0 Reserved SMC 2 0 rw rw rw rw Bits Fields Descriptions 15 8 Reserved Must be kept at reset value 7 ...

Page 360: ...nter clock when it is high and disables the counter clock when it is low 110 Event mode A rising edge of the trigger input enables the counter 111 External clock mode0 The counter counts on the rising edges of the selected trigger Interrupt enable register TIMERx_DMAINTEN Address offset 0x0C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7...

Page 361: ...apture event occurs while CH0IF flag has already been set This flag is cleared by software 0 No over capture interrupt occurred 1 Over capture interrupt occurred 8 7 Reserved Must be kept at reset value 6 TRGIF Trigger interrupt flag This flag is set on trigger event and cleared by software When in pause mode both edges on trigger input generates a trigger event otherwise onlyan active edge on tri...

Page 362: ...omatically When this bit is set the TRGIF flag in TIMERx_STAT register is set related interrupt or DMA transfer can occur if enabled 0 No generate a trigger event 1 Generate a trigger event 5 3 Reserved Must be kept at reset value 2 CH1G Channel 1 s capture or compare event generation Refer to CH0G description 1 CH0G Channel 0 s capture or compare event generation This bit is set by software in or...

Page 363: ...ion 10 CH1COMFEN Channel 1 output compare fast enable Refer to CH0COMFEN description 9 8 CH1MS 1 0 Channel 1 mode selection This bit field specifies the direction of the channel and the input signal selection This bit field is writable only when the channel is not active CH1EN bit in TIMERx_CHCTL2 register is reset 00 Channel 1 is programmed as output mode 01 Channel 1 is programmed as input mode ...

Page 364: ... mode to PWM mode or the comparison result changes This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH0MS bit filed is 00 COMPARE MODE 3 CH0COMSEN Channel 0 compare output shadow enable When this bit is set the shadow register of TIMERx_CH0CV register which updates at each update event will be enabled 0 Channel 0 output compare shadow disable 1 Channel 0 output...

Page 365: ... mode 7 4 CH0CAPFLT 3 0 Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit field configure the filtering capability Basic principle of digital filter continuouslysample the CI0 input signal according to fSAMP and record the number of times of the same level of the signal After reaching the filtering capacity configured by this bit it is consi...

Page 366: ... 8 Reserved Must be kept at reset value 7 CH1NP Channel 1 complementary output polarity Refer to CH0NP description 6 Reserved Must be kept at reset value 5 CH1P Channel 1 capture compare function polarity Refer to CH0P description 4 CH1EN Channel 1 capture compare function enable Refer to CH1EN description 3 CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode ...

Page 367: ... CH0EN Channel 0 capture compare function enable When channel 0 is configured in output mode setting this bit enables CH0_O signal in active state When channel 0 is configured in input mode setting this bit enables the capture event in channel0 0 Channel 0 disabled 1 Channel 0 enabled Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 This register can be accessed by half word 16 b...

Page 368: ...hen the timer is configured in input capture mode this register must be configured a non zero value such as 0xFFFF which is larger than user expected value Channel 0 capture compare value register TIMERx_CH0CV Address offset 0x34 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 15 0 CH0...

Page 369: ... is configured in output mode this bit filed contains value to be compared to the counter When the corresponding shadow register is enabled the shadow register updates every update event Configuration register TIMERx_CFG Address offset 0xFC Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL Reserved rw Bits Fiel...

Page 370: ...er In addition the general level2 timers can be programmed and be used to count or time external events that drive otherTimers 16 4 2 Characteristics Total channel num 1 Counter width 16bit Source of count clock internal clock Counter mode count up only Programmable prescaler 16 bit Factor can be changed on the go Each channel is user configurable Input capture mode output compare mode programmabl...

Page 371: ...rigger processor Trigger Selector Counter Counter TIMERx_CHxCV Register Interrupt Register set and update Interrupt collector APB BUS CK_TIMER CH0_IN CI0 CAR Output Logic generation of outputs signals in compare PWM and mixed modes according to initialization software output mask and polarity control CH0_O TIMERx_TRGO Interrupt Update Trigger Cap Com PSC TIMER_CK PSC_CLK ...

Page 372: ... to generate PSC_CLK The TIMER_CK driven counter s prescaler to count is equal to CK_TIMER which is from RCU Figure 16 59 Timing chart of internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 06 07 Update event UPE Clock prescaler The counter clock PSC_CK is obtained by the TIMER_CK through the prescaler and ...

Page 373: ...er will start counting up from 0 again The update event is generated at each counter overflow The counting direction bit DIR in the TIMERx_CTL1 register should be set to 0 for the up counting mode When the update event is set by the UPG bit in the TIMERx_SWEVGregister the counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update...

Page 374: ... 8 PSC_CLK 97 98 99 0 1 Figure 16 62 Timing chart of up counting mode change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 ...

Page 375: ... Channels input captureprinciple CI0 Synchronizer D presclare Capture Register CH0VAL Clock Processer Counter TIMER_CK Q Filter D Q D Q Edge Detector CI1FE0 ITS CH0MS CH0IF CH0IE CH0_CC_I TIMERx_CC_INT Capture INT From Other Channal CH0CAPPSC Edge selector inverter Based on CH0P CH0NP CI0FE0 Rising Falling ITI0 ITI3 ITI1 ITI2 CI0FED Rising Falling IS0 CI0FED First the channel input signal CIx is s...

Page 376: ...on risingedge Select channel 1 capture signal to CI0 by setting CH1MS to 2 b10 in the channel control register TIMERx_CHCTL0 and set capture on falling edge The counter set to restart mode and restart on channel 0 rising edge Then the TIMERX_CH0CV can measure the PWM period and theTIMERx_CH1CV can measure the PWM duty Channel output compare function In channel Compare function the TIMERx can gener...

Page 377: ...OMCTL field to 0x01 set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of theTIMERx_CHxCV register The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTLfield to 0x06 0x07 In these modes the OxCPRE signal level is changed according to the cou...

Page 378: ...03xx UserManual 378 Timers interconnection Refer to Advanced timer TIMERx x 0 7 Timer debug mode When theCortex M4halted andtheTIMERx_HOLDconfigurationbit inDBG_CTL0 register set to 1 the TIMERx counter stops ...

Page 379: ...y software to specify division factor between the CK_TIMER and the dead time and digital filter sample clock DTS 00 fDTS fCK_TIMER 01 fDTS fCK_TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 3 Reserved Must be kept at reset value 2 UPS Update source This bit...

Page 380: ...gister 1 TIMERx_CTL1 Address offset 0x04 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MMC 2 0 Reserved rw Bits Fields Descriptions 15 8 Reserved Must be kept at reset value 7 Reserved Must be kept at reset value 6 4 MMC 2 0 Master mode control These bits control the selection of TRGO signal which is sent in maste...

Page 381: ...be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0IE UPIE rw rw Bits Fields Descriptions 15 2 Reserved Must be kept at reset value 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabled 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 This register can be ac...

Page 382: ... 1 Update interrupt occurred Software event generation register TIMERx_SWEVG Address offset 0x14 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0G UPG w w Bits Fields Descriptions 15 2 Reserved Must be kept at reset value 1 CH0G Channel 0 s capture or compare event generation This bit is set by software in order ...

Page 383: ...l output O0CPRE signal is forced high when the counter is equals to the output compare register TIMERx_CH0CV 010 Clear the channel output O0CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH0CV 011 Toggle on match O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV 100 Force low O0CPRE is forced to low level 101 Force hig...

Page 384: ...CH0MS 1 0 Channel 0 I O mode selection This bit field specifies the work mode of the channel and the input signal selection This bit field is writable only when the channel is not active CH0EN bit in TIMERx_CHCTL2 register is reset 00 Channel 0 is programmed as output mode 01 Channel 0 is programmed as input mode IS0 is connected to CI0FE0 10 Channel 0 is programmed as input mode IS0 is connected ...

Page 385: ... 10 The input capture occurs on every 4 channel input edges 11 The input capture occurs on every 8 channel input edges 1 0 CH0MS 1 0 Channel 0 mode selection Same as output compare mode Channel control register 2 TIMERx_CHCTL2 Address offset 0x20 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0NP Reserved CH0P CH...

Page 386: ...gger operation in slave mode And CIxFE0 will not be inverted CH0NP 0 CH0P 1 CIxFE0 s falling edge is the active signal for capture or trigger operation in slave mode And CIxFE0 will be inverted CH0NP 1 CH0P 0 Reserved CH0NP 1 CH0P 1 Reserved This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 or 10 0 CH0EN Channel 0 capture compare function enable When channel 0 is co...

Page 387: ...ter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 15 0 CARL 15 0 Counter auto reload value This bit filed specifies the auto reload value of the counter Note When the timer is configured in input capture mode this register must be con...

Page 388: ...sponding shadow register is enabled the shadow register updates every update event Configuration register TIMERx_CFG Address offset 0xFC Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL Reserved rw Bits Fields Descriptions 15 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxVAL register selection This ...

Page 389: ...e 16 65 Basic timer block diagram provides details on the internal configuration of the basic timer Figure 16 65 Basic timer block diagram PSC Trigger processor Trigger Selector Counter Counter Register Interrupt Register set and update Interrupt collector APB BUS CK_TIMER CAR TIMERx_TRGO Interrupt Update UPIE TIMER_CK PSC_CLK DMA controller DMA REQ ACK TIMERx_UP 16 5 4 Function overview Clock sou...

Page 390: ...unter clock PSC_CK is obtained by the TIMER_CK through the prescaler and the prescale factor can be configured from 1 to 65536 through the prescaler register TIMERx_PSC The new written prescaler value will not take effect until the next update event Figure 16 67 Timing chart of PSC valuechange from 0 to 2 TIMER_CK CEN PSC_CLK CNT_REG Reload Pulse Prescaler CNT Prescaler shadow 94 95 96 97 98 99 0 ...

Page 391: ...the TIMERx_SWEVGregister the counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update event occurs all the shadow registers counter auto reload register prescaler register are updated The following figures show some examples of the counter behavior for different clock prescaler factor whenTIMERx...

Page 392: ... ARSE 1 Single pulse mode Single pulse mode is opposite to the repetitive mode which can be enabled by setting SPM inTIMERx_CTL0 Whenyouset SPM thecounterwill beclearandstopwhenthenext update event Once the timer is set to operate in the single pulse mode it is necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter then the CEN bit keeps at a high state un...

Page 393: ...ble The counter continues after update event 1 Single pulse mode enable The counter counts until the next update event occurs 2 UPS Update source This bit is used to select the update event sources by software 0 These events generate update interrupts or DMA requests The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event 1 This event gene...

Page 394: ...at reset value 6 4 MMC 2 0 Master mode control These bits control the selection of TRGO signal which is sent in master mode to slave timers for synchronization function 000 When a counter reset event occurs a TGRO trigger signal is output The counter resert source Master timer generate a reset the UPG bit in the TIMERx_SWEVG register is set 001 Enable When a conter start event occurs a TGRO trigge...

Page 395: ...Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UPIF rc_w0 Bits Fields Descriptions 15 1 Reserved Must be kept at reset value 0 UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software 0 No update interrupt occurred 1 Update interrupt occurred Software event generation regist...

Page 396: ... 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 15 0 CNT 15 0 This bit filed indicates the current counter value Writing to this bit filed can change the value of the counter Prescaler register TIMERx_PSC Address offset 0x28 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 15 0 PSC 15 0 Pres...

Page 397: ...ister can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 15 0 CARL 15 0 Counter auto reload value This bit filed specifies the auto reload value of the counter ...

Page 398: ...ware flow control protocol CTS RTS The data frame can be transferred from LSB or MSB bit The polarity of the data bits and theTX RX pins can be configured independently and flexibly The USART supports DMA function for high speed data communication except UART4 17 2 Characteristics NRZ standard format Asynchronous full duplex communication Programmable baud rate generator Divided from the periphera...

Page 399: ...lock EBF and receiver timeout RTF Interrupt occurs at these events when the corresponding interrupt enable bits are set While USART0 1 2 is fully implemented UART3 4 is only partially implemented with the following features not supported Smartcard mode Synchronous mode Hardware flow control protocol CTS RTS Configurable data polarity 17 3 Function overview The interface is externally connected to ...

Page 400: ... data frame is configured by the WL bit in the USART_CTL0 register The last data bit can be used as parity check bit by setting the PCEN bit of in USART_CTL0 register When the WL bit is reset the parity bit is the 7th bit When the WL bit is set the parity bit is the 8th bit Themethodof calculatingtheparity bit is selectedby thePM bit inUSART_CTL0register Figure 17 2 USART character frame 8 bits da...

Page 401: ... USARTDIV has the following relationship with the UCLK USARTDIV UCLK 16 Baud Rate 16 1 For example when oversampled by 16 1 Get USARTDIV by caculating the value of USART_BUAD If USART_BUAD 0x21D then INTDIV 33 0x21 FRADIV 13 0xD USARTDIV 33 13 16 33 81 2 Get the value of USART_BUAD by calculating the value of USARTDIV If USARTDIV 30 37 then INTDIV 30 0x1E 16 0 37 5 92 the nearest integer is 6 so F...

Page 402: ... bits length 3 Set the STB 1 0 bits in USART_CTL1 to configure the number of stopbits 4 Enable DMA DENT bit in USART_CTL2 if multibuffer communication is selected 5 Set the baud rate in USART_BAUD 6 Set theTEN bit in USART_CTL0 7 Wait for theTBE to be asserted 8 Write the data to the USART_DATA register 9 Repeat step7 8 for each data if DMA is not enabled 10 Wait until TC 1 to finish Figure 17 3 U...

Page 403: ...re samples of a frame bit is 0 the frame bit is confirmed as a 0 else 1 If the value of the three samples of any bit are not the same whatever it is a start bit data bit parity bit or stop bit a noisy error NERR will be generated for the frame An interrupt is generated if the receive DMA is enabled and the ERRIE bit in USART_CTL2 register is set Figure 17 4 Receiving a frame bit by oversampling me...

Page 404: ...eivingdatabuffer TheDENT bit inUSART_CTL2is usedtoenabletheDMAtransmission and the DENR bit in USART_CTL2 is used to enable the DMA reception When DMA is used for USART transmission DMA transfers data from internal SRAM to the transmit data buffer of the USART The configuration steps are shown in Figure 17 5 Configuration step when using DMA for USART transmission Figure 17 5 Configuration step wh...

Page 405: ...guration steps when using DMAfor USART reception Set the address of USART_DATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA interrupt enable priority etc Enable the DMA channel for USART When the number of the data received by USART reaches the DMA transfer n...

Page 406: ...er a data frame can be transmitted If theTBE bit in USART_STAT0 is 0 and the nCTS signal is low the transmitter transmits the data frame When the nCTS signal goes high during a transmission the transmitter stops after the current transmission is accomplished Figure 17 8 Hardware flow control nCTS RX CTS follow control TX start data2 start data3 stop stop data1 stop start data1 start data2 stop sto...

Page 407: ...TL1 register the hardware sets the RWU bit and enters mute mode automatically In this situation the RBNE bit is not set If the address match method is selected the receiver does not check the parity value of an address frame by default If the PCEN bit in USART_CTL0 is set the MSB bit will be checked as the parity bit and the bit precedingthe MSB bit is detectedas the address flag 17 3 8 LIN mode T...

Page 408: ...itter and can be only activated when the TEN bit is enabled No clock pulse will be sent through the CK pin during the transmission of the start bit and stop bit The CLEN bit in USART_CTL1 can be used to determine whether the clock is output or not during the last address flag bit transmission The CPH bit in USART_CTL1 can be used to determine whether data is captured on the first or the second clo...

Page 409: ...t encoder and transmitted to theinfrared LED through theTX pin The SIR receive decoder receives the modulated signal from the infrared LED through the RX pin and puts the demodulated data frametotheUSART receiver Thebaudrateshouldnot belargerthan115200 forthe encoder Figure 17 13 IrDA SIR ENDEC module Normal USART Transmit Encoder Receive Decoder SIR MODULE TX RX TX pin RX pin IREN 1 0 0 1 Infrare...

Page 410: ...plex communication mode In the half duplex mode the receive line is internally connected totheTX pin and the RX pin is no longer used TheTX pin should be configured as output open drain mode The software should make sure that the transmissionand reception process never conflict with each other 17 3 12 Smartcard ISO7816 3 mode The smartcard mode is an asynchronous mode whichis designed to support t...

Page 411: ... inserted before the start of a resented frame At the end of the last repeated character the TC bit is set immediately without guard time The USART will stop transmitting and assert the framing error status if it still receives the NACK signal after the programmed number of retries The USART will not take the NACK signal as the start bit During USART reception if the parity error is detected in th...

Page 412: ...tus EBF bit in USART_STAT1 is set after the block length counter reaches the maximum value An interrupt is generated if the EBIE bit in USART_CTL3 is set The RTF bit may be set in case that an error in the block length If DMA is used for reception this register field must be programmed to the minimum value 0x0 before the start of the block With this value the end of the block interrupt occurs afte...

Page 413: ...CTL1 LBDIE Receiver timeout RTF USART_CTL3 RTIE End of block EBF USART_CTL3 EBIE Reception errors noise flag overrun error framing error in DMA reception NERR or ORERR or FERR USART_CTL2 ERRIE All of the interrupt events are ORed together before being sent to the interrupt controller so the USART can only generate a single interrupt request to the controller at any given time Software can service ...

Page 414: ...et by hardware when the nCTS input toggles An interrupt occurs if the CTSIE bit in USART_CTL2 is set Software can clear this bit by writing 0 to it 0 The status of the nCTS line does not change 1 The status of the nCTS line has changed This bit is not available for UART3 4 8 LBDF LIN break detected flag LMEN bit in USART_CTL1 is set when LIN break is detected An interrupt occurs if the LBDIE bit i...

Page 415: ...L0 is set Software can clear this bit by reading the USART_STAT0 and USART_DATA registers one by one 0 The USART module does not detect an IDLE frame 1 The USART module has detected an IDLE frame 3 ORERR Overrun error This bit is set if the RBNE is not cleared and a new data frame is received through the receive shift register An interrupt occurs if the ERRIE bit in USART_CTL2 is set Software can ...

Page 416: ...to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DATA 8 0 rw Bits Fields Descriptions 31 9 Reserved Must be kept the reset value 8 0 DATA 8 0 Transmit or read data value Software can write these bits to update the transmit data or read these bits to get the receive data If the parity check function is enabled when...

Page 417: ... 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UEN WL WM PCEN PM PERRIE TBEIE TCIE RBNEIE IDLEIE TEN REN RWU SBKCMD rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 14 Reserved Must be kept the reset value 13 UEN USART enable 0 USART disabled 1 USART enabled 12 WL Word length 0 8 Data bits 1 9 Data bits 11 WM Wakeup method in mute mode 0 wake up by ...

Page 418: ...1 Read data register not empty interrupt and overrun error interrupt enabled 4 IDLEIE IDLE line detected interrupt enable If this bit is set an interrupt occurs when the IDLEF bit in USART_STAT0 is set 0 IDLE line detected interrupt disabled 1 IDLE line detected interrupt enabled 3 TEN Transmitter enable 0 Transmitter is disabled 1 Transmitter is enabled 2 REN Receiver enable 0 Receiver is disable...

Page 419: ... 1 0 STOP bits length 00 1 Stop bit 01 0 5 Stop bit 10 2 Stop bits 11 1 5 Stop bit Only 1 stop bit and 2 stop bits are available for UART3 4 11 CKEN CK pin enable 0 CK pin disabled 1 CK pin enabled This bit is reserved for UART3 4 10 CPL CK polarity This bit specifies the polarity of the CK pin in synchronous mode 0 The CK pin is in low state when the USART is in idle state 1 The CK pin is in high...

Page 420: ... value 3 0 ADDR 3 0 Address of the USART In wake up by address match mode WM 1 the USART enters mute mode when the LSB 4 bits of a received frame do not equal the ADDR 3 0 bits and wakes up when the LSB 4 bits of a received frame equal the ADDR 3 0 bits 17 4 6 Control register 2 USART_CTL2 Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26...

Page 421: ...r reception 1 DMA request is enabled for reception 5 SCEN Smartcard mode enable This bit enables the smartcard work mode 0 Smartcard Mode disabled 1 Smartcard Mode enabled This bit is reserved for UART3 4 4 NKEN NACK enable in smartcard mode This bit enables the NACK transmission when parity error occurs in smartcard mode 0 Disable NACK transmission 1 Enable NACK transmission This bit is reserved ...

Page 422: ...is delayed by GUAT 7 0 baud clock cycles These bits are not available for UART3 4 7 0 PSC 7 0 When the USART IrDA low power mode is enabled these bits specify the division factor that is used to divide the peripheral clock PCLK1 PCLK2 to generate the low power frequency 00000000 Reserved never program this value 00000001 divides by 1 00000010 divides by 2 11111111 divides by 255 When the USART wor...

Page 423: ...0 DINV Data bit level inversion This bit specifies the polarity of the data bits in transmission and reception 0 Data bit signal values are not inverted 1 Data bit signal values are inverted This bit field cannot be written when the USART is enabled UEN 1 9 TINV TX pin level inversion This bit specifies the polarity of the TX pin 0 TX pin signal values are not inverted 1 TX pin signal values are i...

Page 424: ...r timeout enable This bit enables the receive timeout counter of the USART 0 Receiver timeout function disabled 1 Receiver timeout function enabled 17 4 9 Receiver timeout register USART_RT Address offset 0x84 Reset value 0x0000 0000 This register is not available for UART3 4 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BL 7 0 RT 23 16 rw rw 15 14...

Page 425: ...once per received character 17 4 10 Status register 1 USART_STAT1 Address offset 0x88 Reset value 0x0000 0000 This register is not available for UART3 4 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BSY r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EBF RTF Reserved w0 w0 Bits Fields Descriptions 31 17 Reserved Must be kept the reset val...

Page 426: ...e RX pin is in idle state for longer than RT bits time An interrupt occurs if the RTIE bit in USART_CTL3 is set Software can clear this bit by writing 0 to it 0 Receiver timeout event does not occur 1 Receiver timeout event has occurred 10 0 Reserved Must be kept the reset value ...

Page 427: ...rface provides DMA mode for users to reduce CPU overload 18 2 Characteristics Parallel bus to I2C bus protocol conversion and interface Both master and slave functions with the sameinterface Bi directional data transfer between master and slave Supports 7 bit and 10 bit addressing and General Call Addressing Multi master capability Supports standard mode up to 100 kHz fast mode up to 400 kHz and f...

Page 428: ...ave The device addressed by a master Multi master More than one master can attempt to controlthe bus at the same time without corrupting the message Synchronization Procedure to synchronize the clock signalsof two or more devices Arbitration Procedure to ensure that if more than one master tries to control the bus simultaneously onlyone is allowed to do so and the winning master s message is not c...

Page 429: ...ing the HIGH period of the clock The HIGH or LOW state of the SDA line can only change when the clock signal on the SCL line is LOW seeFigure18 2 Datavalidation Oneclock pulseis generatedforeachdatabit transferred Figure 18 2 Data validation SDA SCL 18 3 3 START and STOP signal All transmissions begin with a START and are terminated by a STOP see Figure 18 3 START and STOP condition A HIGH to LOWt...

Page 430: ...LK1 CLK2 SCL 18 3 5 Arbitration Arbitration like synchronization is part of the protocol where more than one master is used in the system Slaves are not involved in the arbitration procedure A master may start a transfer only if the bus is free Two masters may generate a START signal withintheminimum holdtimeof theSTARTsignal whichresultsinavalidSTART signal on the bus Arbitration is then required...

Page 431: ...0 ACK DATA0 ACK DATAN ACK Stop data transfer N 1 bytes From master to slave From slave to master R 1 DATA0 ACK DATAN NACK Figure 18 7 I2C communication flowwith 10 bit address Master Transmit Start Slave address byte2 W 0 ACK DATA0 ACK DATAN ACK Stop data transfer N 1 bytes From master to slave From slave to master Slave address byte1 header ACK 1 1 1 1 0 x x Figure 18 8 I2C communication flowwith...

Page 432: ...it again after it detects the repeated START signal and the following header TheADDSEND bit must be cleared by software again by reading I2C_STAT0 and then I2C_STAT1 3 Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty Once TBE is set software should write the first byte of data to I2C_DATA register TBE is not clear...

Page 433: ...A N 1 Master sends Acknowledge Set TBE 7 Clear AERR I2C Line State Hardware Action Software Flow Master sends Header Slave sends Acknowledge Programming model in slave receiving mode As is shown in Figure 18 10 Programming model for slave receiving 10 bit address mode the following software procedure should be followed if users wish to receive data in slave receiver mode 1 First of all enable I2C ...

Page 434: ... DATA 1 Slave sends Acknowledge Data transmission Master sends DATA N Slave sends Acknowledge Master generates STOP condition Set ADDSEND 2 Clear ADDSEND Set RBNE Set STPDET 4 Read DATA x Set RBNE 3 Read DATA 1 5 Read DATA N 6 Clear STPDET I2C Line State Hardware Action Software Flow Set RBNE 1 Software initialization Programming model in master transmitting mode As it shows in Figure 18 11 Progra...

Page 435: ...h the shift register and data register I2C_DATA are empty Software now writes the first byte data to I2C_DATA register but the TBE will not be cleared because the byte written in I2C_DATAis movedtointernal shiftregisterimmediately TheI2Cbegins totransmitdata to I2C bus as soon as the shift register is not empty 6 Duringthetransmissionof the first byte softwarecanwritethesecondbytetoI2C_DATA and th...

Page 436: ... SCL stretched by master 3 Clear SBSEND SCL stretched by master SCL stretched by master Programming model in master receiving mode In master receiving mode a master is responsible for generating NACK for the last byte reception and then sending STOP a condition on I2C bus So special attention should be paid to ensure the correct ending of data reception Two solutions for master receiving are provi...

Page 437: ...ND bit by reading I2C_STAT0 and writing header toI2C_DATA Thentheheaderis sent out toI2Cbus andADDSENDis setagain Software should again clearADDSEND by reading I2C_STAT0 and then I2C_STAT1 5 As soon as the first byte is received RBNE is set by hardware Software now can read the first byte from I2C_DATAand RBNE is cleared as well 6 Any time RBNE is set software can read a byte from I2C_DATA 7 After...

Page 438: ...L stretched by master Master sends Header Slave sends Acknowledge Set ADDSEND 4 Clear ADDSEND SCL stretched by master 6 Read DATA N 1 7 Clear ACKEN Set STOP Solution B 1 First of all enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing After enabled and configured I2C operates in its default slave state and waits for START signal foll...

Page 439: ...is not read out by software so after the N 1 byte is received both BTC and RBNE are asserted The bus is stretched by master to prevent the reception of the last byte Then software should clearACKEN bit 7 Software reads out N 2 byte clearing BTC After this the N 1 byte is moved from shift register to I2C_DATA and bus is released and begins to receive the last byte Master doesn t send anACK for the ...

Page 440: ...dware Action Software Flow 2 Set START Set SBSEND SCL stretched by master 3 Clear SBSEND SCL stretched by master 4 Set START Master generates repeated START condition Set SBSEND 4 Clear SBSEND SCL stretched by master Master sends Header Slave sends Acknowledge Set ADDSEND 4 Clear ADDSEND SCL stretched by master 7 Clear ACKEN Slave sends DATA N 2 Master sends Acknowledge SCL stretched by master Set...

Page 441: ...er for the configuration method of a DMA stream The DMA controller must be configured and enabled before the I2C transfer When the configured number of bytes have been transferred the DMA controller generates End of Transfer EOT interrupt DMA will send an End of Transmission EOT signal to the I2C interface and generates a DMA full transfer finish interrupt When a master receives two or more bytes ...

Page 442: ...ns Dynamic reconfigurationof thehardwareand softwareallows bus devicestobe hot plugged andused immediately without restarting the system The devices are recognized automatically and assigned unique addresses This advantage results in a plug and play user interface In this protocol there is a very useful distinction between a system host and all the other devices in the system that is the host prov...

Page 443: ...should be configured to desired values 2 In order to support address resolution protocol ARP ARPEN 1 the software should respond to HSTSMB flag in SMBus Host Mode SMBSEL 1 or DEFSMB flag in SMBus Device Mode and implement the function of ARP protocol 3 In order to support SMBus Alert Mode thesoftware should respond to SMBALT flag and implement the related function 18 3 12 Status errors and interru...

Page 444: ...GD32F403xx UserManual 444 Error Name Description AERR No acknowledge received PECERR CRC value doesn t match SMBTO Bus timeout in SMBus mode SMBALT SMBus Alert ...

Page 445: ...uld wait until the I2C lines are released to reset the I2C 0 I2C is not reset 1 I2C is reset 14 Reserved Must be kept at reset value 13 SALT SMBus Alert Issue alert through SMBA pin Software can set and clear this bit and hardware can clear this bit 0 Don t issue alert through SMBA pin 1 Issue alert through SMBA pin 12 PECTRANS PEC transfer Software sets and clears this bit while hardware clears t...

Page 446: ...a START condition on I2C bus This bit is set and cleared by software and cleared by hardware when a START condition is detected or I2CEN 0 0 START will not be sent 1 START will be sent 7 DISSTRC SCL stretching Whether to stretch SCL low when data is not ready in slave mode This bit is set and cleared by software 0 SCL stretching is enabled 1 SCL stretching is disabled 6 GCEN Whether or not to resp...

Page 447: ...ext DMA EOT is not the last transfer 1 Next DMA EOT is the last transfer 11 DMAON DMA is mode switched on 0 DMA mode is switched off 1 DMA mode is switched on 10 BUFIE 0 Buffer interrupt is disabled 1 Buffer interrupt is enabled which means that interrupt will be generated when TBE 1 or RBNE 1 if EVIE 1 9 EVIE Event interrupt enable 0 Event interrupt is disabled 1 Event interrupt is enabled which ...

Page 448: ...3 Slave address register 0 I2C_SADDR0 Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDFOR MAT Reserved ADDRESS 9 8 ADDRESS 7 1 ADDRES S0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 ADDFORMAT Address for...

Page 449: ...bled 1 Dual Address mode is enabled 18 4 5 Transfer buffer register I2C_DATA Address offset 0x10 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRB 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 TRB 7 0 Transmission or rece...

Page 450: ...eived PEC matches calculated PEC 1 Received PEC doesn t match the calculated PEC I2C will send NACK careless of ACKEN bit 11 OUERR Over run or under run situation occurs in slave mode when SCL stretching is disabled In slave receiving mode if the last byte in I2C_DATA is not read out while the following byte is already received over run occurs In slave transmitting mode if the current byte is alre...

Page 451: ...TAT0 and then writing I2C_CTL0 0 STOP signal not detected in slave mode 1 STOP signal detected in slave mode 3 ADD10SEND Header of 10 bit address is sent in master mode This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA 0 No header of 10 bit address is sent in master mode 1 Header of 10 bit address is sent in master mode 2 BTC Byte transmission is completed If a byte...

Page 452: ... 7 6 5 4 3 2 1 0 PECV 7 0 DUMODF HSTSMB DEFSMB RXGC Reserved TR I2CBSY MASTER r r r r r r r r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 8 PECV 7 0 Packet Error Checking value that calculated by hardware when PEC is enabled 7 DUMODF Dual flag in slave mode indicates which address matches with the address in Dual Address mode This bit is cleared by hardware after a STOP ...

Page 453: ...n active 0 MASTER A flag indicating whether I2C block is in master or slave mode This bit is set by hardware when a START signal generates This bit is cleared by hardware after a STOP signal or I2CEN 0 or LOSTARB 1 0 Slave mode 1 Master mode 18 4 8 Clock configure register I2C_CKCFG Address offset 0x1C Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 2...

Page 454: ... 4 9 Rise time register I2C_RT Address offset 0x20 Reset value 0x0000 0002 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RISETIME 6 0 rw Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 0 RISETIME 6 0 Maximum rise time in master mode The RISETIME value shou...

Page 455: ...rManual 455 Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 FMPEN Fast mode plus enable The I2C device supports up to 1MHz when this bit is set 0 Fast mode plus disabled 1 Fast mode plus enabled ...

Page 456: ...aracteristics Master or slave operation with full duplex or simplex mode Separate transmit and receive buffer 16 bits wide Data frame size can be 8 or 16 bits Bit order can be LSB first or MSB first Software and hardware NSS management Hardware CRC calculation transmission and checking Transmission and reception using DMA SPI TI mode supported SPI NSS pulse mode supported Quad SPI configuration av...

Page 457: ...irection Description SCK I O Master SPI clock output Slave SPI clock input MISO I O Master data reception line Slave data transmission line Master with bidirectional mode not used Slave with bidirectional mode data transmission and reception line MOSI I O Master data transmission line Slave data reception line Master with bidirectional mode data transmission and reception line Slave with bidirecti...

Page 458: ... 19 2 Quad SPI signal description Pin Name Direction Description SCK O SPI Clock Output MOSI I O Transmission or Reception Data 0 line MISO I O Transmission or Reception Data 1 line IO2 I O Transmission or Reception Data 2 line IO3 I O Transmission or Reception Data 3 line NSS O NSS output 19 3 3 SPI clock timing and data format CKPL and CKPH bits in SPI_CTL0 register decide the timing of SPI cloc...

Page 459: ...er is fixed to MSB first inTI mode 19 3 4 NSS function Slave Mode When slave mode is configured MSTMOD 0 SPI gets NSS level from NSS pin in hardware NSS mode SWNSSEN 0 or from SWNSS bit in software NSS mode SWNSSEN 1 and transmits receives data only when NSS level is low In software NSS mode NSS pin is not used Table 19 3 NSS function in slave mode Mode Register configuration Description Slave har...

Page 460: ... the SPI slave device At this time the NSS is configured as the hardware output mode NSS goes low after enabling SPI Master hardware NSS input mode MSTMOD 1 SWNSSEN 0 NSSDRV 0 Applicable to multi master mode At this time NSS is configured as hardware input mode Once the NSS pin is pulled low SPI will automatically enter slave mode and a master configuration errorwill occur and the CONFERR bit will...

Page 461: ...eception with bidirectional connection MSTMOD 1 RO 0 BDEN 1 BDOEN 0 MOSI Reception MISO Not used SFD Slave Full Duplex MSTMOD 0 RO 0 BDEN 0 BDOEN Don t care MOSI Reception MISO Transmission STU Slave Transmission with unidirectionalconnection MSTMOD 0 RO 0 BDEN 0 BDOEN Don t care MOSI Not used MISO Transmission SRU Slave Reception with unidirectionalconnection MSTMOD 0 RO 1 BDEN 0 BDOEN Don t care...

Page 462: ... simplex connection Master Receive Slave Transmit Master MRU MISO MOSI SCK NSS Slave STU MISO MOSI SCK NSS Figure 19 6 A typical simplex connection Master Transmit only Slave Receive Master MTU MISO MOSI SCK NSS Slave SRU MISO MOSI SCK NSS Figure 19 7 A typical bidirectional connection Master MTB MRB MISO MOSI SCK NSS Slave SRB STB MISO MOSI SCK NSS ...

Page 463: ...uence After the initialization sequence the SPI is enabled and stays at idle state In master mode the transmission starts when the application writes a data into the transmit buffer In slave mode the transmission starts when SCK clock signal begins to toggle at SCK pin and NSS level is low soapplicationshouldensurethatdatais already writtenintotransmit bufferbefore the transmission starts in slave...

Page 464: ...until the SPI is disabled So the application should ignore the TBE flag and read out reception buffer in time after the RBNE flag is set otherwise a data overrun fault will occur Theslavereceptionmode SRUorSRB is similartofull duplex mode exceptthat application should ignore theTBE flag and only perform reception sequence described above SPI TI mode SPI TI mode takes NSS as a special frame header ...

Page 465: ...2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SCK NSS MOSI MISO sample Td In SlaveTI mode after the last rising edge of SCK in transfer the slave begins to transmit the LSB bit of the last data byte and after a half bit time the master begins to sample the line To make sure that the master samples the right value the slave should continue to drive this bit after the falling sample edge of SCK for a pe...

Page 466: ...d SPI mode BDEN BDOEN CRCEN CRCNT FF16 RO and LF in SPI_CTL0 register should be kept cleared and MSTMOD should be set to ensure that SPI is in master mode SPIEN PSC CKPL and CKPH should be configured as desired There are 2 operation modes in Quad SPI mode quad write and quad read decided by QRD bit in SPI_QCTL register Quad write operation SPI works in quad write mode when QMOD is set and QRD is c...

Page 467: ...only to generate SCK clocks so the written data can be any value Once SPI starts transmission it always checks SPIEN andTBE status at the end of a frame and stops when condition is not met So software should always write dummy data into SPI_DATA to makeSPI generate SCK The operation flow for receiving in quad mode 1 Configure clock prescaler clock polarity phase etc in SPI_CTL0 and SPI_CTL1 regist...

Page 468: ...g SPIEN bit MTU MTB STU STB Write the last data into SPI_DATAand wait until the TBE flag is set and then wait until the TRANS flag is cleared Disable the SPI by clearing SPIEN bit MRU MRB After getting the second last RBNE flag read out this data and delay for a SCK clock time and then disable the SPI by clearing SPIEN bit Wait until the last RBNE flag is set and read out the last data SRU SRB App...

Page 469: ... one for transmission and the other for reception The CRC calculation uses the polynomial in SPI_CRCPOLY register Application can switch on the CRC function by setting CRCEN bit in SPI_CTL0 register The CRC calculators continuously calculate CRC for each bit transmitted and received on lines and the calculated CRC values can be read from SPI_TCRC and SPI_RCRC register To transmit the calculated CR...

Page 470: ...vice can be in slave mode with CONFERR bit set which means there might have been a multi master conflict for system control Rx Overrun Error RXORERR The RXORERR bit is set if a data is received when the RBNE is set That means the last data has not been read out and the newly incoming data is received The receive buffer contents won t be covered with the newly incoming data so the newly incoming da...

Page 471: ...registers module including theTX buffer and RX buffer The clock generator is used to produce I2S communication clock in master mode The master control logic is implemented to generate the I2S_WS signal and control the communication in master mode The slave control logic is implemented to control the communication in slave modeaccordingtothereceivedI2SCK andI2S_WS Theshift registerhandles theserial...

Page 472: ...r read operations to or from the SPI_DATA register are needed to complete a frame In the case that the data length is 16 bits only one write or read operation to or from the SPI_DATA register is needed to complete a frame When using 16 bit data packed in 32 bit frame 16 bit 0 is inserted by hardware automatically to extend the data to 32 bit format For all standards and packet types the most signi...

Page 473: ... the lower 16 bits Figure 19 19 I2S Phillips standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 bit 0 MSB Figure 19 20 I2S Phillips standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 bit 0 MSB When the packet type is 24 bit data packe...

Page 474: ... extend the data to 32 bit format MSB justified standard For MSB justified standard I2S_WS and I2S_SD are updated on the falling edge of I2S_CK The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard The timing diagrams for each configuration are shown below Figure 19 23 MSB justified standard timing diagram DTLEN 00 CHLEN 0 CKPL 0 I2S_CK I2S_SD 16 bit data frame...

Page 475: ..._CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB Figure 19 30 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB LSB justified standard For LSB justified standard I2S_WS and I2S_SD are updated on the falling edge of I2S_CK In the case that the cha...

Page 476: ... reception mode if a 24 bit data D 23 0 is received the first data read from the SPI_DATA register is a 16 bit data The high 8 bits of this 16 bit data are zeros and the lower 8 bits are D 23 16 The second data read from the SPI_DATA register is D 15 0 Figure 19 33 LSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit 0 frame 1 channel left frame 2 channel right I2S_WS...

Page 477: ...ta MSB I2S_WS MSB LSB frame 1 frame 2 Figure 19 36 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figure 19 37 PCM standard short frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 0 I2S_CK I2S_SD 32 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figure 19 38 PCM standard short frame synchr...

Page 478: ...ization mode timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 Thetimingdiagrams foreachconfigurationof thelongframesynchronizationmodeareshown below Figure 19 43 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 0 I2S_CK I2S_SD 16 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure19 44 PCM standard long fra...

Page 479: ... mode timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0 Figure 19 48 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0 Figure 19 49 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 1...

Page 480: ...KOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register The I2S bitrate can be calculated by the formulas shown in Table 19 7 I2S bitrate calculation formulas Table 19 7 I2S bitrate calculation formulas MCKOEN CHLEN Formula 0 0 I2SCLK DIV 2 OF 0 1 I2SCLK DIV 2 OF 1 0 I2SCLK 8 DIV 2 OF 1 1 I2SCLK 4 DIV 2 OF The relationship between audio sampling frequency Fs and I2S bitrat...

Page 481: ...The direction of I2S interface signals for each operation mode is shown in the Table 19 9 Direction of I2S interface signals for each operation mode Table 19 9 Direction of I2S interface signals for each operation mode Operation mode I2S_MCK I2S_CK I2S_WS I2S_SD Master transmission output or NU 1 output output output Master reception output or NU 1 output output input Slave transmission input or N...

Page 482: ...s to select I2S operation mode Configure the DTLEN 1 0 bits and the CHLEN bit to select I2S data format Configure the TBEIE bit the RBNEIE bit the ERRIE bit to enable I2S interrupt optional Configure the DMATEN bit and the DMAREN bit to enable I2S DMA function optional Configure the I2SEN bit to enable I2S No I2S master transmission sequence The TBE flag is used to control the transmission sequenc...

Page 483: ... theTBE flagis high and the TRANS flag is low I2S master reception sequence The RBNE flag is used to control the reception sequence As is mentioned before the RBNE flag indicates the receive buffer is not empty and an interrupt will be generated if the RBNEIE bit in the SPI_CTL1 register is set The reception sequence begins immediately when the I2SEN bit in the SPI_I2SCTL register is set At the be...

Page 484: ...xternal master starts the communication Thetransmissionsequencebeginswhentheexternal mastersendstheclock and when the I2S_WS signal requests the transfer of data The data has to be written to the SPI_DATA register before the master initiates the communication Software should write the next audio data into SPI_DATA register before the current data finishe Otherwise transmission underrun error occur...

Page 485: ...TBE RBNE TRANS and I2SCH The user can use them to fully monitor the state of theI2S bus Transmit buffer empty flag TBE This bit is set when the transmit buffer is empty the software can write the next data to the transmit buffer by writing the SPI_DATA register Receive buffer not empty flag RBNE This bit is set when receive buffer is not empty which means that one data is received and storedinther...

Page 486: ...ve I2S mode the I2S monitors the I2S_WS signal and anerror flag will be set if I2S_WS toggles at an unexpected position I2S interrupt events and corresponding enabled bits are summed up in the Table 19 10 I2S interrupt Table 19 10 I2S interrupt Flag Name Description Clear Method Interrupt Enable bit TBE Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not empty Read SPI_DATA...

Page 487: ...w rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 BDEN Bidirectionalenable 0 2 line unidirectional transmit mode 1 1 line bidirectional transmit mode The information transfersbetween the MOSI pin in master and the MISO pin in slave 14 BDOEN Bidirectional transmit output enable When BDEN is set this bit determines the direction of transfer 0 Work in receive ...

Page 488: ...ing in SPI TI mode 8 SWNSS NSS pin selection in NSS software mode 0 NSS pin is pulled low 1 NSS pin is pulled high This bit has an effect only when the SWNSSEN bit is set This bit has no meaning in SPI TI mode 7 LF LSB first mode 0 Transmit MSB first 1 Transmit LSB first This bit has no meaning in SPI TI mode 6 SPIEN SPI enable 0 SPI peripheral is disabled 1 SPI peripheral is enabled 5 3 PSC 2 0 M...

Page 489: ...errupt is disabled 1 TBE interrupt is enabled An interrupt is generated when the TBE bit is set 6 RBNEIE Receive buffer not empty interrupt enable 0 RBNE interrupt is disabled 1 RBNE interrupt is enabled An interrupt is generated when the RBNE bit is set 5 ERRIE Errors interrupt enable 0 Error interrupt is disabled 1 Error interrupt is enabled An interrupt is generated when the CRCERR bit or the C...

Page 490: ...fset 0x08 Reset value 0x0002 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FERR TRANS RXORERR CONFERR CRCERR TXURERR I2SCH TBE RBNE rc_w0 r r r rc_w0 r r r r Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 FERR Format error bit SPI TI Mode 0 No TI Mode format error 1 TI Mo...

Page 491: ...st This bit is set by hardware and is able to be cleared by writing 0 This bit is not used in I2S mode 3 TXURERR Transmission underrun error bit 0 No transmission underrun error occurs 1 Transmission underrun error occurs This bit is set by hardware and cleared by a read operation on the SPI_STAT register This bit is not used in SPI mode 2 I2SCH I2S channel side 0 The next data needs to be transmi...

Page 492: ..._DATA 7 0 is used for transmission and reception transmit buffer and receive buffer are 8 bits If the Data frame format is set to 16 bit data the SPI_DATA 15 0 is used for transmission and reception transmit buffer and receive buffer are 16 bit 19 5 5 CRC polynomial register SPI_CRCPOLY Address offset 0x10 Reset value 0x0007 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 2...

Page 493: ... standard and saves the value in RCRC 15 0 The hardware computes the CRC value after each received bit when the TRANS is set a read to this register could return an intermediate value This register is reset when the CRCEN bit or the SPIEN bit in SPI_CTL0 register is cleared 19 5 7 TX CRC register SPI_TCRC Address offset 0x18 Reset value 0x0000 This register has to be accessed by word 32 bit 31 30 ...

Page 494: ...t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved I2SSEL I2SEN I2SOPMOD 1 0 PCMSMOD Reserved I2SSTD 1 0 CKPL DTLEN 1 0 CHLEN rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 I2SSEL I2S mode selection 0 SPI mode 1 I2S mode This bit should be configured when SPI mode or I2S mode is disabled 10 I2SEN...

Page 495: ... low level 1 The idle state of I2S_CK is high level This bit should be configured when I2S mode is disabled This bit is not used in SPI mode 2 1 DTLEN 1 0 Data length 00 16 bits 01 24 bits 10 32 bits 11 Reserved These bits should be configured when I2S mode is disabled These bits are not used in SPI mode 0 CHLEN Channel length 0 16 bits 1 32 bits The channel length must be equal to or greater than...

Page 496: ...ed in SPI mode 7 0 DIV 7 0 Dividing factor for the prescaler Real divider value is DIV 2 OF DIV must not be 0 These bits should be configured when I2S mode is disabled These bits are not used in SPI mode 19 5 10 Quad SPI mode control register SPI_QCTL of SPI0 Address offset 0x80 Reset value 0x0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reser...

Page 497: ... read mode This bit should be only be configured when SPI is not busy TRANS bit cleared This bit is only available in SPI0 0 QMOD Quad SPI mode enable 0 SPI is in single wire mode 1 SPI is in Quad SPI mode This bit should onlybe configured when SPI is not busy TRANS bit cleared This bit is only available in SPI0 ...

Page 498: ...wing MMC Full support for Multimedia Card System Specification Version 4 2 and previous versions Card and three different data bus modes 1 bit default 4 bit and 8 bit SD Card Full support for SD Memory Card Specifications Version 2 0 SDI O Full support forSDI OCardSpecificationVersion2 0 card and twodifferentdata bus modes 1 bit default and 4 bit CE ATA Full compliance with CE ATA digital protocol...

Page 499: ...ne This mode reduces the command overhead to an absoluteminimum only MMC supports Block oriented commands These commands send a data block successfully by CRC bits Both read and write operations allow either single or multiple block transmission A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read The basic transaction on the bus ...

Page 500: ...e operation Data transfers to from SD memory cards SD I O cards both IO only card and combo card and CE ATA device are done in data blocks Data transfers to from MMC are done in data blocks or streams Figure20 4 SDIO sequential read operation and Figure 20 5 SDIO sequential write operation are the stream read and write operation Figure 20 4 SDIO sequential read operation ...

Page 501: ...egisters by AHBbus containsFIFOunit which is data FIFO used for data transfer and generates interrupt and DMArequest signals Figure 20 6 SDIO block diagram SDIO controller HCLK SDIOCLK SDIO_CMD SDIO_CLK SDIO_DAT 7 0 SDIO adapter control unit command unit data unit registers FIFO AHB interface interrupt DMA request AHB bus 20 4 1 SDIO adapter The SDIO adapter contains control unit command unit and ...

Page 502: ...nects the internal pull ups of lines DAT1 and DAT2 DAT3 internal pull up is left connected due to the SPI mode CS usage Correspondingly right after entering to the 8 bit mode the card disconnects the internal pull ups of lines DAT1 DAT2 and DAT4 DAT7 Table 20 1 SDIO I O definitions Pin function Direction Description SDIO_CLK O SD SD I O MMC clock SDIO_CMD I O Command input output SDIO_DAT 7 0 I O ...

Page 503: ...which have 136 bits The response stores in SDIO_RESP0 SDIO_RESP3 registers The command unit also generates the command status flags defined in SDIO_STAT register Command state machine CS_Idle After reset ready to send command 1 CSM enabled and WAITDEND enabled CS_Pend 2 CSM enabled and WAITDEND disabled CS_Send 3 CSM disabled CS_Idle Note The state machine remains in the Idle state for at least ei...

Page 504: ...bits inSDIO_CLKCTL register is 0b01 or SDIO_DAT 0 signal when 1 bit data width BUSMODE bits in SDIO_CLKCTL register is 0b00 The data transfer flow is controlled by Date StateMachine DSM After a write operation to SDIO_DATACTL register and DATAEN in SDIO_DATACTL register is 1 the data transfer starts It sends data to card when DATADIR in SDIO_DATACTL register is 0 or receive data from card when DAT...

Page 505: ...egister SDIO_DATATO DS_Receive Receive data from the card and write it to the data FIFO 1 Data block received DS_WaitR 2 Data transfer ended DS_WaitR 3 Data FIFO overrun error occurs DS_Idle 4 Data received and Read Wait Started and SD I O mode enabled DS_Readwait 5 DSM disabled or CRC fails DS_Idle DS_Readwait Wait for the read wait stop command 1 ReadWait stop enabled DS_WaitR 2 DSM disabled DS_...

Page 506: ...mmand Other fields are their reset value When the CMDRECV flag is set program the SDIO data control register SDIO_DATACTL DATAEN with 1 enable to send data DATADIR with0 from controller to card TRANSMOD with 0 block data transfer DMAEN with 1 DMA enabled BLKSZ with 0x9 512 bytes Other bits don t care Wait for DTBLKEND flag is set Check that no channels are still enabled by polling the DMA Interrup...

Page 507: ... register provides information regarding access to the card contents The CSD defines the data format error correction type maximum data access time datatransferspeed whethertheDSRregistercanbeused etc Theprogrammablepart of the register can be changed by CMD27 The host can use CMD9 to get the content of this register Extended CSD Register Just MMC4 2has this register The Extended CSD register defi...

Page 508: ...commands with response bcr response from all cards simultaneously Addressed point to point commands ac no data transfer on DAT Addressed point to point data transfer commands adtc data transfer on DAT Command format All commands have a fixed code length of 48 bits as show in Figure 20 7 Command Token Format needing a transmission time of 1 92μs 25 MHz 0 96μs 50 MHz and 0 92us 52 MHz Figure 20 7 Co...

Page 509: ...ritable card or a stream readable card The supported Card Command Classes CCC are coded as a parameter in the card specific data CSD register of each card providing the host withinformation on how to access the card For CE ATA device the device shall support the MMC commands required to achieve the transfer state during device initialization Other interface configuration settings such as bus width...

Page 510: ... M CMD12 M CMD13 M CMD14 M CMD15 M CMD16 M CMD17 M CMD18 M CMD19 M CMD20 M CMD23 M CMD24 M CMD25 M CMD26 M CMD27 M CMD28 M CMD29 M CMD30 M CMD32 M CMD33 M CMD34 O CMD35 O CMD36 O CMD37 O CMD38 M CMD39 CMD40 CMD42 CMD50 O CMD52 O CMD53 O CMD55 M CMD56 M CMD57 O CMD60 M CMD61 M ...

Page 511: ...ment Response format Abbreviation Description CMD0 bc 31 0 stuff bits GO_IDLE_STATE Resets all cards to idle state CMD1 bc 31 0 OCR without busy R3 SEND_OP_CON D Asks the card in idle state to send its Operating Conditions Register contents in the response on the CMD line CMD2 bcr 31 0 stuff bits R2 ALL_SEND_CID Asks any card to send the CID numbers on the CMD line any card that is connected to th...

Page 512: ...card supports voltage Reserved bits shall be set to 0 CMD8 adtc 31 0 stuff bits R1 SEND_EXT_CSD For MMC only The card sends its EXT_CSD register as a block of data CMD9 ac 31 16 RCA 15 0 stuff bits R2 SEND_CSD Addressed card sends its card specific data CSD on the CMD line CMD10 ac 31 16 RCA 15 0 stuff bits R2 SEND_CID Addressed card sends its card identification CID on CMD the line CMD12 ac 31 0 ...

Page 513: ... commands Always 512 Bytes fixed block length is used In both cases if block length is set larger than 512Bytes the card sets the BLOCK_LEN_ERROR bit CMD17 adtc 31 0 data address R1 READ_SINGLE_B LOCK In the case of a Standard Capacity SD and MMC this command reads a block of the size selected by the SET_BLOCKLEN command In the case of a High Capacity Card block length is fixed 512 Bytes regardles...

Page 514: ...esponse format Abbreviation Description CMD16 ac 31 0 block length R1 SET_BLOCKLEN See description in Table 20 5 Block Oriented read commands class 2 CMD23 ac 31 16 set to 0 15 0 number of blocks R1 SET_BLOCK_ COUNT Defines the number of blocks which are going to be transferred in the immediately succeeding multiple block read or write command If the argument is all 0s the subsequent read write op...

Page 515: ...in a High Capacity SD Memory Card Table 20 8 Erase commands class 5 Cmd index type argument Response format Abbreviation Description CMD32 ac 31 0 data address R1 ERASE_WR_BLK _START Sets the address of the first write block to be erased SD CMD33 ac 31 0 data address R1 ERASE_WR_BLK _END Sets the address of the last write block of the continuous range to be erased SD CMD35 ac 31 0 data address R1 ...

Page 516: ...the write protection bit of the addressed group CMD30 adtc 31 0 write protect data address R1 SEND_WRITE_PR OT If the card provides write protection features this command asks the card to send the status of the write protection bits Note 1 High Capacity SD Memory Card does not support these three commands Table 20 10 Lock card class 7 Cmd index type argument Response format Abbreviation Descriptio...

Page 517: ...ion Register SCR CMD55 ac 31 16 RCA 15 0 stuff bits R1 APP_CMD Indicates to the card that the next command is an application specific command rather than a standard command CMD56 adtc 31 1 stuff bits 0 RD WR R1 GEN_CMD Used either to transfer a data block to the card or to get a data block from the card for general purpose application specific command The host sets RD WR 1 for reading data from th...

Page 518: ...into interrupt mode CMD52 adtc 31 R W Flag 30 28 Function Number 27 RAW Flag 26 Stuff Bits 25 9 Register Address 8 Stuff Bits 7 0 Write Data Stuff Bits R5 IO_RW_DIREC T The IO_RW_DIRECT is the simplest means to access a single register within the total 128K of register space in any I O function including the common I O area CIA This command reads or writes 1 byte using only 1 command response pair...

Page 519: ...unction group 4 0h or Fh 11 8 reserved for function group 3 0h or Fh 7 4 function group 2 for command system 3 0 function group 1 for access mode R1 SWITCH_FUNC Only for SD memory and SD I O Checks switchable function mode 0 and switch card function mode 1 20 5 3 Responses All responses are sent on the CMD line The response transmission always starts with the left bit of the bit string correspondi...

Page 520: ...e type R3 are protected by a CRC Every command code word is terminated by the end bit always 1 R1 normal response command Code length is 48 bits The bits 45 40 indicate the index of thecommand to be responded to this value being interpreted as a binary coded number between 0 and 63 The status of the card is coded in 32 bits Note that if a data transfer to the card is involved then a busy signal ma...

Page 521: ...emory CMD1 MMC The responseof different cards may havea little different Table 20 16 Response R3 Bit position 47 46 45 40 39 8 7 1 0 Width 1 1 6 32 7 1 Value 0 0 111111 x 1111111 1 description start bit transmission bit reserved OCR register reserved end bit R4 Fast I O For MMC only Code length 48 is bits The argument field contains the RCA of the addressed card the register address to be read out...

Page 522: ...bit transmission bit CMD40 RCA 31 16 of winning card or of the host 15 0 Not defined May be used for IRQ data CRC7 end bit R5b ForSDI Oonly The SDIOcard s responsetoCMD52andCMD53is R5 If thecommunication between the card and host is in the 1 bit or 4 bit SD mode the response shall be in a 48 bit response R5 Table 20 20 Response R5 for SD I O Bit position 47 46 45 40 39 24 23 16 15 8 7 1 0 Width 1 ...

Page 523: ...1000 00000h x x x 1 description start bit transmission bit CMD8 Reserved bits Voltage accepted echo back of check pattern CRC7 end bit 20 5 4 Data packets format There are 3 data bus mode 1 bit 4 bit and 8 bit width 1 bit mode is mandatory 4 bit and 8 bit modeis optional Althoughusing1 bit mode DAT3alsoneedtonotify cardcurrent working mode is SDIO or SPI when card reset and initialize 1 bit data p...

Page 524: ...b6 b5 b4 b7 b6 b5 b4 b7 b6 b5 b4 b3 b2 b1 b0 20 5 5 Two status fields of the card The SD Memory supports two status fields and others just support the first one Card Status Error and state information of a executedcommand indicated in the response SD Status Extended status field of 512 bits that supports special features of the SD Memory Card and futureApplication Specific features Card status The...

Page 525: ...its Identifier Type Value Description Clear Condition 31 OUT_OF_RANGE ERX 0 no error 1 error The command s argument was out of the allowed range for this card C 30 ADDRESS_ERROR ERX 0 no error 1 error A misaligned addresswhichdid not match the block length was used in the command C 29 BLOCK_LEN_ERROR ERX 0 no error 1 error The transferred block length is not allowed for this card or the number of ...

Page 526: ...RRUN ERX 0 no error 1 error Only for MMC The card could not sustain data programming in stream write mode C 16 CID CSD_OVERWRITE ERX 0 no error 1 error Can be either one of the following errors The read only section of the CSD does not match the card content An attempt to reverse the copy set as original or permanent WP unprotected bits was made C 15 WP_ERASE_SKIP ERX 0 not protected 1 protected S...

Page 527: ...s been interpreted as ACMD C 4 Reserved 3 AKE_SEQ_ERROR ER 0 no error 1 error Only for SD memory Error in the sequence of the authentication process C 2 Reserved for application specific commands 1 0 Reserved for manufacturer test mode Note 18 17 7 bits are only for MMC 14 3 bits are only for SD memory SD status register The SD Status contains status bits that are related to the SD Memory Card pro...

Page 528: ...future the 8 LSBs will be used to define different variations of an SD Memory Card Each bit will define different SD Types The 8 MSBs will be used to define SD Cards that do not comply with current SD Physical Layer Specification A 479 448 SIZE_OF_PROTECT ED_AREA SR Size of protected area See below A 447 440 SPEED_CLASS SR Speed class of the card See below A 439 432 PERFORMANCE_M OVE SR Performanc...

Page 529: ...otected area is calculated as follows ProtectedArea SIZE_OF_PROTECTED_AREA SIZE_OF_PROTECTED_AREAis specified by the unit in byte SPEED_CLASS This 8 bit field indicates theSpeed Class 00h Class 0 01h Class 2 02h Class 4 03h Class 6 04h Class 10 05h FFh Reserved PERFORMANCE_MOVE This 8 bit field indicates Pm and the value can be set by 1 MB sec step If the card does not move useing RUs Pm should be...

Page 530: ...at is less than or equal to the maximum AU size The card should set smallerAU size as possible Table 20 27 MaximumAU size Card Capacity up to 64MB up to 256MB up to 512MB up to 32GB up to 2TB Maximum AU Size 512 KB 1 MB 2 MB 4 MB1 64MB ERASE_SIZE This 16 bit field indicates NERASE When NERASE of AUs are erased the timeout value is specified by ERASE_TIMEOUT Refer to ERASE_TIMEOUT The host should d...

Page 531: ...se timeout of XAU TERASE NERASE X TOFFSET 20 1 Table 20 29 Erase timeout field ERASE_TIMEOUT Value Definition 00 Erase Time out Calculation is not supported 01 1 sec 02 2 sec 03 3 sec 63 63 sec If ERASE_SIZE field is set to 0 this field shall be set to 0 ERASE_OFFSET This 2 bit field indicates the TOFFSET and one of four values can be selected This field is meaningless if ERASE_SIZE and ERASE_TIME...

Page 532: ...now the card supportedvoltageandthecardmay not knowwhetherit supports thecurrent suppliedvoltage To verify the voltage thefollowing commands are defined in the related specification TheSEND_OP_COND CMD1forMMC SD_SEND_OP_COND ACMD41forSDmemory IO_SEND_OP_COND CMD5 for SD I O command is designed to provide hosts with a mechanism to identify and reject cards which do not match the VDD range desired b...

Page 533: ...d the CPU should select theATA modeby setting theATA bit bit 4 in the EXT_CSD register slice 191 CMD_SET to activate the ATA command set The CPU selects the command set using theSWITCH CMD6 command In the presence of a CE ATA device the FAST_IO CMD39 and RW_MULTIPLE_REGISTER CMD60 commands will succeed and the returned data will be the CE ATA reset signature 20 6 2 No data commands To send any non...

Page 534: ...data and completing the CRC check the card will begin writing and hold the DAT0 line low if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command Thehost may poll thestatusof thecardwithaSEND_STATUScommand CMD13 at any time and the card will respond with its status The status bit READY_FOR_DATA indicates whether the card can accept new data or whether the write proc...

Page 535: ...AD_MULTIPLE_BLOCK starts a transfer of several consecutiveblocks CRCis appendedtotheendof eachblock ensuringdatatransfer integrity Block Length set by CMD16 can be set up to 512 bytes regardless of READ_BL_LEN Blocks will be continuously transferred until a STOP_TRANSMISSION command CMD12 is issued The stop command has an execution delay due to the serial command transmission The data transfer sto...

Page 536: ...ecardaddress space otherwiseit shall start andstoponlyat blockboundaries Since the amount of data to be transferred is not determined in advance CRC cannot be used If the host provides an out of range address as an argument to CMD20 the card will reject the command remain in Tran state and respond with the ADDRESS_OUT_OF_RANGE bit set Note that the stream write command works only on a 1 bit bus co...

Page 537: ...o stop command has been sent yet by the host the contents of the further transferred payload is undefined As the host sends CMD12 the card will respond with the ADDRESS_OUT_OF_RANGE bit set and return to Tran state In order to sustain data transfer in stream mode of the card the time it takes to transmit the data defined by the bus clock rate must be less than the time it takes to read it out of t...

Page 538: ...r of CMD35 CMD36 CMD38 or CMD13 is received the card shall respond with the ERASE_RESET bit set reset the erase sequence and execute the last command If the erase range includes write protected blocks they shall be left intact and only the non protected blocks shall be erased The WP_ERASE_SKIP status bit in thestatus register shall be set As described above for block write the card will indicate t...

Page 539: ...e window is closed the card is not write protected Password card Lock Unlock Operation The Password Card Lock Unlock protection is described in Card Lock Unlock operation 20 6 9 Card Lock Unlock operation The password protection feature enables the host tolock a card while providing a password which later will be used for unlocking the card The password and its size are kept in a 128 bit PWD and 8...

Page 540: ...rd Setting the password Select a card CMD7 if not previously selected Define the block length CMD16 given by the 8 bit card lock unlock mode the 8 bit password size in bytes and the number of bytes of the new password In the case that a password replacement is done then the block size shall consider that both passwords the old and the new one are sent with the command Send the Card Lock Unlock com...

Page 541: ...ze on thedata line including the 16 bit CRC The data block shall indicate the mode LOCK the length PWDS_LEN and the password itself If the PWD content is equal to the sent password then the card will be locked and the card locked status bit will be set in the status register If the password is not correct then the LOCK_UNLOCK_FAILED error bit will be set in the status register Unlocking the card S...

Page 542: ... not abort data in the middle of a read multiple command is to control the SDIO_CLK The limitation of this method is that with the clock stopped the host cannot issue any commands and so cannot perform other operations during the delay time Read Wait support is mandatory for the card to support suspend resume Figure 20 12 Read wait control by stopping SDIO_CLK and Figure 20 13 Read wait operation ...

Page 543: ...ed where it left off resume Figure 20 14 Function2read cycle inserted during function1 multiple read cycle shows a condition where the first suspend request is not immediately accepted The host then checks the status of the request with a read and determines that the bus has now been released BS 0 At this time a read to function 2 is started Once that single block read is completed the resume is i...

Page 544: ...ycle timing SDIO_CLK DAT0 Command read data 2 CLK CMD DAT1 DAT1 mode S E Response S E Command read data S E Data S E Data S E interrupt data data Figure 20 16 Write interrupt cycle timing SDIO_CLK DAT0 Command write data 2 CLK CMD DAT1 DAT1 mode S E Response S E Data S E interrupt data interrupt Data S E Command write data S E CRC S E When transferring multiple blocks of data in the 4 bit SD mode ...

Page 545: ...DIO supports these operations only when SDIO_CMDCTL 14 is set Command completion signal CE ATA defines a command completion signal that the device uses to notify the host upon normal ATA command completion or when ATA command termination has occurred due to an error condition the device has encountered If the enable CMD completion bit SDIO_CMDCTL 12 is set and the not interrupt Enable bit SDIO_CMD...

Page 546: ...letion signal disable when it has received an R1b response for an outstanding RW_MULTIPLE_BLOCK CMD61 command Command completionsignal disableissent 8bitcyclesafterthereceptionof ashortresponse if the enableCMDcompletion bit SDIO_CMDCTL 12 is not setand the not interruptEnable bit SDIO_CMDCTL 13 is reset Figure 20 19 The operation for command completion disable signal CMD Nrc Ncr CMD S E Response ...

Page 547: ...or output 00 SDIO power off SDIO cmd data state machine reset to IDLE clock to card stopped no cmd data output to card 01 Reserved 10 Reserved 11 SDIO Power on Note Between Two write accesses to this register it needs at least 3 SDIOCLK 2 pclk2 which used to sync the registers to SDIOCLK clock domain 20 8 2 Clock control register SDIO_CLKCTL Address offset 0x04 Reset value 0x0000 0000 This registe...

Page 548: ...t 00 1 bit SDIO card bus mode selected 01 4 bit SDIO card bus mode selected 10 8 bit SDIO card bus mode selected 10 CLKBYP Clock bypass enable bit This bit defines the SDIO_CLK is directly SDIOCLK or not 0 NO bypass the SDIO_CLK refers to DIV bits in SDIO_CLKCTL register 1 Clock bypass the SDIO_CLK is directly from SDIOCLK SDIOCLK 1 9 CLKPWRSAV SDIO_CLK clock dynamic switch on off for power saving...

Page 549: ...essage contains an argument this field must update before writing SDIO_CMDCTL register when sending a command 20 8 4 Command control register SDIO_CMDCTL Address offset 0x0C Reset value 0x0000 0000 The SDIO_CMDCTL register contains the command index and other command control bits to control command state machine This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 550: ...mand state machine enable 9 WAITDEND Waits for ends of data transfer If this bit is set the command state machine starts to send a command must wait the end of data transfer 0 no effect 1 Wait the end of data transfer 8 INTWAIT Interrupt wait instead of timeout This bit defines the command state machine to wait card interrupt at CS_Wait state in command state machine If this bit is set no command ...

Page 551: ...3 the content of this register is undefined 20 8 6 Response register SDIO_RESPx x 0 3 Address offset 0x14 4 x x 0 3 Reset value 0x0000 0000 These register contains the content of the last card response received This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESPx 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESPx 15 0 r Bits Fields Descriptions 31 ...

Page 552: ...Y the internal counter which loads from this register starts decrement The DSM timeout and enter the state Idle and set the DTTMOUT flag when the counter decreases to 0 Note The data timer register and the data length register must be updated before being written to the data control register when need a data transfer 20 8 8 Data length register SDIO_DATALEN Address offset 0x28 Reset value 0x0000 0...

Page 553: ...eserved IOEN RWTYPE RWSTOP RWEN BLKSZ 3 0 DMAEN TRANSM OD DATADIR DATAEN rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 IOEN SD I O specific function enable SD I O only 0 Not SD I O specific function 1 SD I O specific function 10 RWTYPE Read wait type SD I O only 0 Read Wait control using SDIO_DAT 2 1 Read Wait control by stopping SDIO_CLK 9 RWSTO...

Page 554: ... bit to start data transfer regardless this bit is 0 or 1 The DSM moves to Readwait state if RWEN is set or to the WaitS WaitR state depend on DATADIR bit Start a new data transfer it not need to clear this bit to 0 Note Between Two write accesses to this register it needs at least 3 SDIOCLK 2 pclk2 which used to sync the registers to SDIOCLK clock domain 20 8 10 Data counter register SDIO_DATACNT...

Page 555: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ATAEND SDIOINT RXDTVA L TXDTVAL RFE TFE RFF TFF r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFH TFH RXRUN TXRUN CMDRUN DTBLKE ND STBITE DTEND CMDSEN D CMDREC V RXORE TXURE DTTMOU T CMDTMO UT DTCRCE RR CCRCER R r r r r r r r r r r r r r r r r Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 ATAEND CE ATA command com...

Page 556: ...nsmit FIFO underrun error occurs 3 DTTMOUT Data timeout The data timeout period depends on the SDIO_DATATO register 2 CMDTMOUT Command response timeout The command timeout period has a fixed value of 64 SDIO_CLK clock periods 1 DTCRCERR Data block sent received CRC check failed 0 CCRCERR Command response received CRC check failed 20 8 12 Interrupt clear register SDIO_INTC Address offset 0x38 Reset...

Page 557: ... this bit to clear the flag 6 CMDRECVC CMDRECV flag clear bit Write 1 to this bit to clear the flag 5 RXOREC RXORE flag clear bit Write 1 to this bit to clear the flag 4 TXUREC TXURE flag clear bit Write 1 to this bit to clear the flag 3 DTTMOUTC DTTMOUT flag clear bit Write 1 to this bit to clear the flag 2 CMDTMOUTC CMDTMOUT flag clear bit Write 1 to this bit to clear the flag 1 DTCRCERRC DTCRCE...

Page 558: ...le the interrupt 20 TXDTVALIE Data valid in transmit FIFO interrupt enable Write 1 to this bit to enable the interrupt 19 RFEIE Receive FIFO empty interrupt enable Write 1 to this bit to enable the interrupt 18 TFEIE Transmit FIFO empty interrupt enable Write 1 to this bit to enable the interrupt 17 RFFIE Receive FIFO full interrupt enable Write 1 to this bit to enable the interrupt 16 TFFIE Trans...

Page 559: ...e Write 1 to this bit to enable the interrupt 3 DTTMOUTIE Data timeout interrupt enable Write 1 to this bit to enable the interrupt 2 CMDTMOUTIE Command response timeout interrupt enable Write 1 to this bit to enable the interrupt 1 DTCRCERRIE Data CRC fail interrupt enable Write 1 to this bit to enable the interrupt 0 CCRCERRIE Command response CRC fail interrupt enable Write 1 to this bit to ena...

Page 560: ...FIFO data register SDIO_FIFO Address offset 0x80 Reset value 0x0000 0000 This register occupies 32 entries of 32 bit words the address offset is from 0x80 to 0xFC This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIFODT 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFODT 15 0 rw Bits Fields Descriptions 31 0 FIFODT 31 0 Receive FIFO data or transmit ...

Page 561: ...y SRAM PSRAM ROM NOR Flash 8 bit or 16 bit NAND Flash 16 bit PC Card Protocol translation between the AMBA and the multitude of external memory protocol Offering a variety of programmable timing parameters to meet user s specific needs Each bank has its own chip select signal which canbe configured independently Independent read write timing configuration to a sub set memory type Embedded ECC hard...

Page 562: ...ead write accesses can be split into several consecutive 8 bit or 16 bit read write operations respectively In the process of data transfer AHB access data width and memory datawidthmay notbethesame Inordertoensureconsistency of datatransmission EXMC s read write accesses follows the following basic regulation When the width of AHB bus equals to the memory bus width no conversion is applied When t...

Page 563: ...kx x 1 2 is divided into two spaces the attribute memory space and the common memory space Bank3 is divided into three spaces which are the attribute memory space the common memory space and the I O memory space Each bank or region has a separate chip select control signal which can be configured independently Bank0 is used for NOR and PSRAM device access Bank1 and bank2 are used to access NAND Fl...

Page 564: ...he following rules When data bus width of the external memory is 8 bits in this casethe memory address is bytealigned HADDR 25 0 is connectedtoEXMC_A 25 0 andthentheEXMC_A 25 0 is connected to the external memory address lines When databus widthof theexternal memoryis 16 bits inthis casethememoryaddress is half word aligned HADDR byteaddress must be converted into half word aligned by connecting H...

Page 565: ...800_0000 0x9BFF_FFFF 0x9C00_0000 0x9FFF_FFFF Address Memory Space EXMC Memory Bank NAND address mapping For NAND Flash the common space and the attribute space are further divided into three areas individually thedataarea thecommandareaand theaddress areaas shownin Figure 21 5 Diagram of bank1 common space Figure 21 5 Diagram of bank1 common space Data Area Command Area Address Area 0x70000000 0x7...

Page 566: ...EXMC is in data reception mode software should read the data from the NAND Flash by reading this area Data access address is incremented automatically in consecutive mode users need not to be concerned with access address area 21 3 4 NOR PSRAM controller NOR PSRAM memory controller controls bank0 which is designed to support NOR Flash PSRAM SRAM ROM and honeycomb RAM external memory EXMC has 4 ind...

Page 567: ...c Chip selection x 0 1 2 3 EXMC_NOE Output Async Sync Read enable EXMC_NWE Output Async Sync Write enable EXMC_NWAIT Input Async Sync Wait input signal EXMC_NL NADV Output Async Sync Latch enable address valid enable NADV EXMC_NBL 1 Output Async Sync Upper byte enable EXMC_NBL 0 Output Async Sync Lower byte enable Supported memory access mode Table below shows an example of the supported devices t...

Page 568: ...it into 2 EXMC accesses Async R 16 16 Async R 32 8 Split into 4 EXMC accesses Async R 32 16 Split into 2 EXMC accesses Async W 8 8 Async W 8 16 Use of byte lanes EXMC_NBL 1 0 Async W 16 8 Async W 16 16 Async W 32 8 Async W 32 16 NOR Flash PSRAM controller timing EXMCprovidesvariousprogrammabletimingparameters andtimingmodels forSRAM ROM PSRAM NOR Flash and other external static memory Table 21 4 N...

Page 569: ...d capability WDSET WAHLD WASET DSET AHLD ASET Mode AM 0 NOR Flash address data mux DSET AHLD ASET BUSLAT DSET AHLD ASET BUSLAT Sync Mode E 0 NOR PSRAM CRAM synchronous read PSRAM CRAM synchronous write DLAT CKDIV DLAT CKDIV Mode SM 0 NOR Flash address data mux DLAT CKDIV DLAT CKDIV As shown in Table 21 5 EXMC_timing models EXMC NOR Flash PSRAM controller provides a variety of timing model users ca...

Page 570: ...elect EXMC_NBL 1 0 Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EXMC_D 15 0 Address Setup Time ASET 1 HCLK Data Setup Time DSET HCLK EXMC Output 1 HCLK Table 21 6 Mode 1 related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 CPS 0x0 15 ASYNCWAIT Depends on memory 14 EXMODEN 0x0 13 NRWTEN 0x0 12 WE...

Page 571: ...t 19 16 BUSLAT Time between EXMC_NE x rising edge to EXMC_NE x falling edge 15 8 DSET Depends on memory and user DSET 1 HCLK for write DSET 3 HCLK for read 7 4 AHLD No effect 3 0 ASET Depends on memory and user Mode A SRAM PSRAM CRAM OE toggling Figure 21 8 Mode A read access Address EXMC_A 25 0 Byte Lane Select EXMC_NBL 1 0 Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EX...

Page 572: ...g configuration is independent of its read configuration Table 21 7 Mode A related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 CPS 0x0 15 ASYNCWTEN Depends on memory 14 EXMODEN 0x1 13 NRWTEN 0x0 12 WEN Depends on user 11 NRWTCFG No effect 10 WRAPEN 0x0 9 NRWTPOL Meaningful only when the bit 15 is set to 1 8 SBRSTEN 0x0 ...

Page 573: ...ed 0x0 29 28 WASYNCMOD 0x0 27 20 Reserved 0x00 19 16 WBUSLAT Time between EXMC_NE x rising edge to EXMC_NE x falling edge 15 8 WDSET Depends on memory and user WDSET 1 HCLK for write 7 4 WAHLD 0x0 3 0 WASET Depends on memory and user Mode 2 B NOR Flash Figure 21 10 Mode 2 B read access Address EXMC_A 25 0 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Dat...

Page 574: ...nable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EXMC_D 31 0 Address Setup Time WASET 1 HCLK Data Setup Time WDSET HCLK EXMC Output 1 HCLK Table 21 8 Mode 2 B related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx Mode 2 Mode B 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 CPS 0x0 15 ASYNCWTEN Depends on memory 14 EXMODEN Mode 2 0x0 Mode B 0x1 13 NRWTE...

Page 575: ...3 HCLK for read 7 4 AHLD 0x0 3 0 ASET Depends on memory and user EXMC_SNWTCFGx Write in mode B 31 30 Reserved 0x0000 29 28 WASYNCMOD Mode B 0x1 27 20 Reserved 0x00 19 16 WBUSLAT Time between EXMC_NE x rising edge to EXMC_NE x falling edge 15 8 WDSET Depends on memory and user WDSET 1 HCLK for write 7 4 WAHLD 0x0 3 0 WASET Depends on memory and user Mode C NOR Flash OE toggling Figure 21 13 Mode C ...

Page 576: ...ite timing configuration is independent of its read configuration Table 21 9 Mode C related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 CPS 0x0 15 ASYNCWTEN Depends on memory 14 EXMODEN 0x1 13 NRWTEN 0x0 12 WEN Depends on user 11 NRWTCFG No effect 10 WRAPEN 0x0 9 NRWTPOL Meaningful only when the bit 15 is set to 1 8 SBR...

Page 577: ... Reserved 0x00 19 16 WBUSLAT Time between EXMC_NE x rising edge to EXMC_NE x falling edge 15 8 WDSET Depends on memory and user WDSET 1 HCLK for write 7 4 WAHLD 0x0 3 0 WASET Depends on memory and user Mode D Asynchronous access with extended address Figure 21 15 Mode D read access Address EXMC_A 25 0 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EX...

Page 578: ...MC_SNCTLx 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 CPS 0x0 15 ASYNCWTEN Depends on memory 14 EXMODEN 0x1 13 NRWTEN 0x0 12 WEN Depends on user 11 NRWTCFG No effect 10 WRAPEN 0x0 9 NRWTPOL Meaningful only when the bit 15 is set to 1 8 SBRSTEN 0x0 7 Reserved 0x1 6 NREN Depends on memory 5 4 NRW Depends on memory 3 2 NRTP Depends on memory 1 NRMUX 0x0 0 NRBKEN 0x1 EXMC_SNTCFGx 31 30 Reserved 0x0 29 28...

Page 579: ...sh address data bus multiplexing Figure 21 17 Multiplex mode read access 1 HCLK Address EXMC_A 25 16 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data Mux EXMC_D 15 0 Memory Output Address Setup Time ASET 1 HCLK Data Setup Time DSET 1 HCLK Address Hold Time AHLD 1 HCLK Address 15 0 Address 25 16 2 HCLK Figure 21 18 Multiplex mode write access Address EX...

Page 580: ...ASYNCMOD 0x0 27 24 DLAT No effect 23 20 CKDIV No effect 19 16 BUSLAT Minimum time between EXMC_NE x rising edge to EXMC_NE x falling edge 15 8 DSET Depends on memory and user DSET 2 HCLK for write DSET 3 HCLK for read 7 4 AHLD Depends on memory and user 3 0 ASET Depends on memory and user Wait timing of asynchronous communication Wait feature is controlled by the bit ASYNCWAIT in register EXMC_SNC...

Page 581: ...p Time Memory Output 4 HCLK Wait EXMC_NWAIT NRWTPOL 1 2 HCLK Data sampling point Figure 21 20 Write access timing diagram under async wait signal assertion Address EXMC_A 25 0 Wait EXMC_NWAIT NRWTPOL 0 Chip Enable EXMC_NEx Write Enable EXMC_NWE Data EXMC_D 15 0 Address Setup Time Data Setup Time 3 HCLK EXMC Output 1 HCLK Wait EXMC_NWAIT NRWTPOL 1 Synchronous access timing diagram The relations bet...

Page 582: ...cted after a period of data latency If EXMC_NWAIT signal detected is valid wait cycles will be inserted until EXMC_NWAIT becomes invalid The valid polarity of EXMC_NWAIT NRWTPOL 1 valid level of EXMC_NWAIT signal is high NRWTPOL 0 valid level of EXMC_NWAIT signal is low In synchronous burst mode EXMC_NWAIT signal has two kinds of configurations NRWTCFG 1 When EXMC_NWAIT signal is active current cy...

Page 583: ...ble EXMC_NOE Write Enable EXMC_NWE HCLK Clock EXMC_CLK Wait EXMC_NWAIT Data EXMC_D 15 0 Address 15 0 Memory Data 1 Memory Data 2 Memory Data 3 Data Latency DATLAT 2 EXMC_CLK Wait Cycle NRWTCFG 0 Address 25 16 Burst read of three half words 2 EXMC_CLK Table 21 12 Timing configurations of synchronous multiplexed read mode Bit Position Bit Name Reference Setting Value EXMC_SNCTLx Bit Position Bit Nam...

Page 584: ... Mode SM Synchronous mux burst write timing PSRAM CRAM Figure 21 22 Write timing of synchronous multiplexed burst mode Address EXMC_A 25 16 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE HCLK Clock EXMC_CLK Wait EXMC_NWAIT Data EXMC_D 15 0 Address 15 0 Data Latency DATLAT 2 EXMC_CLK Wait Cycle NRWTCFG 0 Address 25 16 EXMC Data 2 EXMC Data 3 Burst write of...

Page 585: ...ct 3 0 ASET No effect 21 3 5 NAND Flash or PC Card controller EXMC has partitioned Bank1 and Bank2 as NAND Flash access field bank3 as PC Card access field Each bank has its own set of control register for access timing configuration 8 and 16 bit NAND Flash and 16 bit PC Card are supported An ECC hardware is provided for the NAND Flash controller to ensure the robustness of data transfer and stora...

Page 586: ...ctionaldata bus EXMC_NCE3_x Output Chip select x 0 1 EXMC_NOE Output Output enable EXMC_NWE Output Write enable EXMC_NWAIT Input PC Card wait input signal to the EXMC EXMC_INTR Input PC Card interrupt input signal EXMC_CD Input PC Card presence detection Active high Supported memory access mode Table 21 16 Bank1 2 3 of EXMC support the memory and access mode Memory Mode R W AHB transaction size Co...

Page 587: ...write operation 0 255 Memory hold time HLD W R HCLK The number of HCLK clock cycles to keep address valid after sending the command In write mode it is also data hold time 1 254 Memory wait time WAIT W R HCLK Minimum duration of sending command 2 256 Memory setup time SET W R HCLK The number of HCLK clock cycles to build address before sending command 1 255 The figure below shows the programmable ...

Page 588: ...l Inthis period NANDcontrollerwill maintainEXMC_NCE valid 5 Read data byte by byte from the data area of the common space 6 If new commands or address haven t been written data of the next page can be read out automatically You can also read the data of the next page by going to step 3 and then writing a new address or writing a new command and address in step 2 NAND Flash pre wait functionality S...

Page 589: ...CC offers one bit error correctionand two bits errors detection When NAND memory block is enabled ECC module will detect EXMC_D 15 0 EXMC_NCE and EXMC_NWE signals When a data size of ECCSZ has been read or written software must read the calculated ECC in theEXMC_NECCx register When a recalculation of ECC is needed software must clear the EXMC_NECCx register value by resetting ECCEN bit of EXMC_NPC...

Page 590: ...is notsupportedinbytemode WhenAHB word access is selected EXMC automatically splits it into 2 consecutive half word access EXMC_NREG is high when common memory is targeted EXMC_NOE and EXMC_NWE are the read and write enable signal for this type of access 2 Attribute space It is usually where configuration information are stored for byte AHB access only even address is possible Half word access con...

Page 591: ...eserved NR EN NRW 1 0 NRTP 1 0 NR MUX NRBK EN rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 SYNCWR Synchronous write 0 Asynchronous write 1 Synchronous write 18 16 CPS 2 0 CRAM page size 000 Automatic burst split on page boundary crossing 001 128 bytes 010 256 bytes 011 512 bytes 100 1024 bytes Others Reserved 15 ASYNCWAIT Asynchronou...

Page 592: ...NWAIT 8 SBRSTEN Synchronous burst enable 0 Disable burst access mode 1 Enable burst access mode 7 Reserved Must be kept at reset value 6 NREN NOR Flash access enable 0 Disable NOR Flash access 1 Enable NOR Flash access 5 4 NRW 1 0 NOR region memory data bus width 00 8 bits 01 16 bits default after reset 10 11 Reserved 3 2 NRTP 1 0 NOR region memory type 00 SRAM default after reset for region1 regi...

Page 593: ...e D access 27 24 DLAT 3 0 Data latency for NOR Flash Only valid in synchronous access 0x0 Data latency of first burst access is 2 EXMC_CLK 0x1 Data latency of first burst access is 3 EXMC_CLK 0xF Data latency of first burst access is 17 EXMC_CLK 23 20 CKDIV 3 0 Synchronous clock divide ratio This filed is onlyeffect in synchronous mode 0x0 Reserved 0x1 EXMC_CLK period 2 HCLK period 0xF EXMC_CLK pe...

Page 594: ...ddress setup time 16 HCLK SRAM NOR Flash write timing configuration registers EXMC_SNWTCFGx x 0 1 2 3 Address offset 0x104 8 x X 0 1 2 and 3 Reset value 0x0FFF FFFF This register has to be accessed by word 32 bit This register is meaningful only when the EXMODEN bit in EXMC_SNCTLx is set to 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WASYNCMOD 1 0 Reserved WBUSLAT 3 0 rw rw 15 14 13...

Page 595: ... time This field is used to set the time of address hold phase which onlyused in mode D and multiplexed mode 0x0 Reserved 0x1 Address hold time 2 HCLK 0xF Address hold time 16 HCLK 3 0 WASET 3 0 Address setup time This field is used to set the time of address setup phase Note Meaningful only in asynchronous access of SRAM ROM NOR Flash 0x0 Address setup time 1 HCLK 0x1 Address setup time 2 HCLK 0x...

Page 596: ...ALE to RE delay 16 HCLK 12 9 CTR 3 0 CLE to RE delay 0x0 CLE to RE delay 1 HCLK 0x1 CLE to RE delay 2 HCLK 0xF CLE to RE delay 16 HCLK 8 7 Reserved Must be kept at reset value 6 ECCEN ECC enable 0 Disable ECC and reset EXMC_NECCx 1 Enable ECC 5 4 NDW 1 0 NAND bank memory data bus width 00 8 bits 01 16 bits Others Reserved Note for PC CF card 16 bit bus width must be selected 3 NDTP NAND bank memor...

Page 597: ... only after the FIFO empty status flag is raised 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FFEPT INTFEN INTHEN INTREN INTFS INTHS INTRS r rw rw rw rw rw rw Bits Fields Description 31 7 Reserved Must be kept at reset value 6 FFEPT FIFO empty flag 0 FIFO is not empty 1 FIFO is empty 5 INTFEN Interrupt falling edge detection enable 0 Disab...

Page 598: ...8 27 26 25 24 23 22 21 20 19 18 17 16 COMHIZ 7 0 COMHLD 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMWAIT 7 0 COMSET 7 0 rw rw Bits Fields Description 31 24 COMHIZ 7 0 Common memory data bus HiZ time The bits are defined as time of bus keep high impedance state after writing the data 0x00 COMHIZ 1 HCLK 0xFE COMHIZ 255 HCLK 0xFF Reserved 23 16 COMHLD 7 0 Common memory hold time After sending ...

Page 599: ... space of the PC Card or to access the NAND Flash for the last address or command write access if another timing must be applied 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ATTHIZ 7 0 ATTHLD 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATTWAIT 7 0 ATTSET 7 0 rw rw Bits Fields Description 31 24 ATTHIZ 7 0 Attribute memory data bus HiZ time The bits are defined as time of bus keep high impeda...

Page 600: ...OTCFG3 Address offset 0xB0 Reset value 0xFCFC FCFC This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IOHIZ 7 0 IOHLD 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IOWAIT 7 0 IOSET 7 0 rw rw Bits Fields Description 31 24 IOHIZ 7 0 IO space data bus HiZ time The bits are defined as time of bus keep high impedance state after writing the data 0x00 IOHIZ...

Page 601: ...00 IOSET 1 HCLK 0xFF IOSET 256 HCLK NAND Flash ECC registers EXMC_NECCx x 1 2 Address offset 0x54 0x20 x Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ECC 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ECC 15 0 r Bits Fields Description 31 0 ECC 31 0 ECC result ECCSZ 2 0 NAND Flash page size ECC bits 0b000 256 ECC 21 0 0b001 ...

Page 602: ...ted firstly Three complete messages can be stored in every FIFO The FIFOs are managed completely by hardware Two receiving FIFOs are used by hardware to store the incoming messages In addition the CAN controller provides all hardware functions which supports the time triggered communication option in safety critical applications 22 2 Characteristics Supports CAN protocols version 2 0A B Baud rates...

Page 603: ...leep working mode is the default modeafter reset In sleep working mode the CAN is in the low power status and the CAN clock is stopped When SLPWMOD bit in CAN_CTL register is set the CAN enters the sleep working mode Then the SLPWS bit in CAN_STAT register is set by hardware To leave sleep working mode automatically the AWU bit in CAN_CTL register is set and the CAN bus activity is detected To lea...

Page 604: ...L register and wait the current transmission or reception completed Normal working mode to initial working mode set IWMOD bit in CAN_CTL register and wait the current transmission or reception completed 22 3 2 Communication modes The CAN interface has four communication modes Silent communication mode Loopback communication mode Loopback and silent communication mode Normal communication mode Sile...

Page 605: ...n mode while clearing them to leave Loopback and silent communication mode is used for self test The TX pin holds in recessive state The RX pin holds in high impedance state Normal communication mode Normal communication mode is the default communication mode when the LCMOD and SCMOD bits in CAN_BT register are cleared 22 3 3 Data transmission Transmission register Three transmit mailboxes are use...

Page 606: ...TF mailbox transmit finished Typically MTF is set when the frame in the transmit mailbox has been sent MTFNERR mailbox transmit finished with no error MTFNERR is set when the frame in the transmit mailbox has been sent without any error MAL mailbox arbitration lost MALis set when the frame transmission is failed due to the arbitration lost MTE mailbox transmit error MTE is set when the frame trans...

Page 607: ... lowest identifier has the highest priority of transmission If the identifiers are equal the lower mailbox number will be scheduled firstly 22 3 4 Data reception Reception register Two Rx FIFOs are used for the application Rx FIFOs are managed by five registers CAN_RFIFOx CAN_RFIFOMIx CAN_RFIFOMPx CAN_RFIFOMDATA0x and CAN_RFIFOMDATA1x FIFO s status and operation can be handled by CAN_RFIFOx regist...

Page 608: ...ves after the FIFO has held three frames the RFObit in CAN_RFIFOx register will be set and it indicates FIFOx is overrun If the RFOD bit in CAN_CTL register is set the new frame is discarded If the RFOD bit in CAN_CTL register is reset the new frame is stored into the Rx FIFO and the last frame in the Rx FIFO is discarded Steps of receiving a message Step 1 Check the number of frames in the Rx FIF...

Page 609: ...F FT 0 FDATA0 31 21 FDATA0 20 3 FDATA0 2 0 ID Mask Figure 22 8 16 bit mask mode filter FDATA0 15 5 FDATA0 4 0 SFID 10 0 FT FF EFID 17 15 FDATA1 15 5 FDATA1 4 0 SFID 10 0 FT FF EFID 17 15 FDATA0 31 21 FDATA0 20 16 FDATA1 31 21 FDATA1 20 16 ID Mask List mode The filter consists of frame identifiers The filter can determine whether a frame will be discarded or not When one frame arrived the filter wi...

Page 610: ...32bit ID 1 F1DATA1 32bit ID 2 Associated FIFO 28 banks can be associated with FIFO0 or FIFO1 If the bank is associated with FIFO0 the frames passed the bank will be stored in the FIFO0 Active The filterbank needstobeactivatedif thebank isto beused otherwise thefilterbankshould be left deactivated Filtering index Each filter number corresponds to a filtering rule When the frame which is associated ...

Page 611: ...its ID 6 F7DATA1 15 0 16bits ID 7 F6DATA1 15 0 16bits ID 7 F7DATA1 31 16 16bits ID 8 F6DATA1 31 16 16bits ID 8 8 F8DATA0 15 0 16bits ID Yes 9 10 F10DATA0 15 0 16bits ID No 9 F8DATA0 31 16 16bits ID 10 F10DATA0 31 16 16bits Mask F8DATA1 15 0 16bits ID 11 F10DATA1 15 0 16bits ID 10 F8DATA1 31 16 16bits ID 12 F10DATA1 31 16 16bits Mask 9 F9DATA0 15 0 16bits ID Yes 13 11 F11DATA0 15 0 16bits ID No 11 ...

Page 612: ...ia MTFNERR MAL and MTE Bit time On thebit level theCANprotocol usessynchronousbit transmission This notonlyenhances the transmitting capacity but also requires a sophisticated method of bit synchronization While bit synchronization in a character oriented transmission asynchronous is performed upon the reception which the start bit is available with each character the synchronous transmission prot...

Page 613: ...l Bit Time CAN protocol SYNG_SEG BIT SEGMENT 1 BS1 BIT SEGMENT 2 BS2 CAN The resynchronization Jump Width SJW it can be lengthened or shortened to compensate for the Synchronization error of the CAN network node It is programmable from 1 to 4 time quanta A valid edge is defined as the first togglein a bit time from dominant to recessive bus level before the controller sends a recessive bit If a va...

Page 614: ...state to detect the Bus Off recovery sequence defined by CAN protocol when CAN_RX detects 128 consecutive 11 bit recessive bits before automatic recovery If ABOR is set it will be automatically recovered when a Bus Off recovery sequence is detected If ABOR is cleared CAN controller must beconfigured to enter initialization mode by setting IWMOD bit in CAN_CTL register thenexit and enter nomal mode...

Page 615: ... CAN_RFIFO1register are not 00 and RFNEIE1 in CAN_INTEN register is set Rx FIFO1 full RFF1 bit in the CAN_RFIFO1 register is set and RFFIE1 in CAN_INTEN register is set Rx FIFO1 overrun RFO1 bit in the CAN_RFIFO1 register is set and RFOIE1 in CAN_INTEN register is set Error and working mode change interrupt The error and working mode change interrupt canbe generated by the following conditions Err...

Page 616: ...CTL0 register is set this bit defines the CAN controller is in debug freezing mode or normal working mode If the CANx_HOLD in DBG_CTL0 register is cleared this bit takes no effect 0 CAN reception and transmission work normal even during debug 1 CAN reception and transmission stop working during debug 15 SWRST Software reset 0 No effect 1 Reset CAN to enter sleep working mode This bit is automatica...

Page 617: ...dentifier has higher priority 1 Order with first in and first out 1 SLPWMOD Sleep working mode If this bit is set by software the CAN enters sleep working mode after current transmission or reception is completed This bit can be cleared by software or hardware If AWU bit in CAN_CTL register is set this bit is cleared by hardware when CAN bus activity is detected 0 Disable sleep working mode 1 Enab...

Page 618: ...t is set by the following events The BOERR bit in CAN_ERR register is set and BOIE bit in CAN_INTEN register is set Or the PERR bit in CAN_ERR register is set and PERRIE bit in CAN_INTEN register is set Or the WERR bit in CAN_ERR register is set and WERRIE bit in CAN_INTEN register is set Or the ERRN bits in CAN_ERR register are set to 1 to 6 not 0 and not 7 and ERRNIE in CAN_INTEN register is set...

Page 619: ...accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMLS2 TMLS1 TMLS0 TME2 TME1 TME0 NUM 1 0 MST2 Reserved MTE2 MAL2 MTFNER R2 MTF2 r r r r r r r rs rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MST1 Reserved MTE1 MAL1 MTFNER R1 MTF1 MST0 Reserved MTE0 MAL0 MTFNER R0 MTF0 rs rc_w1 rc_w1 rc_w1 rc_w1 rs rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 TMLS2 Tra...

Page 620: ...when next transmit starts 18 MAL2 Mailbox 2 arbitration lost This bit is set when the arbitration lost occurs This bit is reset by writting 1 to this bit or MTF2 bit in CAN_TSTAT register This bit is reset by hardware when next transmit starts 17 MTFNERR2 Mailbox 2 transmit finished with no error This bit is set when the transmission finishes and no error occurs Thisbit is reset by writting 1 to t...

Page 621: ... 1 Mailbox 1 transmit finished 7 MST0 Mailbox 0 stop transmitting This bit is set by the software to stop mailbox 0 transmitting This bit is reset by the hardware when the mailbox 0 is empty 6 4 Reserved Must be kept at reset value 3 MTE0 Mailbox 0 transmit error This bit is set by hardware when the transmit error occurs This bit is reset by writting 1 to this bit or MTF0 bit in CAN_TSTAT register...

Page 622: ...s bit is set by software to start dequeuing a frame from Rx FIFO0 This bit is reset by hardware when the dequeuing is done 4 RFO0 Rx FIFO0 overfull This bit is set by hardware when Rx FIFO0 is overfull and reset by software when writting 1 to this bit 0 The Rx FIFO0 is not overfull 1 The Rx FIFO0 is overfull 3 RFF0 Rx FIFO0 full This bit is set by hardware when Rx FIFO0 is full and reset by softwa...

Page 623: ... by writting 1 to this bit 0 The Rx FIFO1 is not overfull 1 The Rx FIFO1 is overfull 3 RFF1 Rx FIFO1 full This bit is set by hardware when Rx FIFO1 is full and reset by writting 1 to this bit 0 The Rx FIFO1 is not full 1 The Rx FIFO1 is full 2 Reserved Must be kept at reset value 1 0 RFL1 1 0 Rx FIFO1 length These bits are the length of the Rx FIFO1 22 4 6 Interrupt enable register CAN_INTEN Addre...

Page 624: ...rrupt disabled 1 Bus Off interrupt enabled 9 PERRIE Passive error interrupt enable 0 Passive error interrupt disabled 1 Passive error interrupt enabled 8 WERRIE Warning error interrupt enable 0 Warning errorinterrupt disabled 1 Warning errorinterrupt enabled 7 Reserved Must be kept at reset value 6 RFOIE1 Rx FIFO1 overfull interrupt enable 0 Rx FIFO1 overfull interrupt disabled 1 Rx FIFO1 overfull...

Page 625: ... 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RECNT 7 0 TECNT 7 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ERRN 2 0 Reserved BOERR PERR WERR rw r r r Bits Fields Descriptions 31 24 RECNT 7 0 Receive error count defined by the CAN standard 23 16 TECNT 7 0 Transmit error count defined by the CAN standard 15 7 Reserved Must be kept at reset value 6 4 ERRN 2 0 Error number These bits indicat...

Page 626: ...CMOD LCMOD Reserved SJW 1 0 Reserved BS2 2 0 BS1 3 0 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BAUDPSC 9 0 rw Bits Fields Descriptions 31 SCMOD Silent communication mode 0 Silent communication disabled 1 Silent communication enabled 30 LCMOD Loopback communication mode 0 Loopback communication disabled 1 Loopback communication enabled 29 26 Reserved Must be kept at reset value ...

Page 627: ...FID 28 1 8 The frame identifier SFID 10 0 Standard format frame identifier EFID 28 18 Extended format frame identifier 20 16 EFID 17 13 The frame identifier EFID 17 13 Extended format frame identifier 15 3 EFID 12 0 The frame identifier EFID 12 0 Extended format frame identifier 2 FF Frame format 0 Standard format frame 1 Extended format frame 1 FT Frame type 0 Data frame 1 Remote frame 0 TEN Tran...

Page 628: ...mp disabled 1 Time stamp enabled The TS 15 0 will be transmitted in the DB6 and DB7 in DL This bit is available when the TTC bit in CAN_CTL is set 7 4 Reserved Must be kept at reset value 3 0 DLENC 3 0 Data length code DLENC 3 0 is the number of bytes in a frame 22 4 11 Transmit mailbox data0 register CAN_TMDATA0x x 0 2 Address offset 0x188 0x198 0x1A8 Reset value 0xXXXX XXXX This register has to ...

Page 629: ... 0 DB4 7 0 rw rw Bits Fields Descriptions 31 24 DB7 7 0 Data byte 7 23 16 DB6 7 0 Data byte 6 15 8 DB5 7 0 Data byte 5 7 0 DB4 7 0 Data byte 4 22 4 13 Receive FIFO mailbox identifier register CAN_RFIFOMIx x 0 1 Address offset 0x1B0 0x1C0 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SFID 10 0 EFID 28 18 EFID 17 13 r r 15 14 ...

Page 630: ...er CAN_RFIFOMPx x 0 1 Address offset 0x1B4 0x1C4 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TS 15 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FI 7 0 Reserved DLENC 3 0 r r Bits Fields Descriptions 31 16 TS 15 0 Time stamp The time stamp of frame in transmit mailbox 15 8 FI 7 0 Filtering index The index of the filter which t...

Page 631: ... 7 0 Data byte 0 22 4 16 Receive FIFO mailbox data1 register CAN_RFIFOMDATA1x x 0 1 Address offset 0x1BC 0x1CC Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB7 7 0 DB6 7 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB5 7 0 DB4 7 0 r r Bits Fields Descriptions 31 24 DB7 7 0 Data byte 7 23 16 DB6 7 0 Data byte 6 15 8 DB5 7 0 D...

Page 632: ...k disable 0 Filter lock enabled 1 Filter lock disabled 22 4 18 Filter mode configuration register CAN_FMCFG Just for CAN0 Address offset 0x204 Reset value 0x0000 0000 This register has to be accessed by word 32 bit This register can be modified only when FLD bit in CAN_FCTL register is set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FMOD27 FMOD26 FMOD25 FMOD24 FMOD23 FMOD22 FMOD21 FMO...

Page 633: ...reset value 27 0 FSx Filter scale 0 Filter x with 16 bit scale 1 Filter x with 32 bit scale 22 4 20 Filter associated FIFO register CAN_FAFIFO Just for CAN0 Address offset 0x214 Reset value 0x0000 0000 This register has to be accessed by word 32 bit This register can be modified only when FLD bit in CAN_FCTL register is set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FAF27 FAF26 FAF25...

Page 634: ...0 FWx Filter working 0 Filter x working disabled 1 Filter x working enabled 22 4 22 Filter x data y register CAN_FxDATAy x 0 27 y 0 1 Just for CAN0 Address offset 0x240 8 x 4 y x 0 27 y 0 1 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FD31 FD30 FD29 FD28 FD27 FD26 FD25 FD24 FD23 FD22 FD21 FD20 FD19 FD18 FD17 FD16 rw rw rw r...

Page 635: ...tiation Protocol and SRP Session Request Protocol Supports all the 4 types of transfer control bulk interrupt and isochronous Includes a USB transaction scheduler in host mode to handle USB transaction request efficiently Includes a 1 25KB FIFO RAM Supports 8 channels in host mode Includes 2 transmit FIFOs periodic and non periodic and a receive FIFO shared by all channels in host mode Includes 4 ...

Page 636: ...odes USBFS could be operated as a host a device or a DRD Dual role Device It contains an internal full speed PHY The maximum speed supported by USBFS is full speed The internal PHY supports Full Speed and Low Speed in host mode supports Full speed in device mode and supports OTG mode with HNP and SRP The USB clock used by the USBFS shouldbe48MHz The48MHzUSB clock is generatedfrom internalclocksins...

Page 637: ...configured by VBUSIG bit in USBFS_GCCFG register So if the device is not necessaryto detect thevoltageonVBUS pin itcouldbeconfiguredbysettingtheVBUSIG bit then the VBUS pin can befreed for other uses Otherwise the VBUS connection cannot be omitted and USBFS continuously monitor the VBUS voltage It will immediately switch off the pull up resistor on DP line once that the VBUS voltage falls below th...

Page 638: ...isconnected state After a connectionis detected USB port changes into connected state The USB port changes into enabled state after a port reset is performed on USB bus Figure 23 4 State transition diagram of host port Power off Dis connected Connected Enabled set PP bit clear PP bit or VBUS is not valid in OTG host mode connection event disconnection event port reset Clear PP bit disconnection ev...

Page 639: ...nslator at each 1ms in full speed links Once that USBFS enterred into enabled state it will send the SOF packet periodically which the time is defined in USB 2 0 protocol In addition application may adjust the length of a frame by writing FRI filed in USBFS_HFT registers The FRI bits define the number of USB clock cycles in a frame so its value should be calculated based on the frequency of USB cl...

Page 640: ...in the current frame and if this is a periodic request USBFS stops processing the periodic queue and starts to process non periodic request If this is a non periodic queue the USBFS will stop processing any queue and wait until the end of current frame 23 5 3 USB device function USB Device Connection In device mode USBFS stays at power off state after initialization After connecting to a USB host ...

Page 641: ... registers canbe used to get current bus time and position information 23 5 4 OTG function overview USBFS supports OTG function described in OTG protocol 1 3 OTG function includes SRP and HNP protocols A Device and B Device A Device is an OTG capable USB device with a Standard A or Micro A plug inserted into its receptacle The A Device supplies power to VBUS and it is host at the start of a sessio...

Page 642: ...us activity As is described in OTG protocol an OTG device must compare VBUS voltage with several threshold values and the compared result should be reported in ASV and BSV bits in USBFS_GOTGCS register Set SRPREQ bit in USBFS_GOTGCS register to start a SRP request when USBFS is in B Device OTG mode USBFS will generate a success flag SRPS in USBFS_GOTGCS register if the SRP request successfully Whe...

Page 643: ...hare the same FIFO It is important for USBFS to know which channel the current pushed packet belongs to Rx FIFO is also able to be accessed by using USBFS_GRSTATR USBFS_GRSTATP register Figure 23 6 Host mode FIFO access register map CH0 FIFO Write Read CH1 FIFO Write Read 1000h 1FFFh CH7 FIFO Write Read 2000h 2FFFh 8000h 8FFFh Device mode In device mode the data FIFO is divided into several parts ...

Page 644: ... 23 8 Device mode FIFO access register map describes the register memory area where thedataFIFOcanaccess Theaddressesinthefigureareaddressedinbytes Eachendpoint has its own FIFO access register space Rx FIFO is also able to be accessed by using USBFS_GRSTATR USBFS_GRSTATP register Figure 23 8 Device mode FIFO access register map IEP0 FIFO Write IEP1 FIFO Write 1000h 1FFFh IEP3 FIFO Write 2000h 2FF...

Page 645: ...then read PE bit to ensure that the port is successfully enabled Read PS 1 0 bits to get the connected device s speed and then program USBFS_HFT register to change the SOF interval if needed Channel initialization and enable sequence 1 Program USBFS_HCHxCTL registers with desired transfer type direction packet size etc Ensure that CEN and CDIS bits keep cleared during configuration 2 Program USBFS...

Page 646: ...ts the IN transaction on USB bus 6 If the IN transaction is finished successfully ACK handshake received USBFS pushes the received data packet into the Rx FIFO and triggers ACK flag Otherwise the status flag NAK reports the transactionresult 7 If the IN transaction described in step 5 is successful and PCNT is larger than 1 in step2 return to step 3 and continues to receive the remaining packets I...

Page 647: ...ode Global register initialization sequence 1 Program USBFS_GAHBCS register according to application s demand such as the TxFIFO s empty threshold etc GINTEN bit should be kept cleared at this time 2 Program USBFS_GUSBCS register according to application s demand such as the operation mode host device or OTG and some parameters of OTG and USB protocols 3 Program USBFS_GCCFG register according to a...

Page 648: ...ers is cleared IN transfers operation sequence 1 Initialize USBFS global registers 2 Initialize and enable the IN endpoint 3 Write packets into the endpoint s Tx FIFO At any time a data packet is written into the FIFO USBFS decreases the TLEN field in USBFS_DIEPxLEN register by the written packet s size 4 When an IN token received USBFS transmits the data packet and after the transaction finishes ...

Page 649: ...ion interrupt Host or device mode DISCIF Disconnect interrupt flag Host Mode IDPSC ID pin status change Host or device mode PTXFEIF Periodic Tx FIFO empty interrupt flag Host Mode HCIF Host channels interrupt flag Host Mode HPIF Host port interrupt flag Host Mode ISOONCIF PXNCI F Periodic transfer Not Complete Interrupt flag Isochronous OUT transfer Not Complete Interrupt Flag Host or device mode ...

Page 650: ... OTG interrupt flag Host or device mode MFIF Mode fault interrupt flag Host or device mode Wake up interrupt can be triggered when USBFS is in suspend state even if when the USBFS s clocks are stopped The source of the wake up interrupt is WKUPIF bit in USBHS_GINTF register ...

Page 651: ...et value 19 BSV B Session Valid described in OTG protocol 0 Vbus voltage level of a OTG B Device is below VBSESSVLD 1 Vbus voltage level of a OTG B Device is not below VBSESSVLD Note Only accessible in OTG B Device mode 18 ASV A Session valid A host mode transceiver status 0 Vbus voltage level of a OTG A Device is below VASESSVLD 1 Vbus voltage level of a OTG A Device is below VASESSVLD The A Devi...

Page 652: ...vice 0 HNP function is not enabled 1 HNP function is enabled Note Only accessible in host mode 9 HNPREQ HNP request This bit is set by software to start a HNP on the USB This bit can be cleared when HNPEND bit in USBFS_GOTGINTF register is set by writing zero to it or clearing the HNPEND bit in USBFS_GOTGINTF register 0 Don t send HNP request 1 Send HNP request Note Only accessible in device mode ...

Page 653: ...d rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HNPEND SRPEND Reserved SESEND Reserved rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 DF Debounce finish Set by USBFS when the debounce during device connection is done Note Only accessible in host mode 18 ADTO A Device timeout Set by USBFS when the A Device s waiting for a B Device connect...

Page 654: ...FS_GAHBCS Address offset 0x0008 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PTXFTH TXFTH Reserved GINTEN rw rw rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 PTXFTH Periodic Tx FIFO threshold 0 PTXFEIF will be triggered when the periodic trans...

Page 655: ...s register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FDM FHM Reserved rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UTT 3 0 HNPCEN SRPCEN Reserved TOC 2 0 rw r rw r rw rw Bits Fields Descriptions 31 Reserved Must be kept at reset value 30 FDM Force device mode Setting this bit will force the core to device mode irrespective of the USBFS...

Page 656: ...ability enable Controls whether the SRP capability is enabled 0 SRP capability is disabled 1 SRP capability is enabled Note Accessible in both device and host modes 7 3 Reserved Must be kept at reset value 2 0 TOC 2 0 Timeout calibration USBFS always uses time out value required in USB 2 0 when waiting for a packet Application may use TOC 2 0 to add the value is in terms of PHY clock The frequency...

Page 657: ...automatically clears this bit after the flush process completes After setting this bit application should wait until this bit is cleared before any other operation on USBFS Note Accessible in both device and host modes 4 RXFF Rx FIFO flush Application set this bit to flush data Rx FIFO Hardware automatically clears this bit after the flush process completes After setting this bit application shoul...

Page 658: ... rc_w1 rc_w1 rc_w1 rc_w1 r r r rc_w1 rc_w1 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EOPFIF ISOOPDIF ENUMF RST SP ESP Reserved GONAK GNPINAK NPTXFEIF RXFNEIF SOF OTGIF MFIF COPM rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r r r r rc_w1 r rc_w1 r Bits Fields Descriptions 31 WKUPIF Wakeup interrupt flag This interrupt is triggered when a resume signal in device mode or a remote wakeup signal in host mode is...

Page 659: ...are cleared Note Only accessible in host mode 23 22 Reserved Must be kept at reset value 21 PXNCIF ISOONCIF Periodic transfer Not Complete Interrupt flag USBFS sets this bit when there are periodic transactions for current frame not completed at the end of frame Host mode Isochronous OUT transfer Not Complete Interrupt Flag At the end of a periodic frame defined by EOPFT bit in USBFS_DCFG USBFS wi...

Page 660: ...t into Rx FIFO because the FIFO doesn t have enough space Note Only accessible in device mode 13 ENUMF Enumeration finished USBFS sets this bit after the speed enumeration finishes Read USBFS_DSTAT register to get the current device speed Note Only accessible in device mode 12 RST USB reset USBFS sets this bit when it detects a USB reset signal on bus Note Only accessible in device mode 11 SP USB ...

Page 661: ...sible in both host and device modes 2 OTGIF OTG interrupt flag USBFS sets this bit when the flags in USBFS_GOTGINTF register generate an interrupt Software should read USBFS_GOTGINTF register to get the source of this interrupt This bit is cleared after the flags in USBFS_GOTGINTF causing this interrupt are cleared Note Accessible in both host and device modes 1 MFIF Mode fault interrupt flag USBF...

Page 662: ...odes 30 SESIE Session interrupt enable 0 Disable session interrupt 1 Enable session interrupt Note Accessible in both host and device modes 29 DISCIE Disconnect interrupt enable 0 Disable disconnect interrupt 1 Enable disconnect interrupt Note Only accessible in device mode 28 IDPSCIE ID pin status change interrupt enable 0 Disable connector ID pin status interrupt 1 Enable connector ID pin status...

Page 663: ...1 Enable isochronous IN transfer not complete interrupt Note Only accessible in device mode 19 OEPIE OUT endpoints interrupt enable 0 Disable OUT endpoints interrupt 1 Enable OUT endpointsinterrupt Note Only accessible in device mode 18 IEPIE IN endpoints interrupt enable 0 Disable IN endpointsinterrupt 1 Enable IN endpoints interrupt Note Only accessible in device mode 17 16 Reserved Must be kept...

Page 664: ...ective interrupt enable 0 Disable global non periodicIN NAK effective interrupt 1 Enable global non periodic IN NAK effective interrupt Note Only accessible in device mode 5 NPTXFEIE Non periodic Tx FIFO empty interrupt enable 0 Disable non periodic Tx FIFO empty interrupt 1 Enable non periodic Tx FIFO empty interrupt Note Only accessible in Host mode 4 RXFNEIE Receive FIFO non empty interrupt ena...

Page 665: ...es Software should only read this register after when Receive FIFO non empty interrupt flag bit of the global interrupt flag register RXFNEIF bit in USBFS_GINTF is triggered This register has to be accessed by word 32 bit Host mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RPCKST 3 0 DPID r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPID BCOUNT 10 0 CNUM 3 0 r r r Bits Fields Descripti...

Page 666: ...Descriptions 31 21 Reserved Must be kept at reset value 20 17 RPCKST 3 0 Received packet status 0001 Global OUT NAK generates an interrupt 0010 OUT data packet received 0011 OUT transfer completed generates an interrupt 0100 SETUP transaction completed generates an interrupt 0110 SETUP data packet received Others Reserved 16 15 DPID 1 0 Data PID The Data PID of the received OUT data packet 00 DATA...

Page 667: ...ds Descriptions 31 16 Reserved Must be kept at reset value 15 0 RXFD 15 0 Rx FIFO depth In terms of 32 bit words 1 RXFD 1024 Host non periodic transmit FIFO length register Device IN endpoint 0 transmit FIFO length USBFS_HNPTFLEN _DIEP0TFLEN Address offset 0x028 Reset value 0x0200 0200 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HNPTXFD IEP0TXFD ...

Page 668: ...is in term of 32 bit words Host non periodic transmit FIFO queue status register USBFS_HNPTFQSTAT Address offset 0x002C Reset value 0x0008 0200 This register reports the current status of the non periodic Tx FIFO and request queue The request queue holds IN OUT or other request entries in host mode Note In Device mode this register is not valid This register has to be accessed by word 32 bit 31 30...

Page 669: ...ries n n entries 0 n 8 Others Reserved 15 0 NPTXFS 15 0 Non periodic Tx FIFO space The remaining space of the non periodictransmit FIFO In terms of 32 bit words 0 Non periodicTx FIFO is full 1 1 word 2 2 words n n words 0 n NPTXFD Others Reserved Global core configuration register USBFS_GCCFG Address offset 0x0038 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 ...

Page 670: ...e Comparer enable 0 VBUS B device comparer disabled 1 VBUS B device comparer enabled 18 VBUSACEN The VBUS A device Comparer enable 0 VBUS A device comparer disabled 1 VBUS A device comparer enabled 17 Reserved Must be kept at reset value 16 PWRON Power on This bit is the power switch for the internal embedded Full Speed PHY 0 Embedded Full Speed PHY power off 1 Embedded Full Speed PHY power on 15 ...

Page 671: ...2 21 20 19 18 17 16 HPTXFD 15 0 r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HPTXFSAR 15 0 r rw Bits Fields Descriptions 31 16 HPTXFD 15 0 Host Periodic Tx FIFO depth In terms of 32 bit words 1 HPTXFD 1024 15 0 HPTXFSAR 15 0 Host periodic Tx FIFO RAM start address The start address for host periodic transmit FIFO RAM is in term of 32 bit words Device IN endpoint transmit FIFO length register USBFS_D...

Page 672: ...M start address The start address for IN endpoint transmit FIFOx is in term of 32 bit words 23 7 2 Host control and status registers Host control register USBFS_HCTL Address offset 0x0400 Reset value 0x0000 0000 This register configures the core after power on in host mode Do not modify it after host initialization This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20...

Page 673: ... 6 5 4 3 2 1 0 FRI 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 FRI 15 0 Frame interval This value describes the frame time in terms of PHY clocks Each time when port is enabled after a port reset operation USBFS use a proper value according to the current speed and software can write to this field to change the value This value should be calculated using the fr...

Page 674: ...IFO queue status register USBFS_HPTFQSTAT Address offset 0x0410 Reset value 0x0008 0200 This register reports the current status of the host periodic Tx FIFO and request queue The request queue holds IN OUT or other request entries in host mode This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PTXREQT 7 0 PTXREQS 7 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 675: ...pace The remaining space of the periodic transmit FIFO In terms of 32 bit words 0 periodic Tx FIFO is full 1 1 word 2 2 words n n words 0 n PTXFD Others Reserved Host all channels interrupt register USBFS_HACHINT Address offset 0x0414 Reset value 0x0000 0000 When a channel interrupt is triggered USBFS set corresponding bit in this register and software should read this register to know which chann...

Page 676: ...er This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CINTEN 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 CINTEN 7 0 Channel interrupt enable 0 Disable channel n interrupt 1 Enable channel n interrupt Each bit represents a channel Bit 0 for channel 0 bit 7 for chann...

Page 677: ...his bit should be set before a port is used Because USBFS doesn t have power supply ability it only uses this bit to know whether the port is in powered state Software should ensure the true power supply on VBUS before setting this bit 0 Port is powered off 1 Port is powered on 11 10 PLST Port line status Report the current state of USB data lines Bit 10 State of DP line Bit 11 State of DM line 9 ...

Page 678: ...by the core when the status of the Port enable bit 2 in this register changes 2 PE Port Enable This bit is automatically set by USBFS after a USB reset signal finishes and cannot be set by software This bit is cleared by the following events A disconnect condition Software clearing this bit 0 Port disabled 1 Port enabled 1 PCD Port connect detected Set by USBFS when a device connection is detected...

Page 679: ... guide to disable or enable a channel 29 ODDFRM Odd frame For periodic transfers interrupt or isochronous transfer this bit controls that whether in an odd frame or even frame this channel s transaction is desired to be processed 0 Even frame 1 Odd frame 28 22 DAR Device address The address of the USB device that this channel wants to communicate with 21 20 Reserved Must be kept at reset value 19 ...

Page 680: ...e flag bits in this register are all set by hardware and cleared by writing 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DTER REQOVR BBER USBER Reserved ACK NAK STALL Reserved CH TF rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 11 Reserved Must be kept at...

Page 681: ...fer finished All the transactions of this channel finish successfully and no error occurs For IN channel this flag will be triggered after PCNT bits in USBFS_HCHxLEN register reach zero For OUT channel this flag will be triggered when software reads and pops a TF status entry from the RxFIFO Host channel x interrupt enable register USBFS_HCHxINTEN x 0 7 where x channel number Address offset 0x050C...

Page 682: ...IE Babble error interrupt enable 0 Disable babble error interrupt 1 Enable babble error interrupt 7 USBERIE USB bus error interrupt enable 0 Disable USB bus error interrupt 1 Enable USB bus error interrupt 6 Reserved Must be kept at reset value 5 ACKIE ACK interrupt enable 0 Disable ACK interrupt 1 Enable ACK interrupt 4 NAKIE NAK interrupt enable 0 Disable NAK interrupt 1 Enable NAK interrupt 3 S...

Page 683: ...ID of the first transmitted packet For IN transfers this field controls the expected Data PID of the first received packet and DTERR will be triggered if the Data PID doesn t match After the transfer starts USBFS changes and toggles this field automaticallyfollowing the USB protocol 00 DATA0 10 DATA1 11 SETUP For control transfer only 01 Reserved 28 19 PCNT 9 0 Packet count The number of data pack...

Page 684: ...eration Do not change this register after device initialization This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EOPFT 1 0 DAR 6 0 Res NZLSOH DS 1 0 rw rw rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 11 EOPFT 1 0 End of periodic frame time This field defines the pe...

Page 685: ...ed Others Reserved Device control register USBFS_DCTL Address offset 0x0804 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved POIF CGONAK SGONAK CGINAK SGINAK Reserved GONS GINS SD RWKUP rw w w w w r r rw rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset valu...

Page 686: ...nd doesn t save the incoming OUT data packet 2 GINS Global IN NAK status 0 The response to IN transaction is decided by Tx FIFO status endpoint s NAK and STALL bits 1 USBFS always responses to IN transaction with a NAK handshake 1 SD Soft disconnect Software can use this bit to generate a soft disconnect condition on USB bus After this bit is set USBFS switches off the pull up resistor on DP line ...

Page 687: ...d 11 Full speed Others reserved 0 SPST Suspend status This bit reports whether device is in suspend state 0 Device is in suspend state 1 Device is not in suspend state Device IN endpoint common interrupt enable register USBFS_DIEPINTEN Address offset 0x810 Reset value 0x0000 0000 This register contains the interrupt enable bits for the flags in USBFS_DIEPxINTF register If a bit in this register is...

Page 688: ...1 Enable control In timeout interrupt 2 Reserved Must be kept at reset value 1 EPDISEN Endpoint disabled interrupt enable bit 0 Disable endpoint disabled interrupt 1 Enable endpoint disabled interrupt 0 TFEN Transfer finished interrupt enable bit 0 Disable transfer finished interrupt 1 Enable transfer finished interrupt Device OUT endpoint common interrupt enable register USBFS_DOEPINTEN Address o...

Page 689: ...TUP phase finished Onlyfor controlOUT endpoint interrupt enable bit 0 Disable SETUP phase finished interrupt 1 Enable SETUP phase finished interrupt 2 Reserved Must be kept at reset value 1 EPDISEN Endpoint disabled interrupt enable bit 0 Disable endpoint disabled interrupt 1 Enable endpoint disabled interrupt 0 TFEN Transfer finished interrupt enable bit 0 Disable transfer finished interrupt 1 En...

Page 690: ...t bits Each bit represents an IN endpoint Bit 0 for IN endpoint 0 bit 3 for IN endpoint 3 Device all endpoints interrupt enable register USBFS_DAEPINTEN Address offset 0x081C Reset value 0x0000 0000 This register can be used by software to enable or disable an endpoint s interrupt Only the endpoint whose corresponding bit in this register is set is able to cause the endpoint interrupt flag OEPIF o...

Page 691: ... bit represents an IN endpoint Bit 0 for IN endpoint 0 bit 3 for IN endpoint 3 Device VBUS discharge time register USBFS_DVBUSDT Address offset 0x0828 Reset value 0x0000 17D7 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DVBUSDT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset valu...

Page 692: ...et value 11 0 DVBUSPT 11 0 Device VBUS pulsing time This field defines the pulsing time for VBUS The true pulsing time is 1024 DVBUSPT 11 0 TUSBCLOCK where TUSBCLOCK is the period time of USB clock Device IN endpoint FIFO empty interrupt enable register USBFS_DIEPFEINTEN Address offset 0x0834 Reset value 0x0000 0000 This register contains the enable bits for the Tx FIFO empty interrupts of IN endp...

Page 693: ...FS_DIEP0CTL Address offset 0x0900 Reset value 0x0000 8000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EPEN EPD Reserved SNAK CNAK TXFNUM 3 0 STALL Reserved EPTYPE 1 0 NAKS Reserved rs rs w w rw rs r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EPACT Reserved MPL 1 0 r rw Bits Fields Descriptions 31 EPEN Endpoint enable Set by the application and cle...

Page 694: ...Must be kept at reset value 19 18 EPTYPE 1 0 Endpoint type This field is fixed to 00 for control endpoint 17 NAKS NAK status This bit controls the NAK status of USBFS when both STALL bit in this register and GINS bit in USBFS_DCTL register are cleared 0 USBFS sends data or handshake packets according to the status of the endpoint s Tx FIFO 1 USBFS always sends NAK handshake to the IN token This bi...

Page 695: ...hould follow the operation guide to disable or enable an endpoint 30 EPD Endpoint disable Software can set this bit to disable the endpoint Software should following the operation guide to disable or enable an endpoint 29 SODDFRM SD1PID Set odd frame For isochronous IN endpoints This bit has effect only if this is an isochronous IN endpoint Software sets this bit to set EOFRM bit in this register ...

Page 696: ...This bit controls the NAK status of USBFS when both STALL bit in this register and GINS bit in USBFS_DCTL register are are cleared 0 USBFS sends data or handshake packets according to the status of the endpoint s Tx FIFO 1 USBFS always sends NAK handshake to the IN token This bit is read only and software should use CNAK and SNAK in this register to control this bit 16 EOFRM DPID Even odd frame Fo...

Page 697: ...24 23 22 21 20 19 18 17 16 EPEN EPD Reserved SNAK CNAK Reserved STALL SNOOP EPTYPE 1 0 NAKS Reserved rs r w w rs rw r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EPACT Reserved MPL 1 0 r r Bits Fields Descriptions 31 EPEN Endpoint enable Set by the application and cleared by USBFS 0 Endpoint disabled 1 Endpoint enabled Software should follow the operation guide to disable or enable an endpoint 30 EPD ...

Page 698: ...this register and GONS bit in USBFS_DCTL register are cleared 0 USBFS sends data or handshake packets according to the status of the endpoint s Rx FIFO 1 USBFS always sends NAK handshake for the OUT token This bit is read only and software should use CNAK and SNAK in this register to control this bit 16 Reserved Must be kept at reset value 15 EPACT Endpoint active This field is fixed to 1 for endp...

Page 699: ...de to disable or enable an endpoint 29 SODDFRM SD1PID Set odd frame For isochronous OUT endpoints This bit has effect only if this is an isochronous OUT endpoint Software sets this bit to set EOFRM bit in this register Set DATA1 PID For interrupt bulk OUT endpoints Software sets this bit to set DPID bit in this register 28 SEVENFRM SD0PID Set even frame For isochronous OUT endpoints Software sets ...

Page 700: ..._DCTL register are cleared 0 USBFS sends handshake packets according to the status of the endpoint s Rx FIFO 1 USBFS always sends NAK handshake to the OUT token This bit is read only and software should use CNAK and SNAK in this register to control this bit 16 EOFRM DPID Even odd frame For isochronous OUT endpoints For isochronous transfers software can use this bit to control that USBFS only rece...

Page 701: ... read only TXFE bit This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TXFE IEPNE Reserved EPTXFUD CITO Reserved EPDIS TF r rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 TXFE Transmit FIFO empty The Tx FIFO of this IN endpoint has reached the emp...

Page 702: ...egister contains the status and events of an OUT endpoint when an OUT endpoint interrupt occurs read this register for the respective endpoint to know the source of the interrupt The flag bits in this register are all set by hardware and cleared by writing 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 703: ...iggered when all the OUT transactions assigned to this endpoint have been finished Device IN endpoint 0 transfer length register USBFS_DIEP0LEN Address offset 0x0910 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PCNT 1 0 Reserved rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TLEN 6 0 rw Bits Fields Descriptions ...

Page 704: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TLEN 6 0 rw Bits Fields Descriptions 31 Reserved Must be kept at reset value 30 29 STPCNT 1 0 SETUP packet count This field defines the maximum number of back to back SETUP packets this endpoint can accept Program this field before setup transfers Each time a back to back setup packet is received USBFS decrease this field by one When this field reaches ze...

Page 705: ...ister has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MCPF 1 0 PCNT 9 0 TLEN 18 16 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TLEN 15 0 rw Bits Fields Descriptions 31 Reserved Must be kept at reset value 30 29 MCPF 1 0 Multi packet count per frame This field indicates the packet count that must be transmitted per frame for periodic IN endpoints on the US...

Page 706: ...2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RXDPID STPCN T 1 0 PCNT 9 0 TLEN 18 16 r rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TLEN 15 0 rw Bits Fields Descriptions 31 Reserved Must be kept at reset value 30 29 RXDPID 1 0 STPCNT 1 0 Received data PID For isochronous OUT endpoints This field saves the PID of the latest received data packet on this endpoint 00 DATA0 10 DATA1 ...

Page 707: ...s enabled Each time after software reads out a packet from the RxFIFO this field is decreased by the byte size of the packet Device IN endpoint x transmit FIFO status register USBFS_DIEPxTFSTAT x 0 3 where x endpoint_number Address offset 0x0918 endpoint_number 0x20 Reset value 0x0000 0200 This register contains the information of each endpoint s Tx FIFO This register has to be accessed by word 32...

Page 708: ...32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SHCLK SUCLK rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 SHCLK Stop HCLK Stop the HCLK to save power 0 HCLK is not stopped 1 HCLK is stopped 0 SUCLK Stop the USB clock Stop the USB clock to save power 0 USB clock is not stopped 1 USB clock is stopped ...

Page 709: ...eep sleep or standby mode immediately after feeding the dog refers to Function overview 4 In chapter one update table 1 2 integrate the boot loader address together refers to Table 1 2 Memory map of GD32F403xx devices 5 In ADC chapter 12 4 3 add notes about the delay after ADC startup refers to ADCON switch Jun 30 2020 2 3 1 In TIMERx TIMERx x 1 2 3 4 registers modify the description of bits 9 8 r...

Page 710: ...2 and Figure 21 23 Jun 30 2021 2 5 1 Modify the value of max timeout and min timeout in Table 14 1 2 Delete the description of ETM 3 Modify the description of the note below Table 8 24 4 Modify the description of bit15 in the AFIO_PCF0 5 Modify the description of external crystalsparameter from 3 25M to 4 32M 6 Modify the description of ADDSEND bit and MASTER bit in the I2C_STAT0 and I2C_STAT1 Dec...

Page 711: ...y business industrial personal and or householdapplications only TheProducts are not designed intended or authorizedfor use as components in systems designed or intended for the operation of weapons weapons systems nuclear installations atomic energy control instruments combustion control instruments airplane or spaceshipinstruments transportation instruments traffic signal in struments life suppo...

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