GD32F20x User Manual
924
to be transmitted in an OUT transfer. Software should program this field before the
channel is enabled. When software successfully writes a packet into the channel’s
data Tx FIFO, this field is decreased by the byte size of the packet.
For IN transfer each time software or DMA reads out a packet from the RxFIFO,
this field is decreased by the byte size of the packet.
28.7.3.
Device control and status registers
Device configuration register (USBFS_DCFG)
Address offset: 0x0800
Reset value: 0x0000 0000
This register configures the core in device mode after power on, certain control commands or
enumeration. It is not able to change this register after device initialization.
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Rese
rve
d
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rese
rve
d
E
OP
F
T
[1
:0
]
DA
R[6
:0
]
Res
NZ
L
S
OH
DS
[1
:0
]
rw
rw
rw
rw
Bits
Fields
Descriptions
31:13
Reserved
Must be kept at reset value.
12:11
EOPFT[1:0]
End of periodic frame time
This field defines the percentage time point in a frame that the end of periodic
frame (EOPF) flag should be triggered.
00: 80% of the frame time
01: 85% of the frame time
10: 90% of the frame time l
11: 95% of the frame time
10:4
DAR[6:0]
Device address
This field defines the USB device address. USBFS uses this field to match with
the incoming token
’s device address field. Software should program this field after
receiving a set_address command from USB host.
Summary of Contents for GD32F20 Series
Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...
Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...
Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
Page 385: ...GD32F20x User Manual 385 ...
Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...