GD32F20x User Manual
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transaction schedule. A request entry in a request queue described above may represent a
USB transaction request or a channel operation request.
Application needs to write packet into data FIFO via AHB bus if it wants to start an OUT
transaction on USB bus. USBFS hardware will automatically generate a transaction request
entry in request queue after the application writes a whole packet.
The request entries in request queue are processed in order by transaction control module.
USBFS always tries to process periodic request queue firstly and secondly process non-
periodic request queue.
After a start of frame, USBFS begins to process periodic queue until the queue is empty or
bus time required by the current periodic request is not enough, and then process the non-
periodic queue. This strategy ensures the bandwidth of periodic transactions in a frame. Each
time the USBFS reads and pops a request entry from request queue. If the request is a
channel disable request, it immediately disables the channel and prepares to process the
next entry.
If the current request is a transaction request and the USB bus time is enough for this
transaction, USBFS will employ SIE to generate this transaction on USB bus.
When the required bus time for the current request is not enough in the current frame, and
this is a periodic request, USBFS stops processing the periodic queue and starts to process
non-periodic request. If this is a non-periodic queue, the USBFS will stop processing any
queue and wait until the end of current frame.
28.5.3.
USB device function
USB Device Connection
In device mode, USBFS stays at power-off state after initialization. After connecting to a USB
host with a 5V power supply through VBUS pin or setting VBUSIG bit in USBFS_GCCFG
register, USBFS enters into power-on state. In this state, USBFS begins to switch on the pull-
up resistor on DP line and then the host will detect a connection event.
Reset and Speed-Identification
The USB host always starts a USB reset sequence when it detects a device connection, and
USBFS in device mode will trigger a reset interrupt by hardware when it detects the reset
event on USB bus.
After the reset sequence, USBFS will trigger an ENUMF interrupt in USBFS_GINTF register
and report current enumerated device speed by ES bits in USBFS_DSTAT register, the bit
field is always 11(full-speed).
As described in USB 2.0 protocol, USBFS doesn’t support low-speed in device mode.
Suspend and Wake-up
A USB device will enter into suspend state if the USB bus stays at IDLE state and there is no
Summary of Contents for GD32F20 Series
Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...
Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...
Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
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Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...