GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
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Figure 25-12. Mode 2 write access
Address
(EXMC_A[25:0])
Address Valid
(EXMC_NADV)
Chip Enable
(EXMC_NEx)
Output Enable
(EXMC_NOE)
Write Enable
(EXMC_NWE)
Data
(EXMC_D[15:0])
Address Setup Time
(ASET HCLK)
Data Setup Time
(DSET HCLK)
EXMC Output
1 HCLK
Figure 25-13. Mode B write access
Address
(EXMC_A[25:0])
Address Valid
(EXMC_NADV)
Chip Enable
(EXMC_NEx)
Output Enable
(EXMC_NOE)
Write Enable
(EXMC_NWE)
Data
(EXMC_D[15:0])
Address Setup Time
(WASET HCLK)
Data Setup Time
(WDSET HCLK)
EXMC Output
1 HCLK
Table 25-10. Mode 2/B related registers configuration
EXMC_SNCTLx(Mode 2, Mode B)
Bit Position Bit Name Reference Setting Value
31-20 Reserved 0x000
19 SYNCWR 0x0
18-16 Reserved 0x0
15 ASYNCWTEN Depends on memory
14 EXMODEN Mode 2:0x0
，
Mode B:0x1
13 NRWTEN 0x0
12 WEN Depends on user
11 NRWTCFG No effect
10 WRAPEN 0x0
9 NRWTPOL Meaningful only when the bit 15 is set to 1
8 SBRSTEN 0x0
7 Reserved 0x1
6 NREN 0x1
5-4 NRW Depends on memory