GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
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Reset generated when entering Deep-sleep mode when resetting nRST_DPSLP bit in
user option bytes (OB_DPSLP_RSTn).
A system reset resets the processor core and peripheral IP components except for the SW-
DP controller and the backup domain.
A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset
source (external or internal reset).
Figure 5-1. The system reset circuit
Filt er
WWDGT_RSTn
FWDGT_RSTn
SW_RSTn
OB_STDBY_RSTn
OB_DPSLP_RSTn
PO WER_RSTn
NRST
Syst em Reset
min 20 us
pulse
generator
OBL_RSTn
Backup domain reset
A backup domain reset is generated by setting the BKPRST bit in the backup domain control
register or backup domain power on reset (V
DD
or V
BAT
power on, if both supplies have
previously been powered off).
5.2. Clock control unit (CCTL)
5.2.1.
Overview
The clock control unit provides a range of frequencies and clock functions. These include an
Internal 8M RC oscillator (IRC8M), a High Speed crystal oscillator (HXTAL), a Low Speed
Internal 40K RC oscillator (IRC40K), a Low Speed crystal oscillator (LXTAL), a Phase Lock
Loop (PLL), a HXTAL clock monitor, clock prescalers, clock multiplexers and clock gating
circuitry.
The clocks of the AHB, APB and Cortex
®
-M3 are derived from the system clock (CK_SYS)
which can source from the IRC8M, HXTAL or PLL. The maximum operating frequency of the
system clock (CK_SYS) can be up to 108 MHz.