GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
591
Asynchronous access timing diagram
Mode 1 - SRAM/CRAM
Figure 20-6. Mode 1 read access
Address
(EXMC_A[25:0])
Byte Lane Select
(EXMC_NBL[1:0])
Chip Enable
(EXMC_NEx)
Output Enable
(EXMC_NOE)
Write Enable
(EXMC_NWE)
Data
(EXMC_D[15:0])
Memory Output
Address Setup Time
(ASET+1 HCLK)
Data Setup Time
(DSET+1 HCLK)
2 HCLK
Figure 20-7. Mode 1 write access
Address
(EXMC_A[25:0])
Byte Lane Select
(EXMC_NBL[1:0])
Chip Enable
(EXMC_NEx)
Output Enable
(EXMC_NOE)
Write Enable
(EXMC_NWE)
Data
(EXMC_D[15:0])
Address Setup Time
(ASET+1 HCLK)
Data Setup Time
(DSET HCLK)
EXMC Output
1 HCLK
Table 20-6. Mode 1 related registers configuration
Bit Position Bit Name Reference Setting Value
EXMC_SNCTLx
31-20 Reserved 0x000
19 SYNCWR 0x0
18-16 Reserved 0x0
15 ASYNCWAIT Depends on memory
14 EXMODEN 0x0
13 NRWTEN 0x0
12 WREN Depends on user
11 NRWTCFG No effect
10 WRAPEN 0x0
9 NRWTPOL Meaningful only when the bit 15 is set to 1