GigaDevice Semiconductor GD32F10 Series, User Manual

Page: 135 / 853

GD32F10x User Manual
135
5.6.8.
APB1 enable register (RCU_APB1EN)
Address offset: 0x1C
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved DACEN PMUEN BKPIEN CAN1EN CAN0EN Reserved I2C1EN I2C0EN
UART4E
N
UART3E
N
USART2
EN
USART1
EN
Reserved
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2EN SPI1EN Reserved
WWDGT
EN
Reserved
TIMER6E
N
TIMER5E
N
TIMER4E
N
TIMER3E
N
TIMER2E
N
TIMER1E
N
rw rw rw rw rw rw rw rw rw
Bits Fields Descriptions
31:30 Reserved Must be kept at reset value
29 DACEN DAC clock enable
This bit is set and reset by software.
0: Disabled DAC clock
1: Enabled DAC clock
28 PMUEN PMU clock enable
This bit is set and reset by software.
0: Disabled PMU clock
1: Enabled PMU clock
27 BKPIEN Backup interface clock enable
This bit is set and reset by software.
0: Disabled backup interface clock
1: Enabled backup interface clock
26 CAN1EN CAN1 clock enable
This bit is set and reset by software.
0: Disabled CAN1 clock
1: Enabled CAN1 clock
25 CAN0EN CAN0 clock enable
This bit is set and reset by software.
0: Disabled CAN0 clock
1: Enabled CAN0 clock
24:23 Reserved Must be kept at reset value
22 I2C1EN I2C1 clock enable
This bit is set and reset by software.