GD32E23x User Manual
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is from module RCU.
The default clock source is the CK_TIMER for driving the counter prescaler when the SMC
[2:0] == 3’b000. When the CEN is set, the CK_TIMER will be divided by PSC value to
generate PSC_CLK.
In this mode, the TIMER_CK, which drives counter’s prescaler to count, is equal to
CK_TIMER which is from RCU.
If the SMC [2:0] in the TIMERx_SMCFG register are setting to an available value 0x7, the
prescaler is clocked by other clock sources selected by the TRGS [2:0] in the
TIMERx_SMCFG register, details as follows. When the SMC [2:0] bits are set to 0x4, 0x5 or
0x6, the internal clock CK_TIMER is the counter prescaler driving clock source.
Figure 14-54.
Timing chart of internal clock divided by 1
CK_TIMER
CEN
PSC_CLK = TIMER_CK
CNT_REG
Reload Pulse
17
18
19
20
21
22
update event
generate(UPG)
23
00
01
02
03
04
05
06
07
Update event (UPE)
SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer
clock source
The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of
rising or falling edge on the external pin TIMERx_CH0/TIMERx_CH1. This mode can be
selected by setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x4, 0x5 or 0x6.
And, the counter prescaler can also be driven by rising edge on the internal trigger input pin
ITI0/1/2/3. This mode can be selected by setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x0,
0x1, 0x2 or 0x3.
Clock prescaler
The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the
prescale factor can be configured from 1 to 65536 through the prescaler register
(TIMERx_PSC). The new written prescaler value will not take effect until the next update
event.
