User Manual
GD32107C-EVAL
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4.5
USART1/USART2
Figure 5. Schematic diagram of USART1/USART2 function
C1+
1
V+
2
C1-
3
C2+
4
C2-
5
V-
6
T2OUT
7
R2IN
8
R2OUT
9
T2IN
10
T1IN
11
R1OUT
12
R1IN
13
T1OUT
14
GND
15
VCC
16
U3
MAX
+3V3
GND
C23
50V/0.1uF
C25
50V/0.1uF
C24
50V/0.1uF
C22
50V/0.1uF
C21
50V/0.1uF
GND
1
6
2
7
3
8
4
9
5
J1
COM2
GND
USART2_TX
USART2_TX
USART2_RX
USART1_TX
USART1_RX
USART1_TX
USART1_RX
1
6
2
7
3
8
4
9
5
J2
COM1
GND
USART1/USART2
RS232_TX2
RS232_RX2
PA3
PA2
1
2
3
JP5
HEADER 3
1
2
3
JP6
HEADER 3
PA9
PA10
USB_VBUS
USB_ID
Short JP5(2,3),Short JP6(2,3) for USB OTG function
RS232_TX1
RS232_RX1
1
2
3
JP4
HEADER 3
RMII_MDIO
Short JP4(2,3)for USART2 function
Short JP5(1,2),Short JP6(1,2) for USART1 function
Short JP4(1,2) for Ethernet function
4.6
ADC/DAC
Figure 6. Schematic diagram of ADC/DAC function
+3V3
GND
ADC
PA4
DAC
DAC_OUT1
DAC_OUT2
C27
50V/0.1uF
R12
1K
Ω
PC3
VR1
10K
1
TP2
TP ADin
PA5 is an AFIO, please refer to SPI Schematic for right configuration.
PA5
ADC123_IN13
1
2
3
JP7
DAC
GND
