AN050
GD32 USBFS&USBHS Firmware Library User Guide
26
case
RSTAT_SETUP_COMP
:
/* trigger the OUT endpoint interrupt */
break
;
case
RSTAT_SETUP_UPDT
:
if
((
0U
==
transc
->
ep_addr
.
num
)
&&
(
8U
==
bcount
)
&&
(
DPID_DATA0
==
data_PID
))
{
/* copy the setup packet received in FIFO into the setup buffer in RAM */
(
void
)
usb_rxfifo_read
(&
udev
->
regs
,
(
uint8_t
*)&
udev
->
dev
.
control
.
req
,
(
uint16_t
)
bcount
); // read FIFO
transc
->
xfer_count
+=
bcount
;
}
break
;
default
:
break
;
}
/* enable the Rx status queue level interrupt */
udev
->
regs
.
gr
->
GINTEN
|=
GINTEN_RXFNEIE
;
return
1U
;
}
In interrupt handler function of Rx FIFO non empty, mainly process FIFO data receiving,
include SETUP transaction interrupt and OUT transaction interrupt.
5.5.
USB Device Class Interface
The USB device class interface is implemented by the following architecture:
typedef
struct
_usb_class_core
{
uint8_t
command
;
/*!<
device class request command */
uint8_t
alter_set
;
/*!<
alternative set */
uint8_t
(*
init
)
(
usb_dev
*
udev
,
uint8_t
config_index
);
/*!< initialize
handler */
uint8_t
(*
deinit
)
(
usb_dev
*
udev
,
uint8_t
config_index
);
/*!< de-initialize
handler */
