Giga-tronics 80350A, Operation & Maintenance Manual

Page: 48 / 110

Series 8035XA Peak Power Sensors
3-6 Manual 21568, Rev. F, March 2008
3.3.2 Description
When READY (TP17) is true, U8B flip-flop (TP14 - TRIG) is set after TRIG-IN goes high. U13
delays the TRIGgered signal by a delay programmed in 1/2 ns intervals. U3 is a 10-MHz gated
delay line oscillator which, when enabled by the fine delay, clocks (TP1) the coarse counter U1,
U5, U6, U15 and U16, and the SAMPLE flip-flops U7B and U8A. Unlike conventional oscillators
which free run, a gated delay line oscillator beginning time period is the same length as all of its
other time periods with the possible exception of the last period when enable is unasserted.
When RCO (TP8) is true for one clock cycle (ignores pulses less than 100 ns), U7B is latched
as SAMPle (TP11). SAMPle is delayed by one count because 51
µ
s (TP7) can still be true when
SAMPle goes true, and AND’d with 51
µ
s from U1. When true (when SAMPle has been on for
51
µ
s), the U10A loader receives a negative edge clock. LOAD for the COARSE counter is
asserted and held low via U9C, R34, and C27 until the 10-MHz clock (U3) stops via U12A,
U10B, (TP9), U4A, and U4C. Note the sequence:
1. CTR-CLK (TP1) must be running.
2. LOAD-CTR (TP9) goes low and stays low while CTR-CLK continues for at least one cycle.
This loads the COARSE counter.
3. CTR-CLK (TP1) stops. LOAD-CTR is still low. CTR-CLK continues in the CW mode.
4. LOAD-CTR returns high at least 200 ns before POST (TP5) returns high. The same FINE delay
which delayed the start of the 10-MHz clock now works against turning the 10-MHz clock off.
SAMP (TP11) going high turns the Track and Hold (T&H) to Hold on the Analog board, and
turns the Sample and Hold (S&H) to Sample. When it goes low, the T&H goes back to tracking
the input and the S&H holds the sampled signal level. U10B POST (TP5), the major reset
circuit, resets READY (TP17) to prevent the trigger circuit from restarting, continues to reset
TRIG (TP14) (except in the CW mode) which started in PRE-POST, and resets SAMP (TP11).
When the host has read the data, the DATA-IN line is momentarily pulsed low by the host which
sets READY (TP17), and pulls the DATA-IN line (TP20) low via diode CR3. Note that the
DATA-IN — READY handshake does not occur in the CW mode.
EEPROM U11 stores the sensor type, serial number, and calibration constants. This IC is only
accessed by the host. Except for device start and stop conditions, DATA-IN can change states
only when CLK is low. After device stop has been sent, the host sends a 48-bit serial stream to
set up the 80350A sensor. Four zeros are sent followed by the 12 DAC trigger bits, followed by
the fine counter 8 bits, 20 bits for the COARSE counter (with FFFFF meaning zero delay), and
finally the 4 control bits (INTernal, EXTernal, CW, and HIGHGAIN). Because the serial DAC on
the ANALOG board has a data hold requirement of 80 ns minimum, DATA-4 (TP2) must be
delayed by R12 and C25.
Incoming CLK turns on U3 (10 MHz - TP1) and U9C (LOAD) (TP9) via U12B (CLKHOLD)
which loads the COARSE counter with the new delay.
The test points are essentially in order across the length of both the Analog and Digital boards
in the approximate order of signal progression to aid in troubleshooting. In addition, the
between-the-board connectors can be used as test points.