GIGA-BYTE TECHNOLOGY G492-Z50, User Manual, Page: 120 / 141

BIOS Setup - 120 -
5-10 ABL POST Codes
5-10-1 Start Processor Test Points
Entry used for range testing for @b Processor related TPs 0xE000
5-10-2 Memory test points
Memory structure initialization (Public interface) 0xE001
SPD Data processing (Public interface) 0xE002
Memory configuration (Public interface) Phase 1 0xE003
DRAM initialization 0xE004
ProcMemSPDChecking 0xE005
ProcMemModeChecking 0xE006
Speed and TCL configuration 0xE007
ProcMemSpdTiming 0xE008
ProcMemDramMapping 0xE009
ProcMemPlatformSpecificConfig 0xE00A
ProcMemPhyCompensation 0xE00B
ProcMemStartDcts 0xE00C
ProcMemBeforeDramInit (Public interface) 0xE00D
ProcMemPhyFenceTraining 0xE00E
ProcMemSynchronizeDcts 0xE00F
ProcMemSystemMemoryMapping 0xE010
ProcMemMtrrConfiguration 0xE011
ProcMemDramTraining 0xE012
ProcMemBeforeAnyTraining(Public interface) 0xE013
5-10-3 PMU Test Points
ABL Mem - PMU - Before PMU Firmware load 0xE014
ABL Mem - PMU - After PMU Firmware load 0xE015
ABL Mem - PMU Populate SRAM Timing 0xE016
ABL Mem - PMU Populate SRAM Config 0xE017
ABL Mem - PMU Write SRAM Msg Block 0xE018
ABL Mem - Wait for Phy Cal Complete 0xE019
ABL Mem - Phy Cal Complete 0xE01A
ABL Mem - PMU Start 0xE01B
ABL Mem - PMU Started 0xE01C
ABL Mem - PMU Waiting for Complete 0xE01D
ABL Mem - PMU Stage Dec Init 0xE01E
ABL Mem - PMU Stage Training Wr Lvl 0xE01F
ABL Mem - PMU Stage Training Rx En 0xE020
ABL Mem - PMU Stage Training Rd Dqs 0xE021
ABL Mem - PMU Stage Training Rd 2D 0xE022