28
Rev NR
CHAPTER 5: HARDWARE CONFIGURATION
5.0
Board Layout
The following figure is a drawing of the physical components of the PCIe4-SIO8BX2:
USC
USC
J1
P
C
Ie
4
-S
IO
4
B
X
2
R
E
V
B
G
E
N
E
R
A
L
S
T
A
N
D
A
R
D
S
C
O
R
P
.
(C
)2
0
1
2
P
2
7
1
2
8
D2
D1
RP1
USC
USC
PCIe
Bridge
PCI Bridge
PCI Bridge
FPGA
FPGA
J2
RP2
RP4
RP6
RP8
RP9
RP10
RP12
RP14
RP15
RP16
RP18
RP20
RP21
RP22
RP23
D4
D3
D13
D12
D7
D6
D9
D8
D11
D5
D10
Figure 5-1: Board Layout – Top
5.1
Board ID Jumper J1
Jumper J1 allows the user to set the Board ID in the GSC Board Status Register (See Section 2.1.3). This is useful to
uniquely identify a board if more than one SIO8BX2 card is in a system. When the Board ID jumper is installed, it
will read ‘1’ in the Board Status Register. The Board Status Register bit will report ‘0’ when the jumper is removed.
Refer to Figure 5-1 for Jumper J1 location.
J1 Jumper
Description
Notes
1 - 2
Board ID 1
Board ID 1 in Board Status Register (D0)
3 - 4
Board ID 2
Board ID 2 in Board Status Register (D1)
5 - 6
Board ID 3
Board ID 3 in Board Status Register (D2)
7 - 8
Board ID 4
Board ID 4 in Board Status Register (D3)
